misc: Rename SimClock namespace as sim_clock

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::SimClock became ::sim_clock.

Change-Id: I25b8cfc93f283081bc2add9fdef6fec7d7ff3846
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45402
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>

src/arch/arm/fastmodel/CortexA76/evs.cc

@@ -41,7 +41,7 @@ template <class Types>
 void
 ScxEvsCortexA76<Types>::setClkPeriod(Tick clk_period)
 {
-    clockRateControl->set_mul_div(SimClock::Int::s, clk_period);
+    clockRateControl->set_mul_div(sim_clock::Int::s, clk_period);
 }
 
 template <class Types>

src/arch/arm/fastmodel/CortexR52/evs.cc

@@ -40,7 +40,7 @@ template <class Types>
 void
 ScxEvsCortexR52<Types>::setClkPeriod(Tick clk_period)
 {
-    clockRateControl->set_mul_div(SimClock::Int::s, clk_period);
+    clockRateControl->set_mul_div(sim_clock::Int::s, clk_period);
 }
 
 template <class Types>

src/arch/arm/fastmodel/PL330_DMAC/pl330.cc

@@ -255,7 +255,7 @@ void
 PL330::start_of_simulation()
 {
     // Set the clock rate using the divider inside the EVS.
-    clockRateControl->set_mul_div(SimClock::Int::s, clockPeriod);
+    clockRateControl->set_mul_div(sim_clock::Int::s, clockPeriod);
 }
 
 } // namespace FastModel

src/arch/arm/semihosting.cc

@@ -500,13 +500,13 @@ ArmSemihosting::callRename(ThreadContext *tc, Addr from_addr, size_t from_size,
 ArmSemihosting::RetErrno
 ArmSemihosting::callClock(ThreadContext *tc)
 {
-    return retOK(curTick() / (SimClock::Int::s / 100));
+    return retOK(curTick() / (sim_clock::Int::s / 100));
 }
 
 ArmSemihosting::RetErrno
 ArmSemihosting::callTime(ThreadContext *tc)
 {
-    return retOK(timeBase + round(curTick() / SimClock::Float::s));
+    return retOK(timeBase + round(curTick() / sim_clock::Float::s));
 }
 
 ArmSemihosting::RetErrno
@@ -672,7 +672,7 @@ ArmSemihosting::callElapsed64(ThreadContext *tc, InPlaceArg ticks)
 ArmSemihosting::RetErrno
 ArmSemihosting::callTickFreq(ThreadContext *tc)
 {
-    return retOK(semiTick(SimClock::Frequency));
+    return retOK(semiTick(sim_clock::Frequency));
 }
 
 

src/arch/arm/semihosting.hh

@@ -414,7 +414,7 @@ class ArmSemihosting : public SimObject
     unsigned
     calcTickShift() const
     {
-        int msb = findMsbSet(SimClock::Frequency);
+        int msb = findMsbSet(sim_clock::Frequency);
         return msb > 31 ? msb - 31 : 0;
     }
     uint64_t

src/base/time.cc

@@ -53,17 +53,17 @@ Time::_set(bool monotonic)
 void
 Time::setTick(Tick ticks)
 {
-    uint64_t secs = ticks / SimClock::Frequency;
-    ticks -= secs * SimClock::Frequency;
-    uint64_t nsecs = static_cast<uint64_t>(ticks * SimClock::Float::GHz);
+    uint64_t secs = ticks / sim_clock::Frequency;
+    ticks -= secs * sim_clock::Frequency;
+    uint64_t nsecs = static_cast<uint64_t>(ticks * sim_clock::Float::GHz);
     set(secs, nsecs);
 }
 
 Tick
 Time::getTick() const
 {
-    return sec() * SimClock::Frequency +
-        static_cast<uint64_t>(nsec() * SimClock::Float::ns);
+    return sec() * sim_clock::Frequency +
+        static_cast<uint64_t>(nsec() * sim_clock::Float::ns);
 }
 
 std::string

src/cpu/inst_pb_trace.cc

@@ -86,7 +86,7 @@ InstPBTrace::createTraceFile(std::string filename)
     ProtoMessage::InstHeader header_msg;
     header_msg.set_obj_id("gem5 generated instruction trace");
     header_msg.set_ver(0);
-    header_msg.set_tick_freq(SimClock::Frequency);
+    header_msg.set_tick_freq(sim_clock::Frequency);
     header_msg.set_has_mem(true);
     traceStream->write(header_msg);
 

src/cpu/kvm/timer.hh

@@ -129,7 +129,7 @@ class BaseKvmTimer
      * @return Nanoseconds executed in VM converted to simulation ticks
      */
     Tick ticksFromHostNs(uint64_t ns) {
-        return ns * hostFactor * SimClock::Float::ns;
+        return ns * hostFactor * sim_clock::Float::ns;
     }
 
   protected:
@@ -147,7 +147,7 @@ class BaseKvmTimer
      * @return Simulation ticks converted into nanoseconds on the host
      */
     uint64_t hostNs(Tick ticks) {
-        return ticks / (SimClock::Float::ns * hostFactor);
+        return ticks / (sim_clock::Float::ns * hostFactor);
     }
 
     /**

src/cpu/kvm/x86_cpu.cc

@@ -1248,7 +1248,7 @@ X86KvmCPU::kvmRunDrain()
         // Limit the run to 1 millisecond. That is hopefully enough to
         // reach an interrupt window. Otherwise, we'll just try again
         // later.
-        return BaseKvmCPU::kvmRun(1 * SimClock::Float::ms);
+        return BaseKvmCPU::kvmRun(1 * sim_clock::Float::ms);
     } else {
         DPRINTF(Drain, "kvmRunDrain: Delivering pending IO\n");
 

src/cpu/o3/probe/elastic_trace.cc

@@ -87,13 +87,13 @@ ElasticTrace::ElasticTrace(const ElasticTraceParams &params)
     // Create a protobuf message for the header and write it to the stream
     ProtoMessage::PacketHeader inst_pkt_header;
     inst_pkt_header.set_obj_id(name());
-    inst_pkt_header.set_tick_freq(SimClock::Frequency);
+    inst_pkt_header.set_tick_freq(sim_clock::Frequency);
     instTraceStream->write(inst_pkt_header);
     // Create a protobuf message for the header and write it to
     // the stream
     ProtoMessage::InstDepRecordHeader data_rec_header;
     data_rec_header.set_obj_id(name());
-    data_rec_header.set_tick_freq(SimClock::Frequency);
+    data_rec_header.set_tick_freq(sim_clock::Frequency);
     data_rec_header.set_window_size(depWindowSize);
     dataTraceStream->write(data_rec_header);
     // Register a callback to flush trace records and close the output streams.

src/cpu/testers/traffic_gen/trace_gen.cc

@@ -57,7 +57,7 @@ TraceGen::InputStream::init()
     ProtoMessage::PacketHeader header_msg;
     if (!trace.read(header_msg)) {
         panic("Failed to read packet header from trace\n");
-    } else if (header_msg.tick_freq() != SimClock::Frequency) {
+    } else if (header_msg.tick_freq() != sim_clock::Frequency) {
         panic("Trace was recorded with a different tick frequency %d\n",
               header_msg.tick_freq());
     }

src/cpu/trace/trace_cpu.cc

@@ -1202,7 +1202,7 @@ TraceCPU::ElasticDataGen::InputStream::InputStream(
     if (!trace.read(header_msg)) {
         panic("Failed to read packet header from %s\n", filename);
 
-        if (header_msg.tick_freq() != SimClock::Frequency) {
+        if (header_msg.tick_freq() != sim_clock::Frequency) {
             panic("Trace %s was recorded with a different tick frequency %d\n",
                   header_msg.tick_freq());
         }
@@ -1383,7 +1383,7 @@ TraceCPU::FixedRetryGen::InputStream::InputStream(const std::string& filename)
     if (!trace.read(header_msg)) {
         panic("Failed to read packet header from %s\n", filename);
 
-        if (header_msg.tick_freq() != SimClock::Frequency) {
+        if (header_msg.tick_freq() != sim_clock::Frequency) {
             panic("Trace %s was recorded with a different tick frequency %d\n",
                   header_msg.tick_freq());
         }

src/dev/arm/energy_ctrl.cc

@@ -99,7 +99,7 @@ EnergyCtrl::read(PacketPtr pkt)
         break;
       case DVFS_HANDLER_TRANS_LATENCY:
         // Return transition latency in nanoseconds
-        result = dvfsHandler->transLatency() / SimClock::Int::ns;
+        result = dvfsHandler->transLatency() / sim_clock::Int::ns;
         DPRINTF(EnergyCtrl, "reading dvfs handler trans latency %d ns\n",
                 result);
         break;

src/dev/arm/energy_ctrl.hh

@@ -164,7 +164,7 @@ class EnergyCtrl : public BasicPioDevice
     uint32_t perfLevelToRead;
 
     static uint32_t ticksTokHz(Tick period) {
-        return (uint32_t)(SimClock::Int::ms / period);
+        return (uint32_t)(sim_clock::Int::ms / period);
     }
 
     static uint32_t toMicroVolt(double voltage) {

src/dev/arm/generic_timer.cc

@@ -74,7 +74,7 @@ SystemCounter::SystemCounter(const SystemCounterParams &p)
         "frequency table entries, limit surpassed\n");
     // Set the active frequency to be the base
     _freq = _freqTable.front();
-    _period = (1.0 / _freq) * SimClock::Frequency;
+    _period = (1.0 / _freq) * sim_clock::Frequency;
 }
 
 void
@@ -187,7 +187,7 @@ SystemCounter::freqUpdateCallback()
     _activeFreqEntry = _nextFreqEntry;
     _freq = _freqTable[_activeFreqEntry];
     _increment = _freqTable[0] / _freq;
-    _period = (1.0 / _freq) * SimClock::Frequency;
+    _period = (1.0 / _freq) * sim_clock::Frequency;
     notifyListeners();
 }
 
@@ -244,7 +244,7 @@ SystemCounter::unserialize(CheckpointIn &cp)
     }
     UNSERIALIZE_SCALAR(_nextFreqEntry);
 
-    _period = (1.0 / _freq) * SimClock::Frequency;
+    _period = (1.0 / _freq) * sim_clock::Frequency;
 }
 
 ArchTimer::ArchTimer(const std::string &name,

src/dev/arm/rtc_pl031.cc

@@ -69,7 +69,7 @@ PL031::read(PacketPtr pkt)
 
     switch (daddr) {
       case DataReg:
-        data = timeVal + ((curTick() - lastWrittenTick) / SimClock::Int::s);
+        data = timeVal + ((curTick() - lastWrittenTick) / sim_clock::Int::s);
         break;
       case MatchReg:
         data = matchVal;
@@ -154,7 +154,7 @@ PL031::resyncMatch()
             timeVal);
 
     uint32_t seconds_until = matchVal - timeVal;
-    Tick ticks_until = SimClock::Int::s * seconds_until;
+    Tick ticks_until = sim_clock::Int::s * seconds_until;
 
     if (matchEvent.scheduled()) {
         DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");

src/dev/arm/rv_ctrl.cc

@@ -66,12 +66,12 @@ RealViewCtrl::read(PacketPtr pkt)
         break;
       case Clock24:
         Tick clk;
-        clk = SimClock::Float::MHz * curTick() * 24;
+        clk = sim_clock::Float::MHz * curTick() * 24;
         pkt->setLE((uint32_t)(clk));
         break;
       case Clock100:
         Tick clk100;
-        clk100 = SimClock::Float::MHz * curTick() * 100;
+        clk100 = sim_clock::Float::MHz * curTick() * 100;
         pkt->setLE((uint32_t)(clk100));
         break;
       case Flash:
@@ -239,9 +239,9 @@ RealViewOsc::RealViewOsc(const RealViewOscParams &p)
       RealViewCtrl::Device(*p.parent, RealViewCtrl::FUNC_OSC,
                            p.site, p.position, p.dcc, p.device)
 {
-    if (SimClock::Float::s  / p.freq > UINT32_MAX) {
+    if (sim_clock::Float::s  / p.freq > UINT32_MAX) {
         fatal("Oscillator frequency out of range: %f\n",
-            SimClock::Float::s  / p.freq / 1E6);
+            sim_clock::Float::s  / p.freq / 1E6);
     }
 
     _clockPeriod = p.freq;
@@ -286,7 +286,7 @@ RealViewOsc::clockPeriod(Tick clock_period)
 uint32_t
 RealViewOsc::read() const
 {
-    const uint32_t freq(SimClock::Float::s / _clockPeriod);
+    const uint32_t freq(sim_clock::Float::s / _clockPeriod);
     DPRINTF(RVCTRL, "Reading OSC frequency: %f MHz\n", freq / 1E6);
     return freq;
 }
@@ -295,7 +295,7 @@ void
 RealViewOsc::write(uint32_t freq)
 {
     DPRINTF(RVCTRL, "Setting new OSC frequency: %f MHz\n", freq / 1E6);
-    clockPeriod(SimClock::Float::s / freq);
+    clockPeriod(sim_clock::Float::s / freq);
 }
 
 uint32_t

src/dev/intel_8254_timer.cc

@@ -271,7 +271,7 @@ Intel8254Timer::Counter::startup()
 
 Intel8254Timer::Counter::CounterEvent::CounterEvent(Counter* c_ptr)
 {
-    interval = (Tick)(SimClock::Float::s / 1193180.0);
+    interval = (Tick)(sim_clock::Float::s / 1193180.0);
     counter = c_ptr;
 }
 

src/dev/mc146818.cc

@@ -175,7 +175,7 @@ MC146818::writeData(const uint8_t addr, const uint8_t data)
                   // from reset to active. So, we simply schedule the
                   // tick after 0.5s.
                   assert(!tickEvent.scheduled());
-                  schedule(tickEvent, curTick() + SimClock::Int::s / 2);
+                  schedule(tickEvent, curTick() + sim_clock::Int::s / 2);
               }
           } break;
           case RTC_STAT_REGB:
@@ -333,7 +333,7 @@ void
 MC146818::RTCTickEvent::process()
 {
     DPRINTF(MC146818, "RTC clock tick\n");
-    parent->schedule(this, curTick() + SimClock::Int::s);
+    parent->schedule(this, curTick() + sim_clock::Int::s);
     parent->tickClock();
 }
 

src/dev/mc146818.hh

@@ -70,7 +70,7 @@ class MC146818 : public EventManager
         Tick offset;
 
         RTCTickEvent(MC146818 * _parent) :
-            parent(_parent), offset(SimClock::Int::s)
+            parent(_parent), offset(sim_clock::Int::s)
         {}
 
         /** Event process to occur at interrupt*/

src/dev/mips/malta_io.cc

@@ -72,7 +72,7 @@ MaltaIO::MaltaIO(const Params &p)
 Tick
 MaltaIO::frequency() const
 {
-    return SimClock::Frequency / params().frequency;
+    return sim_clock::Frequency / params().frequency;
 }
 
 Tick

src/dev/net/etherdump.cc

@@ -94,8 +94,8 @@ void
 EtherDump::dumpPacket(EthPacketPtr &packet)
 {
     pcap_pkthdr pkthdr;
-    pkthdr.seconds = curTick() / SimClock::Int::s;
-    pkthdr.microseconds = (curTick() / SimClock::Int::us) % 1000000ULL;
+    pkthdr.seconds = curTick() / sim_clock::Int::s;
+    pkthdr.microseconds = (curTick() / sim_clock::Int::us) % 1000000ULL;
     pkthdr.caplen = std::min(packet->length, maxlen);
     pkthdr.len = packet->length;
     stream->write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr));

src/dev/net/etherswitch.cc

@@ -182,7 +182,7 @@ EtherSwitch::Interface::transmit()
     if (!sendPacket(outputFifo.front())) {
         DPRINTF(Ethernet, "output port busy...retry later\n");
         if (!txEvent.scheduled())
-            parent->schedule(txEvent, curTick() + SimClock::Int::ns);
+            parent->schedule(txEvent, curTick() + sim_clock::Int::ns);
     } else {
         DPRINTF(Ethernet, "packet sent: len=%d\n", outputFifo.front()->length);
         outputFifo.pop();

src/dev/net/ethertap.cc

@@ -194,7 +194,7 @@ EtherTapBase::sendSimulated(void *data, size_t len)
         DPRINTF(Ethernet, "bus busy...buffer for retransmission\n");
         packetBuffer.push(packet);
         if (!txEvent.scheduled())
-            schedule(txEvent, curTick() + SimClock::Int::ns);
+            schedule(txEvent, curTick() + sim_clock::Int::ns);
     } else if (dump) {
         dump->dump(packet);
     }
@@ -216,7 +216,7 @@ EtherTapBase::retransmit()
     }
 
     if (!packetBuffer.empty() && !txEvent.scheduled())
-        schedule(txEvent, curTick() + SimClock::Int::ns);
+        schedule(txEvent, curTick() + sim_clock::Int::ns);
 }
 
 

src/dev/net/i8254xGBe.cc

@@ -699,7 +699,7 @@ IGbE::postInterrupt(IntTypes t, bool now)
 
     regs.icr = regs.icr() | t;
 
-    Tick itr_interval = SimClock::Int::ns * 256 * regs.itr.interval();
+    Tick itr_interval = sim_clock::Int::ns * 256 * regs.itr.interval();
     DPRINTF(EthernetIntr,
             "EINT: postInterrupt() curTick(): %d itr: %d interval: %d\n",
             curTick(), regs.itr.interval(), itr_interval);
@@ -807,7 +807,8 @@ IGbE::chkInterrupt()
             DPRINTF(Ethernet,
                     "Possibly scheduling interrupt because of imr write\n");
             if (!interEvent.scheduled()) {
-                Tick t = curTick() + SimClock::Int::ns * 256 * regs.itr.interval();
+                Tick t = curTick() +
+                    sim_clock::Int::ns * 256 * regs.itr.interval();
                 DPRINTF(Ethernet, "Scheduling for %d\n", t);
                 schedule(interEvent, t);
             }

src/dev/net/i8254xGBe.hh

@@ -163,7 +163,7 @@ class IGbE : public EtherDevice
      */
     void cpuClearInt();
 
-    Tick intClock() { return SimClock::Int::ns * 1024; }
+    Tick intClock() { return sim_clock::Int::ns * 1024; }
 
     /** This function is used to restart the clock so it can handle things like
      * draining and resume in one place. */

src/dev/net/ns_gige.cc

@@ -1395,7 +1395,7 @@ NSGigE::transmit()
 
    if (!txFifo.empty() && !txEvent.scheduled()) {
        DPRINTF(Ethernet, "reschedule transmit\n");
-       schedule(txEvent, curTick() + SimClock::Int::ns);
+       schedule(txEvent, curTick() + sim_clock::Int::ns);
    }
 }
 

src/dev/serial/uart8250.cc

@@ -72,7 +72,7 @@ Uart8250::processIntrEvent(int intrBit)
 void
 Uart8250::scheduleIntr(Event *event)
 {
-    static const Tick interval = 225 * SimClock::Int::ns;
+    static const Tick interval = 225 * sim_clock::Int::ns;
     DPRINTF(Uart, "Scheduling IER interrupt for %s, at cycle %lld\n",
             event->name(), curTick() + interval);
     if (!event->scheduled())
@@ -179,7 +179,7 @@ Uart8250::writeIer(Register<Ier> &reg, const Ier &ier)
 
     if (ier.thri) {
         DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
-        if (curTick() - lastTxInt > 225 * SimClock::Int::ns) {
+        if (curTick() - lastTxInt > 225 * sim_clock::Int::ns) {
             DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n",
                     curTick(), lastTxInt);
             txIntrEvent.process();

src/gpu-compute/gpu_compute_driver.cc

@@ -284,7 +284,7 @@ GPUComputeDriver::ioctl(ThreadContext *tc, unsigned req, Addr ioc_buf)
              * Derive all clock counters based on the tick. All
              * device clocks are identical and perfectly in sync.
              */
-            uint64_t elapsed_nsec = curTick() / SimClock::Int::ns;
+            uint64_t elapsed_nsec = curTick() / sim_clock::Int::ns;
             args->gpu_clock_counter = elapsed_nsec;
             args->cpu_clock_counter = elapsed_nsec;
             args->system_clock_counter = elapsed_nsec;

src/kern/freebsd/events.cc

@@ -57,7 +57,7 @@ onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t time)
     // time to 0 with the assumption that quiesce will not happen. To avoid
     // the quiesce handling in this case, only execute the quiesce if time > 0.
     if (time > 0)
-        tc->quiesceTick(curTick() + SimClock::Int::ns * time);
+        tc->quiesceTick(curTick() + sim_clock::Int::ns * time);
 }
 
 } // namespace FreeBSD

src/kern/linux/events.cc

@@ -90,7 +90,7 @@ onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t time)
     // time to 0 with the assumption that quiesce will not happen. To avoid
     // the quiesce handling in this case, only execute the quiesce if time > 0.
     if (time > 0)
-        tc->quiesceTick(curTick() + SimClock::Int::ns * time);
+        tc->quiesceTick(curTick() + sim_clock::Int::ns * time);
 }
 
 } // namespace linux

src/mem/cache/tags/base.cc

@@ -167,13 +167,13 @@ BaseTags::computeStatsVisitor(CacheBlk &blk)
         Tick age = blk.getAge();
 
         int age_index;
-        if (age / SimClock::Int::us < 10) { // <10us
+        if (age / sim_clock::Int::us < 10) { // <10us
             age_index = 0;
-        } else if (age / SimClock::Int::us < 100) { // <100us
+        } else if (age / sim_clock::Int::us < 100) { // <100us
             age_index = 1;
-        } else if (age / SimClock::Int::ms < 1) { // <1ms
+        } else if (age / sim_clock::Int::ms < 1) { // <1ms
             age_index = 2;
-        } else if (age / SimClock::Int::ms < 10) { // <10ms
+        } else if (age / sim_clock::Int::ms < 10) { // <10ms
             age_index = 3;
         } else
             age_index = 4; // >10ms

src/mem/comm_monitor.cc

@@ -49,7 +49,7 @@ CommMonitor::CommMonitor(const Params &params)
       cpuSidePort(name() + "-cpu_side_port", *this),
       samplePeriodicEvent([this]{ samplePeriodic(); }, name()),
       samplePeriodTicks(params.sample_period),
-      samplePeriod(params.sample_period / SimClock::Float::s),
+      samplePeriod(params.sample_period / sim_clock::Float::s),
       stats(this, params)
 {
     DPRINTF(CommMonitor,

src/mem/drampower.cc

@@ -93,7 +93,7 @@ DRAMPower::getTimingParams(const DRAMInterfaceParams &p)
     timingSpec.XSDLL = divCeil(p.tXSDLL, p.tCK);
 
     // Clock period in ns
-    timingSpec.clkPeriod = (p.tCK / (double)(SimClock::Int::ns));
+    timingSpec.clkPeriod = (p.tCK / (double)(sim_clock::Int::ns));
     assert(timingSpec.clkPeriod != 0);
     timingSpec.clkMhz = (1 / timingSpec.clkPeriod) * 1000;
     return timingSpec;

src/mem/dramsim2.cc

@@ -144,7 +144,8 @@ DRAMSim2::tick()
         port.sendRetryReq();
     }
 
-    schedule(tickEvent, curTick() + wrapper.clockPeriod() * SimClock::Int::ns);
+    schedule(tickEvent,
+        curTick() + wrapper.clockPeriod() * sim_clock::Int::ns);
 }
 
 Tick
@@ -283,7 +284,7 @@ DRAMSim2::accessAndRespond(PacketPtr pkt)
 void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle)
 {
     assert(cycle == divCeil(curTick() - startTick,
-                            wrapper.clockPeriod() * SimClock::Int::ns));
+                            wrapper.clockPeriod() * sim_clock::Int::ns));
 
     DPRINTF(DRAMSim2, "Read to address %lld complete\n", addr);
 
@@ -311,7 +312,7 @@ void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle)
 void DRAMSim2::writeComplete(unsigned id, uint64_t addr, uint64_t cycle)
 {
     assert(cycle == divCeil(curTick() - startTick,
-                            wrapper.clockPeriod() * SimClock::Int::ns));
+                            wrapper.clockPeriod() * sim_clock::Int::ns));
 
     DPRINTF(DRAMSim2, "Write to address %lld complete\n", addr);
 

src/mem/dramsim3.cc

@@ -146,7 +146,8 @@ DRAMsim3::tick()
         }
     }
 
-    schedule(tickEvent, curTick() + wrapper.clockPeriod() * SimClock::Int::ns);
+    schedule(tickEvent,
+        curTick() + wrapper.clockPeriod() * sim_clock::Int::ns);
 }
 
 Tick

src/mem/mem_interface.cc

@@ -1800,14 +1800,14 @@ DRAMInterface::Rank::updatePowerStats()
     // Accumulate window energy into the total energy.
     stats.totalEnergy += energy.window_energy * dram.devicesPerRank;
     // Average power must not be accumulated but calculated over the time
-    // since last stats reset. SimClock::Frequency is tick period not tick
+    // since last stats reset. sim_clock::Frequency is tick period not tick
     // frequency.
     //              energy (pJ)     1e-9
     // power (mW) = ----------- * ----------
     //              time (tick)   tick_frequency
     stats.averagePower = (stats.totalEnergy.value() /
                     (curTick() - dram.lastStatsResetTick)) *
-                    (SimClock::Frequency / 1000000000.0);
+                    (sim_clock::Frequency / 1000000000.0);
 }
 
 void
@@ -1951,7 +1951,7 @@ DRAMInterface::DRAMStats::regStats()
 
     avgRdBW = (bytesRead / 1000000) / simSeconds;
     avgWrBW = (bytesWritten / 1000000) / simSeconds;
-    peakBW = (SimClock::Frequency / dram.burstDelay()) *
+    peakBW = (sim_clock::Frequency / dram.burstDelay()) *
               dram.bytesPerBurst() / 1000000;
 
     busUtil = (avgRdBW + avgWrBW) / peakBW * 100;
@@ -2613,7 +2613,7 @@ NVMInterface::NVMStats::regStats()
 
     avgRdBW = (bytesRead / 1000000) / simSeconds;
     avgWrBW = (bytesWritten / 1000000) / simSeconds;
-    peakBW = (SimClock::Frequency / nvm.tBURST) *
+    peakBW = (sim_clock::Frequency / nvm.tBURST) *
               nvm.burstSize / 1000000;
 
     busUtil = (avgRdBW + avgWrBW) / peakBW * 100;

src/mem/probes/mem_trace.cc

@@ -84,7 +84,7 @@ MemTraceProbe::startup()
     // the stream
     ProtoMessage::PacketHeader header_msg;
     header_msg.set_obj_id(name());
-    header_msg.set_tick_freq(SimClock::Frequency);
+    header_msg.set_tick_freq(sim_clock::Frequency);
 
     for (int i = 0; i < system->maxRequestors(); i++) {
         auto id_string = header_msg.add_id_strings();

src/mem/qos/mem_ctrl.cc

@@ -184,7 +184,7 @@ MemCtrl::logResponse(BusState dir, RequestorID id, uint8_t qos,
         }
         // Compute latency
         double latency = (double) (curTick() + delay - requestTime)
-                / SimClock::Float::s;
+                / sim_clock::Float::s;
 
         if (latency > 0) {
             // Record per-priority latency stats

src/mem/xbar.cc

@@ -117,7 +117,7 @@ BaseXBar::calcPacketTiming(PacketPtr pkt, Tick header_delay)
     // do a quick sanity check to ensure the timings are not being
     // ignored, note that this specific value may cause problems for
     // slower interconnects
-    panic_if(pkt->headerDelay > SimClock::Int::us,
+    panic_if(pkt->headerDelay > sim_clock::Int::us,
              "Encountered header delay exceeding 1 us\n");
 
     if (pkt->hasData()) {

src/sim/clocked_object.hh

@@ -209,7 +209,7 @@ class Clocked
      */
     Tick nextCycle() const { return clockEdge(Cycles(1)); }
 
-    uint64_t frequency() const { return SimClock::Frequency / clockPeriod(); }
+    uint64_t frequency() const { return sim_clock::Frequency / clockPeriod(); }
 
     Tick clockPeriod() const { return clockDomain.clockPeriod(); }
 

src/sim/core.cc

@@ -38,7 +38,9 @@
 #include "base/logging.hh"
 #include "base/output.hh"
 
-namespace SimClock {
+GEM5_DEPRECATED_NAMESPACE(SimClock, sim_clock);
+namespace sim_clock
+{
 /// The simulated frequency of curTick(). (In ticks per second)
 Tick Frequency;
 
@@ -63,7 +65,7 @@ Tick ns;
 Tick ps;
 } // namespace Float
 
-} // namespace SimClock
+} // namespace sim_clock
 
 namespace {
 
@@ -80,7 +82,7 @@ fixClockFrequency()
     if (_clockFrequencyFixed)
         return;
 
-    using namespace SimClock;
+    using namespace sim_clock;
     Frequency = _ticksPerSecond;
     Float::s = static_cast<double>(Frequency);
     Float::ms = Float::s / 1.0e3;

src/sim/core.hh

@@ -38,6 +38,7 @@
 #include <functional>
 #include <string>
 
+#include "base/compiler.hh"
 #include "base/types.hh"
 // @todo The next include is not needed in this file, but must be kept
 // until the transitive includes are fixed
@@ -45,7 +46,9 @@
 
 /// These are variables that are set based on the simulator frequency
 ///@{
-namespace SimClock {
+GEM5_DEPRECATED_NAMESPACE(SimClock, sim_clock);
+namespace sim_clock
+{
 extern Tick Frequency; ///< The number of ticks that equal one second
 
 namespace Float {
@@ -84,7 +87,7 @@ extern Tick ns; ///< nanosecond
 extern Tick ps; ///< picosecond
 /** @} */
 } // namespace Int
-} // namespace SimClock
+} // namespace sim_clock
 /** @} */
 
 void fixClockFrequency();

src/sim/power/thermal_model.cc

@@ -166,7 +166,7 @@ ThermalModel::doStep()
         eq_nodes[i]->temp = Temperature::fromKelvin(temps[i]);
 
     // Schedule next computation
-    schedule(stepEvent, curTick() + SimClock::Int::s * _step);
+    schedule(stepEvent, curTick() + sim_clock::Int::s * _step);
 
     // Notify everybody
     for (auto dom : domains)
@@ -203,7 +203,7 @@ ThermalModel::startup()
         eq_nodes[i]->id = i;
 
     // Schedule first thermal update
-    schedule(stepEvent, curTick() + SimClock::Int::s * _step);
+    schedule(stepEvent, curTick() + sim_clock::Int::s * _step);
 }
 
 void

src/sim/pseudo_inst.cc

@@ -126,7 +126,7 @@ void
 quiesceNs(ThreadContext *tc, uint64_t ns)
 {
     DPRINTF(PseudoInst, "PseudoInst::quiesceNs(%i)\n", ns);
-    tc->quiesceTick(curTick() + SimClock::Int::ns * ns);
+    tc->quiesceTick(curTick() + sim_clock::Int::ns * ns);
 }
 
 void
@@ -142,14 +142,14 @@ quiesceTime(ThreadContext *tc)
     DPRINTF(PseudoInst, "PseudoInst::quiesceTime()\n");
 
     return (tc->readLastActivate() - tc->readLastSuspend()) /
-        SimClock::Int::ns;
+        sim_clock::Int::ns;
 }
 
 uint64_t
 rpns(ThreadContext *tc)
 {
     DPRINTF(PseudoInst, "PseudoInst::rpns()\n");
-    return curTick() / SimClock::Int::ns;
+    return curTick() / sim_clock::Int::ns;
 }
 
 void
@@ -174,7 +174,7 @@ m5exit(ThreadContext *tc, Tick delay)
 {
     DPRINTF(PseudoInst, "PseudoInst::m5exit(%i)\n", delay);
     if (DistIface::readyToExit(delay)) {
-        Tick when = curTick() + delay * SimClock::Int::ns;
+        Tick when = curTick() + delay * sim_clock::Int::ns;
         exitSimLoop("m5_exit instruction encountered", 0, when, 0, true);
     }
 }
@@ -193,7 +193,7 @@ void
 m5fail(ThreadContext *tc, Tick delay, uint64_t code)
 {
     DPRINTF(PseudoInst, "PseudoInst::m5fail(%i, %i)\n", delay, code);
-    Tick when = curTick() + delay * SimClock::Int::ns;
+    Tick when = curTick() + delay * sim_clock::Int::ns;
     exitSimLoop("m5_fail instruction encountered", code, when, 0, true);
 }
 
@@ -304,8 +304,8 @@ resetstats(ThreadContext *tc, Tick delay, Tick period)
         return;
 
 
-    Tick when = curTick() + delay * SimClock::Int::ns;
-    Tick repeat = period * SimClock::Int::ns;
+    Tick when = curTick() + delay * sim_clock::Int::ns;
+    Tick repeat = period * sim_clock::Int::ns;
 
     Stats::schedStatEvent(false, true, when, repeat);
 }
@@ -318,8 +318,8 @@ dumpstats(ThreadContext *tc, Tick delay, Tick period)
         return;
 
 
-    Tick when = curTick() + delay * SimClock::Int::ns;
-    Tick repeat = period * SimClock::Int::ns;
+    Tick when = curTick() + delay * sim_clock::Int::ns;
+    Tick repeat = period * sim_clock::Int::ns;
 
     Stats::schedStatEvent(true, false, when, repeat);
 }
@@ -332,8 +332,8 @@ dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
         return;
 
 
-    Tick when = curTick() + delay * SimClock::Int::ns;
-    Tick repeat = period * SimClock::Int::ns;
+    Tick when = curTick() + delay * sim_clock::Int::ns;
+    Tick repeat = period * sim_clock::Int::ns;
 
     Stats::schedStatEvent(true, true, when, repeat);
 }
@@ -346,8 +346,8 @@ m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
         return;
 
     if (DistIface::readyToCkpt(delay, period)) {
-        Tick when = curTick() + delay * SimClock::Int::ns;
-        Tick repeat = period * SimClock::Int::ns;
+        Tick when = curTick() + delay * sim_clock::Int::ns;
+        Tick repeat = period * sim_clock::Int::ns;
         exitSimLoop("checkpoint", 0, when, repeat);
     }
 }

src/sim/root.cc

@@ -75,7 +75,7 @@ Root::RootStats::RootStats()
     statTime(true),
     startTick(0)
 {
-    simFreq.scalar(SimClock::Frequency);
+    simFreq.scalar(sim_clock::Frequency);
     simTicks.functor([this]() { return curTick() - startTick; });
     finalTick.functor(curTick);
 

src/sim/syscall_emul.hh

@@ -519,7 +519,7 @@ getElapsedTimeMicro(T1 &sec, T2 &usec)
 {
     static const int OneMillion = 1000 * 1000;
 
-    uint64_t elapsed_usecs = curTick() / SimClock::Int::us;
+    uint64_t elapsed_usecs = curTick() / sim_clock::Int::us;
     sec = elapsed_usecs / OneMillion;
     usec = elapsed_usecs % OneMillion;
 }
@@ -532,7 +532,7 @@ getElapsedTimeNano(T1 &sec, T2 &nsec)
 {
     static const int OneBillion = 1000 * 1000 * 1000;
 
-    uint64_t elapsed_nsecs = curTick() / SimClock::Int::ns;
+    uint64_t elapsed_nsecs = curTick() / sim_clock::Int::ns;
     sec = elapsed_nsecs / OneBillion;
     nsec = elapsed_nsecs % OneBillion;
 }
@@ -2102,7 +2102,7 @@ SyscallReturn
 timesFunc(SyscallDesc *desc, ThreadContext *tc, VPtr<typename OS::tms> bufp)
 {
     // Fill in the time structure (in clocks)
-    int64_t clocks = curTick() * OS::M5_SC_CLK_TCK / SimClock::Int::s;
+    int64_t clocks = curTick() * OS::M5_SC_CLK_TCK / sim_clock::Int::s;
     bufp->tms_utime = clocks;
     bufp->tms_stime = 0;
     bufp->tms_cutime = 0;

src/systemc/core/sc_time.cc

@@ -50,7 +50,7 @@ set(::sc_core::sc_time *time, double d, ::sc_core::sc_time_unit tu)
     if (d != 0)
         fixClockFrequency();
 
-    double scale = sc_gem5::TimeUnitScale[tu] * SimClock::Float::s;
+    double scale = sc_gem5::TimeUnitScale[tu] * sim_clock::Float::s;
     // Accellera claims there is a linux bug, and that these next two
     // lines work around them.
     volatile double tmp = d * scale + 0.5;
@@ -94,13 +94,13 @@ sc_time::sc_time(double d, const char *unit)
 
 sc_time::sc_time(double d, bool scale)
 {
-    double scaler = scale ? defaultUnit : SimClock::Float::Hz;
+    double scaler = scale ? defaultUnit : sim_clock::Float::Hz;
     set(this, d * scaler, SC_SEC);
 }
 
 sc_time::sc_time(sc_dt::uint64 v, bool scale)
 {
-    double scaler = scale ? defaultUnit : SimClock::Float::Hz;
+    double scaler = scale ? defaultUnit : sim_clock::Float::Hz;
     set(this, static_cast<double>(v) * scaler, SC_SEC);
 }
 
@@ -125,7 +125,7 @@ sc_time::to_double() const
 double
 sc_time::to_seconds() const
 {
-    return to_double() * SimClock::Float::Hz;
+    return to_double() * sim_clock::Float::Hz;
 }
 
 const std::string
@@ -377,7 +377,7 @@ sc_set_default_time_unit(double d, sc_time_unit tu)
     defaultUnit = d * sc_gem5::TimeUnitScale[tu];
     specified = true;
 
-    double resolution = SimClock::Float::Hz;
+    double resolution = sim_clock::Float::Hz;
     if (resolution == 0.0)
         resolution = sc_gem5::TimeUnitScale[SC_PS];
     if (defaultUnit < resolution) {
@@ -398,7 +398,7 @@ sc_time_tuple::sc_time_tuple(const sc_time &t) :
     if (!t.value())
         return;
 
-    Tick frequency = SimClock::Frequency;
+    Tick frequency = sim_clock::Frequency;
 
     // Shrink the frequency by scaling down the time period, ie converting
     // it from cycles per second to cycles per millisecond, etc.

src/systemc/tlm_bridge/tlm_to_gem5.cc

@@ -341,7 +341,7 @@ TlmToGem5Bridge<BITWIDTH>::b_transport(tlm::tlm_generic_payload &trans,
              "Packet sending failed!\n");
 
     auto delay =
-      sc_core::sc_time((double)(ticks / SimClock::Int::ps), sc_core::SC_PS);
+      sc_core::sc_time((double)(ticks / sim_clock::Int::ps), sc_core::SC_PS);
 
     // update time
     t += delay;

src/systemc/utils/vcd.cc

@@ -254,7 +254,7 @@ VcdTraceFile::initialize()
     std::string timedump_comment =
         csprintf("All initial values are dumped below at time "
                  "%g sec = %g timescale units.",
-                 static_cast<double>(now) / SimClock::Float::s,
+                 static_cast<double>(now) / sim_clock::Float::s,
                  static_cast<double>(now / timeUnitTicks));
     writeComment(timedump_comment);