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sim,misc: Rename Int namespace as as_int

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As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

sim_clock::Int became sim_clock::as_int.

"as_int" was chosen because "int" is a reserved
keyword, and this namespace acts as a selector of
how to read the internal variables.

Another possibility to resolve this would be to
remove the namespaces "Float" and "Int" and use
unions instead.

Change-Id: I65f47608d2212424bed1731c7f53d242d5a7d89a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45436
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Daniel R. Carvalho
2021-05-07 16:04:12 -03:00
committed by Daniel Carvalho
parent c487767cff
commit 71460cb13e
30 changed files with 68 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/fastmodel/CortexA76/evs.cc
View File

@@ -42,7 +42,7 @@ template <class Types>
void
ScxEvsCortexA76<Types>::setClkPeriod(Tick clk_period)
{
clockRateControl->set_mul_div(sim_clock::Int::s, clk_period);
clockRateControl->set_mul_div(sim_clock::as_int::s, clk_period);
}
template <class Types>

2
src/arch/arm/fastmodel/CortexR52/evs.cc
View File

@@ -41,7 +41,7 @@ template <class Types>
void
ScxEvsCortexR52<Types>::setClkPeriod(Tick clk_period)
{
clockRateControl->set_mul_div(sim_clock::Int::s, clk_period);
clockRateControl->set_mul_div(sim_clock::as_int::s, clk_period);
}
template <class Types>

2
src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
View File

@@ -256,7 +256,7 @@ void
PL330::start_of_simulation()
{
// Set the clock rate using the divider inside the EVS.
clockRateControl->set_mul_div(sim_clock::Int::s, clockPeriod);
clockRateControl->set_mul_div(sim_clock::as_int::s, clockPeriod);
}
} // namespace fastmodel

2
src/arch/arm/semihosting.cc
View File

@@ -500,7 +500,7 @@ ArmSemihosting::callRename(ThreadContext *tc, Addr from_addr, size_t from_size,
ArmSemihosting::RetErrno
ArmSemihosting::callClock(ThreadContext *tc)
{
return retOK(curTick() / (sim_clock::Int::s / 100));
return retOK(curTick() / (sim_clock::as_int::s / 100));
}
ArmSemihosting::RetErrno

2
src/dev/arm/energy_ctrl.cc
View File

@@ -99,7 +99,7 @@ EnergyCtrl::read(PacketPtr pkt)
break;
case DVFS_HANDLER_TRANS_LATENCY:
// Return transition latency in nanoseconds
result = dvfsHandler->transLatency() / sim_clock::Int::ns;
result = dvfsHandler->transLatency() / sim_clock::as_int::ns;
DPRINTF(EnergyCtrl, "reading dvfs handler trans latency %d ns\n",
result);
break;

2
src/dev/arm/energy_ctrl.hh
View File

@@ -164,7 +164,7 @@ class EnergyCtrl : public BasicPioDevice
uint32_t perfLevelToRead;
static uint32_t ticksTokHz(Tick period) {
return (uint32_t)(sim_clock::Int::ms / period);
return (uint32_t)(sim_clock::as_int::ms / period);
}
static uint32_t toMicroVolt(double voltage) {

5
src/dev/arm/rtc_pl031.cc
View File

@@ -69,7 +69,8 @@ PL031::read(PacketPtr pkt)
switch (daddr) {
case DataReg:
data = timeVal + ((curTick() - lastWrittenTick) / sim_clock::Int::s);
data = timeVal +
((curTick() - lastWrittenTick) / sim_clock::as_int::s);
break;
case MatchReg:
data = matchVal;
@@ -154,7 +155,7 @@ PL031::resyncMatch()
timeVal);
uint32_t seconds_until = matchVal - timeVal;
Tick ticks_until = sim_clock::Int::s * seconds_until;
Tick ticks_until = sim_clock::as_int::s * seconds_until;
if (matchEvent.scheduled()) {
DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");

4
src/dev/mc146818.cc
View File

@@ -175,7 +175,7 @@ MC146818::writeData(const uint8_t addr, const uint8_t data)
// from reset to active. So, we simply schedule the
// tick after 0.5s.
assert(!tickEvent.scheduled());
schedule(tickEvent, curTick() + sim_clock::Int::s / 2);
schedule(tickEvent, curTick() + sim_clock::as_int::s / 2);
}
} break;
case RTC_STAT_REGB:
@@ -333,7 +333,7 @@ void
MC146818::RTCTickEvent::process()
{
DPRINTF(MC146818, "RTC clock tick\n");
parent->schedule(this, curTick() + sim_clock::Int::s);
parent->schedule(this, curTick() + sim_clock::as_int::s);
parent->tickClock();
}

2
src/dev/mc146818.hh
View File

@@ -70,7 +70,7 @@ class MC146818 : public EventManager
Tick offset;
RTCTickEvent(MC146818 * _parent) :
parent(_parent), offset(sim_clock::Int::s)
parent(_parent), offset(sim_clock::as_int::s)
{}
/** Event process to occur at interrupt*/

4
src/dev/net/etherdump.cc
View File

@@ -94,8 +94,8 @@ void
EtherDump::dumpPacket(EthPacketPtr &packet)
{
pcap_pkthdr pkthdr;
pkthdr.seconds = curTick() / sim_clock::Int::s;
pkthdr.microseconds = (curTick() / sim_clock::Int::us) % 1000000ULL;
pkthdr.seconds = curTick() / sim_clock::as_int::s;
pkthdr.microseconds = (curTick() / sim_clock::as_int::us) % 1000000ULL;
pkthdr.caplen = std::min(packet->length, maxlen);
pkthdr.len = packet->length;
stream->write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr));

2
src/dev/net/etherswitch.cc
View File

@@ -182,7 +182,7 @@ EtherSwitch::Interface::transmit()
if (!sendPacket(outputFifo.front())) {
DPRINTF(Ethernet, "output port busy...retry later\n");
if (!txEvent.scheduled())
parent->schedule(txEvent, curTick() + sim_clock::Int::ns);
parent->schedule(txEvent, curTick() + sim_clock::as_int::ns);
} else {
DPRINTF(Ethernet, "packet sent: len=%d\n", outputFifo.front()->length);
outputFifo.pop();

4
src/dev/net/ethertap.cc
View File

@@ -194,7 +194,7 @@ EtherTapBase::sendSimulated(void *data, size_t len)
DPRINTF(Ethernet, "bus busy...buffer for retransmission\n");
packetBuffer.push(packet);
if (!txEvent.scheduled())
schedule(txEvent, curTick() + sim_clock::Int::ns);
schedule(txEvent, curTick() + sim_clock::as_int::ns);
} else if (dump) {
dump->dump(packet);
}
@@ -216,7 +216,7 @@ EtherTapBase::retransmit()
}
if (!packetBuffer.empty() && !txEvent.scheduled())
schedule(txEvent, curTick() + sim_clock::Int::ns);
schedule(txEvent, curTick() + sim_clock::as_int::ns);
}

4
src/dev/net/i8254xGBe.cc
View File

@@ -699,7 +699,7 @@ IGbE::postInterrupt(IntTypes t, bool now)
regs.icr = regs.icr() | t;
Tick itr_interval = sim_clock::Int::ns * 256 * regs.itr.interval();
Tick itr_interval = sim_clock::as_int::ns * 256 * regs.itr.interval();
DPRINTF(EthernetIntr,
"EINT: postInterrupt() curTick(): %d itr: %d interval: %d\n",
curTick(), regs.itr.interval(), itr_interval);
@@ -808,7 +808,7 @@ IGbE::chkInterrupt()
"Possibly scheduling interrupt because of imr write\n");
if (!interEvent.scheduled()) {
Tick t = curTick() +
sim_clock::Int::ns * 256 * regs.itr.interval();
sim_clock::as_int::ns * 256 * regs.itr.interval();
DPRINTF(Ethernet, "Scheduling for %d\n", t);
schedule(interEvent, t);
}

2
src/dev/net/i8254xGBe.hh
View File

@@ -163,7 +163,7 @@ class IGbE : public EtherDevice
*/
void cpuClearInt();
Tick intClock() { return sim_clock::Int::ns * 1024; }
Tick intClock() { return sim_clock::as_int::ns * 1024; }
/** This function is used to restart the clock so it can handle things like
* draining and resume in one place. */

2
src/dev/net/ns_gige.cc
View File

@@ -1395,7 +1395,7 @@ NSGigE::transmit()
if (!txFifo.empty() && !txEvent.scheduled()) {
DPRINTF(Ethernet, "reschedule transmit\n");
schedule(txEvent, curTick() + sim_clock::Int::ns);
schedule(txEvent, curTick() + sim_clock::as_int::ns);
}
}

4
src/dev/serial/uart8250.cc
View File

@@ -72,7 +72,7 @@ Uart8250::processIntrEvent(int intrBit)
void
Uart8250::scheduleIntr(Event *event)
{
static const Tick interval = 225 * sim_clock::Int::ns;
static const Tick interval = 225 * sim_clock::as_int::ns;
DPRINTF(Uart, "Scheduling IER interrupt for %s, at cycle %lld\n",
event->name(), curTick() + interval);
if (!event->scheduled())
@@ -179,7 +179,7 @@ Uart8250::writeIer(Register<Ier> &reg, const Ier &ier)
if (ier.thri) {
DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
if (curTick() - lastTxInt > 225 * sim_clock::Int::ns) {
if (curTick() - lastTxInt > 225 * sim_clock::as_int::ns) {
DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n",
curTick(), lastTxInt);
txIntrEvent.process();

2
src/gpu-compute/gpu_compute_driver.cc
View File

@@ -284,7 +284,7 @@ GPUComputeDriver::ioctl(ThreadContext *tc, unsigned req, Addr ioc_buf)
* Derive all clock counters based on the tick. All
* device clocks are identical and perfectly in sync.
*/
uint64_t elapsed_nsec = curTick() / sim_clock::Int::ns;
uint64_t elapsed_nsec = curTick() / sim_clock::as_int::ns;
args->gpu_clock_counter = elapsed_nsec;
args->cpu_clock_counter = elapsed_nsec;
args->system_clock_counter = elapsed_nsec;

2
src/kern/freebsd/events.cc
View File

@@ -58,7 +58,7 @@ onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t time)
// time to 0 with the assumption that quiesce will not happen. To avoid
// the quiesce handling in this case, only execute the quiesce if time > 0.
if (time > 0)
tc->quiesceTick(curTick() + sim_clock::Int::ns * time);
tc->quiesceTick(curTick() + sim_clock::as_int::ns * time);
}
} // namespace free_bsd

2
src/kern/linux/events.cc
View File

@@ -91,7 +91,7 @@ onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t time)
// time to 0 with the assumption that quiesce will not happen. To avoid
// the quiesce handling in this case, only execute the quiesce if time > 0.
if (time > 0)
tc->quiesceTick(curTick() + sim_clock::Int::ns * time);
tc->quiesceTick(curTick() + sim_clock::as_int::ns * time);
}
} // namespace linux

8
src/mem/cache/tags/base.cc vendored
View File

@@ -167,13 +167,13 @@ BaseTags::computeStatsVisitor(CacheBlk &blk)
Tick age = blk.getAge();
int age_index;
if (age / sim_clock::Int::us < 10) { // <10us
if (age / sim_clock::as_int::us < 10) { // <10us
age_index = 0;
} else if (age / sim_clock::Int::us < 100) { // <100us
} else if (age / sim_clock::as_int::us < 100) { // <100us
age_index = 1;
} else if (age / sim_clock::Int::ms < 1) { // <1ms
} else if (age / sim_clock::as_int::ms < 1) { // <1ms
age_index = 2;
} else if (age / sim_clock::Int::ms < 10) { // <10ms
} else if (age / sim_clock::as_int::ms < 10) { // <10ms
age_index = 3;
} else
age_index = 4; // >10ms

2
src/mem/drampower.cc
View File

@@ -93,7 +93,7 @@ DRAMPower::getTimingParams(const DRAMInterfaceParams &p)
timingSpec.XSDLL = divCeil(p.tXSDLL, p.tCK);
// Clock period in ns
timingSpec.clkPeriod = (p.tCK / (double)(sim_clock::Int::ns));
timingSpec.clkPeriod = (p.tCK / (double)(sim_clock::as_int::ns));
assert(timingSpec.clkPeriod != 0);
timingSpec.clkMhz = (1 / timingSpec.clkPeriod) * 1000;
return timingSpec;

6
src/mem/dramsim2.cc
View File

@@ -145,7 +145,7 @@ DRAMSim2::tick()
}
schedule(tickEvent,
curTick() + wrapper.clockPeriod() * sim_clock::Int::ns);
curTick() + wrapper.clockPeriod() * sim_clock::as_int::ns);
}
Tick
@@ -284,7 +284,7 @@ DRAMSim2::accessAndRespond(PacketPtr pkt)
void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle)
{
assert(cycle == divCeil(curTick() - startTick,
wrapper.clockPeriod() * sim_clock::Int::ns));
wrapper.clockPeriod() * sim_clock::as_int::ns));
DPRINTF(DRAMSim2, "Read to address %lld complete\n", addr);
@@ -312,7 +312,7 @@ void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle)
void DRAMSim2::writeComplete(unsigned id, uint64_t addr, uint64_t cycle)
{
assert(cycle == divCeil(curTick() - startTick,
wrapper.clockPeriod() * sim_clock::Int::ns));
wrapper.clockPeriod() * sim_clock::as_int::ns));
DPRINTF(DRAMSim2, "Write to address %lld complete\n", addr);

2
src/mem/dramsim3.cc
View File

@@ -147,7 +147,7 @@ DRAMsim3::tick()
}
schedule(tickEvent,
curTick() + wrapper.clockPeriod() * sim_clock::Int::ns);
curTick() + wrapper.clockPeriod() * sim_clock::as_int::ns);
}
Tick

2
src/mem/xbar.cc
View File

@@ -117,7 +117,7 @@ BaseXBar::calcPacketTiming(PacketPtr pkt, Tick header_delay)
// do a quick sanity check to ensure the timings are not being
// ignored, note that this specific value may cause problems for
// slower interconnects
panic_if(pkt->headerDelay > sim_clock::Int::us,
panic_if(pkt->headerDelay > sim_clock::as_int::us,
"Encountered header delay exceeding 1 us\n");
if (pkt->hasData()) {

14
src/sim/core.cc
View File

@@ -59,7 +59,9 @@ double MHz;
double GHz;
} // namespace as_float
namespace Int {
GEM5_DEPRECATED_NAMESPACE(Int, as_int);
namespace as_int
{
Tick s;
Tick ms;
Tick us;
@@ -97,11 +99,11 @@ fixClockFrequency()
as_float::MHz = 1.0 / as_float::us;
as_float::GHz = 1.0 / as_float::ns;
Int::s = Frequency;
Int::ms = Int::s / 1000;
Int::us = Int::ms / 1000;
Int::ns = Int::us / 1000;
Int::ps = Int::ns / 1000;
as_int::s = Frequency;
as_int::ms = as_int::s / 1000;
as_int::us = as_int::ms / 1000;
as_int::ns = as_int::us / 1000;
as_int::ps = as_int::ns / 1000;
cprintf("Global frequency set at %d ticks per second\n", _ticksPerSecond);

6
src/sim/core.hh
View File

@@ -81,14 +81,16 @@ extern double GHz; ///< GHz
*
* @{
*/
namespace Int {
GEM5_DEPRECATED_NAMESPACE(Int, as_int);
namespace as_int
{
extern Tick s; ///< second
extern Tick ms; ///< millisecond
extern Tick us; ///< microsecond
extern Tick ns; ///< nanosecond
extern Tick ps; ///< picosecond
/** @} */
} // namespace Int
} // namespace as_int
} // namespace sim_clock
/** @} */

4
src/sim/power/thermal_model.cc
View File

@@ -166,7 +166,7 @@ ThermalModel::doStep()
eq_nodes[i]->temp = Temperature::fromKelvin(temps[i]);
// Schedule next computation
schedule(stepEvent, curTick() + sim_clock::Int::s * _step);
schedule(stepEvent, curTick() + sim_clock::as_int::s * _step);
// Notify everybody
for (auto dom : domains)
@@ -203,7 +203,7 @@ ThermalModel::startup()
eq_nodes[i]->id = i;
// Schedule first thermal update
schedule(stepEvent, curTick() + sim_clock::Int::s * _step);
schedule(stepEvent, curTick() + sim_clock::as_int::s * _step);
}
void

26
src/sim/pseudo_inst.cc
View File

@@ -127,7 +127,7 @@ void
quiesceNs(ThreadContext *tc, uint64_t ns)
{
DPRINTF(PseudoInst, "pseudo_inst::quiesceNs(%i)\n", ns);
tc->quiesceTick(curTick() + sim_clock::Int::ns * ns);
tc->quiesceTick(curTick() + sim_clock::as_int::ns * ns);
}
void
@@ -143,14 +143,14 @@ quiesceTime(ThreadContext *tc)
DPRINTF(PseudoInst, "pseudo_inst::quiesceTime()\n");
return (tc->readLastActivate() - tc->readLastSuspend()) /
sim_clock::Int::ns;
sim_clock::as_int::ns;
}
uint64_t
rpns(ThreadContext *tc)
{
DPRINTF(PseudoInst, "pseudo_inst::rpns()\n");
return curTick() / sim_clock::Int::ns;
return curTick() / sim_clock::as_int::ns;
}
void
@@ -175,7 +175,7 @@ m5exit(ThreadContext *tc, Tick delay)
{
DPRINTF(PseudoInst, "pseudo_inst::m5exit(%i)\n", delay);
if (DistIface::readyToExit(delay)) {
Tick when = curTick() + delay * sim_clock::Int::ns;
Tick when = curTick() + delay * sim_clock::as_int::ns;
exitSimLoop("m5_exit instruction encountered", 0, when, 0, true);
}
}
@@ -194,7 +194,7 @@ void
m5fail(ThreadContext *tc, Tick delay, uint64_t code)
{
DPRINTF(PseudoInst, "pseudo_inst::m5fail(%i, %i)\n", delay, code);
Tick when = curTick() + delay * sim_clock::Int::ns;
Tick when = curTick() + delay * sim_clock::as_int::ns;
exitSimLoop("m5_fail instruction encountered", code, when, 0, true);
}
@@ -305,8 +305,8 @@ resetstats(ThreadContext *tc, Tick delay, Tick period)
return;
Tick when = curTick() + delay * sim_clock::Int::ns;
Tick repeat = period * sim_clock::Int::ns;
Tick when = curTick() + delay * sim_clock::as_int::ns;
Tick repeat = period * sim_clock::as_int::ns;
Stats::schedStatEvent(false, true, when, repeat);
}
@@ -319,8 +319,8 @@ dumpstats(ThreadContext *tc, Tick delay, Tick period)
return;
Tick when = curTick() + delay * sim_clock::Int::ns;
Tick repeat = period * sim_clock::Int::ns;
Tick when = curTick() + delay * sim_clock::as_int::ns;
Tick repeat = period * sim_clock::as_int::ns;
Stats::schedStatEvent(true, false, when, repeat);
}
@@ -334,8 +334,8 @@ dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
return;
Tick when = curTick() + delay * sim_clock::Int::ns;
Tick repeat = period * sim_clock::Int::ns;
Tick when = curTick() + delay * sim_clock::as_int::ns;
Tick repeat = period * sim_clock::as_int::ns;
Stats::schedStatEvent(true, true, when, repeat);
}
@@ -348,8 +348,8 @@ m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
return;
if (DistIface::readyToCkpt(delay, period)) {
Tick when = curTick() + delay * sim_clock::Int::ns;
Tick repeat = period * sim_clock::Int::ns;
Tick when = curTick() + delay * sim_clock::as_int::ns;
Tick repeat = period * sim_clock::as_int::ns;
exitSimLoop("checkpoint", 0, when, repeat);
}
}

6
src/sim/syscall_emul.hh
View File

@@ -519,7 +519,7 @@ getElapsedTimeMicro(T1 &sec, T2 &usec)
{
static const int OneMillion = 1000 * 1000;
uint64_t elapsed_usecs = curTick() / sim_clock::Int::us;
uint64_t elapsed_usecs = curTick() / sim_clock::as_int::us;
sec = elapsed_usecs / OneMillion;
usec = elapsed_usecs % OneMillion;
}
@@ -532,7 +532,7 @@ getElapsedTimeNano(T1 &sec, T2 &nsec)
{
static const int OneBillion = 1000 * 1000 * 1000;
uint64_t elapsed_nsecs = curTick() / sim_clock::Int::ns;
uint64_t elapsed_nsecs = curTick() / sim_clock::as_int::ns;
sec = elapsed_nsecs / OneBillion;
nsec = elapsed_nsecs % OneBillion;
}
@@ -2102,7 +2102,7 @@ SyscallReturn
timesFunc(SyscallDesc *desc, ThreadContext *tc, VPtr<typename OS::tms> bufp)
{
// Fill in the time structure (in clocks)
int64_t clocks = curTick() * OS::M5_SC_CLK_TCK / sim_clock::Int::s;
int64_t clocks = curTick() * OS::M5_SC_CLK_TCK / sim_clock::as_int::s;
bufp->tms_utime = clocks;
bufp->tms_stime = 0;
bufp->tms_cutime = 0;

3
src/systemc/tlm_bridge/tlm_to_gem5.cc
View File

@@ -341,7 +341,8 @@ TlmToGem5Bridge<BITWIDTH>::b_transport(tlm::tlm_generic_payload &trans,
"Packet sending failed!\n");
auto delay =
sc_core::sc_time((double)(ticks / sim_clock::Int::ps), sc_core::SC_PS);
sc_core::sc_time((double)(ticks / sim_clock::as_int::ps),
sc_core::SC_PS);
// update time
t += delay;