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gem5/src/mem
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Matt Sinclair 0eef1069cb ruby: fix typo in VIPER TCC triggerQueue 
The GPU VIPER TCC protocol accidentally used "TiggerMsg" instead
of "TriggerMsg" for the triggerQueue_in port.  This was a benign
bug beacuse the msg type is not used in the in_port implementation
but still makes the SLICC harder to understand, so fixing it is
worthwhile.

Change-Id: I88cbc72bac93bcc58a66f057a32f7bddf821cac9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44905
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-28 01:25:45 +00:00
..
cache
arch,mem: Use szext instead of sext as appropriate.
2021-04-20 00:12:25 +00:00
probes
mem: Add Units to mem stats
2021-02-10 09:03:09 +00:00
protocol
mem: Delete authors lists from mem files.
2020-02-17 21:51:08 +00:00
qos
configs, mem: MemInterface generating its own controller
2021-03-19 13:34:37 +00:00
ruby
ruby: fix typo in VIPER TCC triggerQueue
2021-04-28 01:25:45 +00:00
slicc
misc: Fix coding style for struct's opening braces
2021-03-19 20:57:24 +00:00
abstract_mem.cc
mem: Unclear MemoryAccess debug message
2021-03-30 23:51:03 +00:00
abstract_mem.hh
misc: Fix coding style for struct's opening braces
2021-03-19 20:57:24 +00:00
AbstractMemory.py
mem: Consistently use ISO prefixes
2021-01-22 16:03:54 +00:00
addr_mapper.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
addr_mapper.hh
mem: Ensure that RangeAddrMapper publishes its address range.
2021-03-31 20:54:38 +00:00
AddrMapper.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
backdoor.hh
misc: Fix remaining opening braces
2021-04-07 01:29:31 +00:00
bridge.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
bridge.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
Bridge.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
cfi_mem.cc
mem: CFI Flash Memory implementation
2021-04-16 09:52:55 +00:00
cfi_mem.hh
mem: CFI Flash Memory implementation
2021-04-16 09:52:55 +00:00
CfiMemory.py
mem: CFI Flash Memory implementation
2021-04-16 09:52:55 +00:00
coherent_xbar.cc
mem: Add Units to mem stats
2021-02-10 09:03:09 +00:00
coherent_xbar.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
comm_monitor.cc
mem: Remove units from stats description
2021-02-10 09:03:09 +00:00
comm_monitor.hh
misc: Remove unused params() definitions
2021-02-19 23:27:34 +00:00
CommMonitor.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
DRAMInterface.py
configs, mem: MemInterface generating its own controller
2021-03-19 13:34:37 +00:00
drampower.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
drampower.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
dramsim2_wrapper.cc
misc: Update attribute syntax, and reorganize compiler.hh.
2020-09-28 21:52:59 +00:00
dramsim2_wrapper.hh
mem: Delete authors lists from mem files.
2020-02-17 21:51:08 +00:00
dramsim2.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
dramsim2.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
dramsim3_wrapper.cc
misc: Update attribute syntax, and reorganize compiler.hh.
2020-09-28 21:52:59 +00:00
dramsim3_wrapper.hh
mem,ext: Integrating DRAMSim3 with gem5
2020-09-02 15:51:00 +00:00
dramsim3.cc
misc: Re-remove Authors lines from source files.
2021-02-03 12:55:17 +00:00
dramsim3.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
DRAMsim3.py
misc: Re-remove Authors lines from source files.
2021-02-03 12:55:17 +00:00
DRAMSim2.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
external_master.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
external_master.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
external_slave.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
external_slave.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
ExternalMaster.py
mem: Update port terminology
2020-08-26 16:48:13 +00:00
ExternalSlave.py
mem: Delete authors lists from mem files.
2020-02-17 21:51:08 +00:00
hmc_controller.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
hmc_controller.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
HMCController.py
mem: Delete authors lists from mem files.
2020-02-17 21:51:08 +00:00
htm.cc
arch, mem: Initial Hardware Transactional Memory implementation
2020-09-02 08:30:11 +00:00
htm.hh
arch, mem: Initial Hardware Transactional Memory implementation
2020-09-02 08:30:11 +00:00
mem_checker_monitor.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
mem_checker_monitor.hh
misc: Remove unused params() definitions
2021-02-19 23:27:34 +00:00
mem_checker.cc
misc: Fix some includes
2021-01-15 23:15:30 +00:00
mem_checker.hh
base: Move Named class to its own file
2021-03-16 03:28:52 +00:00
mem_ctrl.cc
mem: Remove units from stats description
2021-02-10 09:03:09 +00:00
mem_ctrl.hh
mem: Expose the underlyig DRAM or NVM's memory back door.
2020-11-06 00:58:20 +00:00
mem_delay.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
mem_delay.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mem_interface.cc
base,misc: Collapse and eliminate the ULL and LL macros.
2021-03-11 04:14:17 +00:00
mem_interface.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mem_object.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mem_requestor.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
MemChecker.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
MemCtrl.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
MemDelay.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
MemInterface.py
mem: Clean up Memory Controller
2020-09-08 16:38:47 +00:00
MemObject.py
mem: Delete authors lists from mem files.
2020-02-17 21:51:08 +00:00
multi_level_page_table.hh
misc: Fix missing includes.
2021-01-13 08:55:59 +00:00
noncoherent_xbar.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
noncoherent_xbar.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
NVMInterface.py
mem: Consistently use ISO prefixes
2021-01-22 16:03:54 +00:00
packet_access.hh
base, sim: Make ByteOrder into a ScopedEnum accessible to Python
2020-09-08 16:24:00 +00:00
packet_queue.cc
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
packet_queue.hh
misc: Fix coding style for class-opening braces
2021-03-19 20:57:24 +00:00
packet.cc
mem: Add HTM fields to the Packet object
2020-09-08 09:13:30 +00:00
packet.hh
misc: Fix remaining opening braces
2021-04-07 01:29:31 +00:00
page_table.cc
mem,sim: Get the page size from the page table in SE mode.
2020-11-06 08:16:40 +00:00
page_table.hh
misc: Fix coding style for enum's opening braces
2021-03-23 16:26:04 +00:00
physical.cc
mem: Stop "using namespace std"
2021-01-23 12:09:58 +00:00
physical.hh
misc: Fix missing includes.
2021-01-13 08:55:59 +00:00
port_proxy.cc
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
port_proxy.hh
mem: Update port terminology
2020-08-26 16:48:13 +00:00
port.cc
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
port.hh
base,mem: Use the standard [[deprecated]] attribute.
2020-09-28 21:52:41 +00:00
qport.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
request.hh
gpu-compute: Implement per-request MTYPEs
2021-04-24 15:54:15 +00:00
SConscript
mem: CFI Flash Memory implementation
2021-04-16 09:52:55 +00:00
se_translating_port_proxy.cc
mem: fixupAddr should not panic if it fails.
2020-06-18 03:58:48 +00:00
se_translating_port_proxy.hh
misc: Fix coding style for enum's opening braces
2021-03-23 16:26:04 +00:00
serial_link.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
serial_link.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
SerialLink.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
simple_mem.cc
mem: Minor refactor of how the abstract mem backdoor is exposed.
2020-11-06 00:58:04 +00:00
simple_mem.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
SimpleMemory.py
configs, mem: MemInterface generating its own controller
2021-03-19 13:34:37 +00:00
snoop_filter.cc
mem: Add Units to mem stats
2021-02-10 09:03:09 +00:00
snoop_filter.hh
misc: Fix coding style for enum's opening braces
2021-03-23 16:26:04 +00:00
stack_dist_calc.cc
mem: Fix some transitive includes.
2021-03-09 01:01:50 +00:00
stack_dist_calc.hh
misc: Fix remaining opening braces
2021-04-07 01:29:31 +00:00
token_port.cc
misc: Re-remove Authors lines from source files.
2021-02-03 12:55:17 +00:00
token_port.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
tport.cc
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
tport.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
translating_port_proxy.cc
mem: Replace any getDTBPtr/getITBPtr usage
2020-10-26 09:20:08 +00:00
translating_port_proxy.hh
mem: Add a Request::Flags parameter to the translating port proxies.
2020-03-19 07:21:13 +00:00
xbar.cc
mem: Remove units from stats description
2021-02-10 09:03:09 +00:00
xbar.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
XBar.py
mem: Consistently use ISO prefixes
2021-01-22 16:03:54 +00:00