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mem: Update port terminology

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Change-Id: Ib4fc8cad7139d4971e74930295a69e576f6da3cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32314
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Shivani Parekh
2020-08-05 17:35:08 -07:00
parent 6333e914d3
commit cf43bc3c8b
41 changed files with 155 additions and 153 deletions
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4
src/mem/AddrMapper.py
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@@ -48,8 +48,8 @@ class AddrMapper(SimObject):
abstract = True
# one port in each direction
master = MasterPort("Master port")
slave = SlavePort("Slave port")
master = RequestPort("Master port")
slave = ResponsePort("Slave port")
# Range address mapper that maps a set of original ranges to a set of

4
src/mem/Bridge.py
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@@ -42,8 +42,8 @@ from m5.objects.ClockedObject import ClockedObject
class Bridge(ClockedObject):
type = 'Bridge'
cxx_header = "mem/bridge.hh"
slave = SlavePort('Slave port')
master = MasterPort('Master port')
slave = ResponsePort('Slave port')
master = RequestPort('Master port')
req_size = Param.Unsigned(16, "The number of requests to buffer")
resp_size = Param.Unsigned(16, "The number of responses to buffer")
delay = Param.Latency('0ns', "The latency of this bridge")

4
src/mem/CommMonitor.py
View File

@@ -47,8 +47,8 @@ class CommMonitor(SimObject):
system = Param.System(Parent.any, "System that the monitor belongs to.")
# one port in each direction
master = MasterPort("Master port")
slave = SlavePort("Slave port")
master = RequestPort("Master port")
slave = ResponsePort("Slave port")
# control the sample period window length of this monitor
sample_period = Param.Clock("1ms", "Sample period for histograms")

2
src/mem/ExternalMaster.py
View File

@@ -41,7 +41,7 @@ class ExternalMaster(SimObject):
type = 'ExternalMaster'
cxx_header = "mem/external_master.hh"
port = MasterPort("Master port")
port = RequestPort("Master port")
port_type = Param.String('stub', 'Registered external port handler'
' to pass this port to in instantiation')

8
src/mem/MemChecker.py
View File

@@ -46,10 +46,10 @@ class MemCheckerMonitor(SimObject):
cxx_header = "mem/mem_checker_monitor.hh"
# one port in each direction
master = MasterPort("Master port")
slave = SlavePort("Slave port")
cpu_side = SlavePort("Alias for slave")
mem_side = MasterPort("Alias for master")
master = RequestPort("Master port")
slave = ResponsePort("Slave port")
cpu_side = ResponsePort("Alias for slave")
mem_side = RequestPort("Alias for master")
warn_only = Param.Bool(False, "Warn about violations only")
memchecker = Param.MemChecker("Instance shared with other monitors")

4
src/mem/MemDelay.py
View File

@@ -41,8 +41,8 @@ class MemDelay(ClockedObject):
cxx_header = 'mem/mem_delay.hh'
abstract = True
master = MasterPort("Master port")
slave = SlavePort("Slave port")
master = RequestPort("Master port")
slave = ResponsePort("Slave port")
class SimpleMemDelay(MemDelay):
type = 'SimpleMemDelay'

4
src/mem/SerialLink.py
View File

@@ -46,8 +46,8 @@ from m5.objects.ClockedObject import ClockedObject
class SerialLink(ClockedObject):
type = 'SerialLink'
cxx_header = "mem/serial_link.hh"
slave = SlavePort('Slave port')
master = MasterPort('Master port')
slave = ResponsePort('Slave port')
master = RequestPort('Master port')
req_size = Param.Unsigned(16, "The number of requests to buffer")
resp_size = Param.Unsigned(16, "The number of responses to buffer")
delay = Param.Latency('0ns', "The latency of this serial_link")

2
src/mem/XBar.py
View File

@@ -78,7 +78,7 @@ class BaseXBar(ClockedObject):
# The default port can be left unconnected, or be used to connect
# a default slave port
default = MasterPort("Port for connecting an optional default slave")
default = RequestPort("Port for connecting an optional default slave")
# The default port can be used unconditionally, or based on
# address range, in which case it may overlap with other

8
src/mem/addr_mapper.hh
View File

@@ -98,13 +98,13 @@ class AddrMapper : public SimObject
};
class MapperMasterPort : public MasterPort
class MapperMasterPort : public RequestPort
{
public:
MapperMasterPort(const std::string& _name, AddrMapper& _mapper)
: MasterPort(_name, &_mapper), mapper(_mapper)
: RequestPort(_name, &_mapper), mapper(_mapper)
{ }
protected:
@@ -153,13 +153,13 @@ class AddrMapper : public SimObject
/** Instance of master port, facing the memory side */
MapperMasterPort masterPort;
class MapperSlavePort : public SlavePort
class MapperSlavePort : public ResponsePort
{
public:
MapperSlavePort(const std::string& _name, AddrMapper& _mapper)
: SlavePort(_name, &_mapper), mapper(_mapper)
: ResponsePort(_name, &_mapper), mapper(_mapper)
{ }
protected:

4
src/mem/bridge.cc
View File

@@ -55,7 +55,7 @@ Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
BridgeMasterPort& _masterPort,
Cycles _delay, int _resp_limit,
std::vector<AddrRange> _ranges)
: SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
: ResponsePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
delay(_delay), ranges(_ranges.begin(), _ranges.end()),
outstandingResponses(0), retryReq(false), respQueueLimit(_resp_limit),
sendEvent([this]{ trySendTiming(); }, _name)
@@ -66,7 +66,7 @@ Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
Bridge& _bridge,
BridgeSlavePort& _slavePort,
Cycles _delay, int _req_limit)
: MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
: RequestPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
delay(_delay), reqQueueLimit(_req_limit),
sendEvent([this]{ trySendTiming(); }, _name)
{

4
src/mem/bridge.hh
View File

@@ -96,7 +96,7 @@ class Bridge : public ClockedObject
* is responsible for. The slave port also has a buffer for the
* responses not yet sent.
*/
class BridgeSlavePort : public SlavePort
class BridgeSlavePort : public ResponsePort
{
private:
@@ -216,7 +216,7 @@ class Bridge : public ClockedObject
* responses. The master port has a buffer for the requests not
* yet sent.
*/
class BridgeMasterPort : public MasterPort
class BridgeMasterPort : public RequestPort
{
private:

4
src/mem/cache/Cache.py vendored
View File

@@ -107,8 +107,8 @@ class BaseCache(ClockedObject):
sequential_access = Param.Bool(False,
"Whether to access tags and data sequentially")
cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
mem_side = MasterPort("Downstream port closer to memory")
cpu_side = ResponsePort("Upstream port closer to the CPU and/or device")
mem_side = RequestPort("Downstream port closer to memory")
addr_ranges = VectorParam.AddrRange([AllMemory],
"Address range for the CPU-side port (to allow striping)")

4
src/mem/cache/base.hh vendored
View File

@@ -79,7 +79,7 @@ namespace Prefetcher {
class Base;
}
class MSHR;
class MasterPort;
class RequestPort;
class QueueEntry;
struct BaseCacheParams;
@@ -166,7 +166,7 @@ class BaseCache : public ClockedObject
public:
CacheReqPacketQueue(BaseCache &cache, MasterPort &port,
CacheReqPacketQueue(BaseCache &cache, RequestPort &port,
SnoopRespPacketQueue &snoop_resp_queue,
const std::string &label) :
ReqPacketQueue(cache, port, label), cache(cache),

12
src/mem/coherent_xbar.cc
View File

@@ -68,7 +68,7 @@ CoherentXBar::CoherentXBar(const CoherentXBarParams *p)
// are enumerated starting from zero
for (int i = 0; i < p->port_master_connection_count; ++i) {
std::string portName = csprintf("%s.master[%d]", name(), i);
MasterPort* bp = new CoherentXBarMasterPort(portName, *this, i);
RequestPort* bp = new CoherentXBarMasterPort(portName, *this, i);
masterPorts.push_back(bp);
reqLayers.push_back(new ReqLayer(*bp, *this,
csprintf("reqLayer%d", i)));
@@ -81,7 +81,7 @@ CoherentXBar::CoherentXBar(const CoherentXBarParams *p)
if (p->port_default_connection_count) {
defaultPortID = masterPorts.size();
std::string portName = name() + ".default";
MasterPort* bp = new CoherentXBarMasterPort(portName, *this,
RequestPort* bp = new CoherentXBarMasterPort(portName, *this,
defaultPortID);
masterPorts.push_back(bp);
reqLayers.push_back(new ReqLayer(*bp, *this, csprintf("reqLayer%d",
@@ -142,7 +142,7 @@ bool
CoherentXBar::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
{
// determine the source port based on the id
SlavePort *src_port = slavePorts[slave_port_id];
ResponsePort *src_port = slavePorts[slave_port_id];
// remember if the packet is an express snoop
bool is_express_snoop = pkt->isExpressSnoop();
@@ -439,7 +439,7 @@ bool
CoherentXBar::recvTimingResp(PacketPtr pkt, PortID master_port_id)
{
// determine the source port based on the id
MasterPort *src_port = masterPorts[master_port_id];
RequestPort *src_port = masterPorts[master_port_id];
// determine the destination
const auto route_lookup = routeTo.find(pkt->req);
@@ -561,7 +561,7 @@ bool
CoherentXBar::recvTimingSnoopResp(PacketPtr pkt, PortID slave_port_id)
{
// determine the source port based on the id
SlavePort* src_port = slavePorts[slave_port_id];
ResponsePort* src_port = slavePorts[slave_port_id];
// get the destination
const auto route_lookup = routeTo.find(pkt->req);
@@ -589,7 +589,7 @@ CoherentXBar::recvTimingSnoopResp(PacketPtr pkt, PortID slave_port_id)
}
} else {
// get the master port that mirrors this slave port internally
MasterPort* snoop_port = snoopRespPorts[slave_port_id];
RequestPort* snoop_port = snoopRespPorts[slave_port_id];
assert(dest_port_id < respLayers.size());
if (!respLayers[dest_port_id]->tryTiming(snoop_port)) {
DPRINTF(CoherentXBar, "%s: src %s packet %s BUSY\n", __func__,

8
src/mem/coherent_xbar.hh
View File

@@ -146,7 +146,7 @@ class CoherentXBar : public BaseXBar
* instantiated for each of the slave interfaces connecting to the
* crossbar.
*/
class CoherentXBarMasterPort : public MasterPort
class CoherentXBarMasterPort : public RequestPort
{
private:
/** A reference to the crossbar to which this port belongs. */
@@ -156,7 +156,7 @@ class CoherentXBar : public BaseXBar
CoherentXBarMasterPort(const std::string &_name,
CoherentXBar &_xbar, PortID _id)
: MasterPort(_name, &_xbar, _id), xbar(_xbar)
: RequestPort(_name, &_xbar, _id), xbar(_xbar)
{ }
protected:
@@ -203,7 +203,7 @@ class CoherentXBar : public BaseXBar
* from a slave port and forwarding it through an outgoing slave
* port. It is effectively a dangling master port.
*/
class SnoopRespPort : public MasterPort
class SnoopRespPort : public RequestPort
{
private:
@@ -217,7 +217,7 @@ class CoherentXBar : public BaseXBar
* Create a snoop response port that mirrors a given slave port.
*/
SnoopRespPort(QueuedSlavePort& slave_port, CoherentXBar& _xbar) :
MasterPort(slave_port.name() + ".snoopRespPort", &_xbar),
RequestPort(slave_port.name() + ".snoopRespPort", &_xbar),
slavePort(slave_port) { }
/**

8
src/mem/comm_monitor.hh
View File

@@ -117,13 +117,13 @@ class CommMonitor : public SimObject
* send function of the slave port is called. Besides this, these
* functions can also perform actions for capturing statistics.
*/
class MonitorMasterPort : public MasterPort
class MonitorMasterPort : public RequestPort
{
public:
MonitorMasterPort(const std::string& _name, CommMonitor& _mon)
: MasterPort(_name, &_mon), mon(_mon)
: RequestPort(_name, &_mon), mon(_mon)
{ }
protected:
@@ -183,13 +183,13 @@ class CommMonitor : public SimObject
* send function of the master port is called. Besides this, these
* functions can also perform actions for capturing statistics.
*/
class MonitorSlavePort : public SlavePort
class MonitorSlavePort : public ResponsePort
{
public:
MonitorSlavePort(const std::string& _name, CommMonitor& _mon)
: SlavePort(_name, &_mon), mon(_mon)
: ResponsePort(_name, &_mon), mon(_mon)
{ }
protected:

10
src/mem/external_master.hh
View File

@@ -48,9 +48,9 @@
* port which is to be bound to. A port handler will usually construct a
* bridge object in the external system to accomodate the port-to-port
* mapping but this bridge is not exposed to gem5 other than be the
* presentation of the MasterPort which can be bound.
* presentation of the RequestPort which can be bound.
*
* The external port must provide a gem5 MasterPort interface.
* The external port must provide a gem5 RequestPort interface.
*/
#ifndef __MEM_EXTERNAL_MASTER_HH__
@@ -64,7 +64,7 @@ class ExternalMaster : public SimObject
{
public:
/** Derive from this class to create an external port interface */
class ExternalPort : public MasterPort
class ExternalPort : public RequestPort
{
protected:
ExternalMaster &owner;
@@ -72,7 +72,7 @@ class ExternalMaster : public SimObject
public:
ExternalPort(const std::string &name_,
ExternalMaster &owner_) :
MasterPort(name_, &owner_), owner(owner_)
RequestPort(name_, &owner_), owner(owner_)
{ }
~ExternalPort() { }
@@ -83,7 +83,7 @@ class ExternalMaster : public SimObject
/* Handlers are specific to *types* of port not specific port
* instantiations. A handler will typically build a bridge to the
* external port from gem5 and provide gem5 with a MasterPort that can be
* external port from gem5 and provide gem5 with a RequestPort that can be
* bound to for each call to Handler::getExternalPort.*/
class Handler
{

2
src/mem/hmc_controller.cc
View File

@@ -43,7 +43,7 @@ int HMCController::rotate_counter()
bool HMCController::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
{
// determine the source port based on the id
SlavePort *src_port = slavePorts[slave_port_id];
ResponsePort *src_port = slavePorts[slave_port_id];
// we should never see express snoops on a non-coherent component
assert(!pkt->isExpressSnoop());

8
src/mem/mem_checker_monitor.hh
View File

@@ -88,13 +88,13 @@ class MemCheckerMonitor : public SimObject
* send function of the slave port is called. Besides this, these
* functions can also perform actions for capturing statistics.
*/
class MonitorMasterPort : public MasterPort
class MonitorMasterPort : public RequestPort
{
public:
MonitorMasterPort(const std::string& _name, MemCheckerMonitor& _mon)
: MasterPort(_name, &_mon), mon(_mon)
: RequestPort(_name, &_mon), mon(_mon)
{ }
protected:
@@ -149,13 +149,13 @@ class MemCheckerMonitor : public SimObject
* send function of the master port is called. Besides this, these
* functions can also perform actions for capturing statistics.
*/
class MonitorSlavePort : public SlavePort
class MonitorSlavePort : public ResponsePort
{
public:
MonitorSlavePort(const std::string& _name, MemCheckerMonitor& _mon)
: SlavePort(_name, &_mon), mon(_mon)
: ResponsePort(_name, &_mon), mon(_mon)
{ }
protected:

21
src/mem/mem_delay.cc
View File

@@ -77,7 +77,7 @@ MemDelay::trySatisfyFunctional(PacketPtr pkt)
masterPort.trySatisfyFunctional(pkt);
}
MemDelay::MasterPort::MasterPort(const std::string &_name, MemDelay &_parent)
MemDelay::RequestPort::RequestPort(const std::string &_name, MemDelay &_parent)
: QueuedMasterPort(_name, &_parent,
_parent.reqQueue, _parent.snoopRespQueue),
parent(_parent)
@@ -85,7 +85,7 @@ MemDelay::MasterPort::MasterPort(const std::string &_name, MemDelay &_parent)
}
bool
MemDelay::MasterPort::recvTimingResp(PacketPtr pkt)
MemDelay::RequestPort::recvTimingResp(PacketPtr pkt)
{
// technically the packet only reaches us after the header delay,
// and typically we also need to deserialise any payload
@@ -100,7 +100,7 @@ MemDelay::MasterPort::recvTimingResp(PacketPtr pkt)
}
void
MemDelay::MasterPort::recvFunctionalSnoop(PacketPtr pkt)
MemDelay::RequestPort::recvFunctionalSnoop(PacketPtr pkt)
{
if (parent.trySatisfyFunctional(pkt)) {
pkt->makeResponse();
@@ -110,7 +110,7 @@ MemDelay::MasterPort::recvFunctionalSnoop(PacketPtr pkt)
}
Tick
MemDelay::MasterPort::recvAtomicSnoop(PacketPtr pkt)
MemDelay::RequestPort::recvAtomicSnoop(PacketPtr pkt)
{
const Tick delay = parent.delaySnoopResp(pkt);
@@ -118,20 +118,21 @@ MemDelay::MasterPort::recvAtomicSnoop(PacketPtr pkt)
}
void
MemDelay::MasterPort::recvTimingSnoopReq(PacketPtr pkt)
MemDelay::RequestPort::recvTimingSnoopReq(PacketPtr pkt)
{
parent.slavePort.sendTimingSnoopReq(pkt);
}
MemDelay::SlavePort::SlavePort(const std::string &_name, MemDelay &_parent)
MemDelay::ResponsePort::
ResponsePort(const std::string &_name, MemDelay &_parent)
: QueuedSlavePort(_name, &_parent, _parent.respQueue),
parent(_parent)
{
}
Tick
MemDelay::SlavePort::recvAtomic(PacketPtr pkt)
MemDelay::ResponsePort::recvAtomic(PacketPtr pkt)
{
const Tick delay = parent.delayReq(pkt) + parent.delayResp(pkt);
@@ -139,7 +140,7 @@ MemDelay::SlavePort::recvAtomic(PacketPtr pkt)
}
bool
MemDelay::SlavePort::recvTimingReq(PacketPtr pkt)
MemDelay::ResponsePort::recvTimingReq(PacketPtr pkt)
{
// technically the packet only reaches us after the header
// delay, and typically we also need to deserialise any
@@ -155,7 +156,7 @@ MemDelay::SlavePort::recvTimingReq(PacketPtr pkt)
}
void
MemDelay::SlavePort::recvFunctional(PacketPtr pkt)
MemDelay::ResponsePort::recvFunctional(PacketPtr pkt)
{
if (parent.trySatisfyFunctional(pkt)) {
pkt->makeResponse();
@@ -165,7 +166,7 @@ MemDelay::SlavePort::recvFunctional(PacketPtr pkt)
}
bool
MemDelay::SlavePort::recvTimingSnoopResp(PacketPtr pkt)
MemDelay::ResponsePort::recvTimingSnoopResp(PacketPtr pkt)
{
const Tick when = curTick() + parent.delaySnoopResp(pkt);

12
src/mem/mem_delay.hh
View File

@@ -71,10 +71,10 @@ class MemDelay : public ClockedObject
Port &getPort(const std::string &if_name,
PortID idx=InvalidPortID) override;
class MasterPort : public QueuedMasterPort
class RequestPort : public QueuedMasterPort
{
public:
MasterPort(const std::string &_name, MemDelay &_parent);
RequestPort(const std::string &_name, MemDelay &_parent);
protected:
bool recvTimingResp(PacketPtr pkt) override;
@@ -97,10 +97,10 @@ class MemDelay : public ClockedObject
MemDelay& parent;
};
class SlavePort : public QueuedSlavePort
class ResponsePort : public QueuedSlavePort
{
public:
SlavePort(const std::string &_name, MemDelay &_parent);
ResponsePort(const std::string &_name, MemDelay &_parent);
protected:
Tick recvAtomic(PacketPtr pkt) override;
@@ -122,8 +122,8 @@ class MemDelay : public ClockedObject
bool trySatisfyFunctional(PacketPtr pkt);
MasterPort masterPort;
SlavePort slavePort;
RequestPort masterPort;
ResponsePort slavePort;
ReqPacketQueue reqQueue;
RespPacketQueue respQueue;

8
src/mem/noncoherent_xbar.cc
View File

@@ -58,7 +58,7 @@ NoncoherentXBar::NoncoherentXBar(const NoncoherentXBarParams *p)
// are enumerated starting from zero
for (int i = 0; i < p->port_master_connection_count; ++i) {
std::string portName = csprintf("%s.master[%d]", name(), i);
MasterPort* bp = new NoncoherentXBarMasterPort(portName, *this, i);
RequestPort* bp = new NoncoherentXBarMasterPort(portName, *this, i);
masterPorts.push_back(bp);
reqLayers.push_back(new ReqLayer(*bp, *this,
csprintf("reqLayer%d", i)));
@@ -69,7 +69,7 @@ NoncoherentXBar::NoncoherentXBar(const NoncoherentXBarParams *p)
if (p->port_default_connection_count) {
defaultPortID = masterPorts.size();
std::string portName = name() + ".default";
MasterPort* bp = new NoncoherentXBarMasterPort(portName, *this,
RequestPort* bp = new NoncoherentXBarMasterPort(portName, *this,
defaultPortID);
masterPorts.push_back(bp);
reqLayers.push_back(new ReqLayer(*bp, *this, csprintf("reqLayer%d",
@@ -98,7 +98,7 @@ bool
NoncoherentXBar::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
{
// determine the source port based on the id
SlavePort *src_port = slavePorts[slave_port_id];
ResponsePort *src_port = slavePorts[slave_port_id];
// we should never see express snoops on a non-coherent crossbar
assert(!pkt->isExpressSnoop());
@@ -176,7 +176,7 @@ bool
NoncoherentXBar::recvTimingResp(PacketPtr pkt, PortID master_port_id)
{
// determine the source port based on the id
MasterPort *src_port = masterPorts[master_port_id];
RequestPort *src_port = masterPorts[master_port_id];
// determine the destination
const auto route_lookup = routeTo.find(pkt->req);

4
src/mem/noncoherent_xbar.hh
View File

@@ -135,7 +135,7 @@ class NoncoherentXBar : public BaseXBar
* instantiated for each of the slave ports connecting to the
* crossbar.
*/
class NoncoherentXBarMasterPort : public MasterPort
class NoncoherentXBarMasterPort : public RequestPort
{
private:
@@ -146,7 +146,7 @@ class NoncoherentXBar : public BaseXBar
NoncoherentXBarMasterPort(const std::string &_name,
NoncoherentXBar &_xbar, PortID _id)
: MasterPort(_name, &_xbar, _id), xbar(_xbar)
: RequestPort(_name, &_xbar, _id), xbar(_xbar)
{ }
protected:

6
src/mem/packet_queue.cc
View File

@@ -232,7 +232,7 @@ PacketQueue::drain()
}
}
ReqPacketQueue::ReqPacketQueue(EventManager& _em, MasterPort& _masterPort,
ReqPacketQueue::ReqPacketQueue(EventManager& _em, RequestPort& _masterPort,
const std::string _label)
: PacketQueue(_em, _label, name(_masterPort, _label)),
masterPort(_masterPort)
@@ -246,7 +246,7 @@ ReqPacketQueue::sendTiming(PacketPtr pkt)
}
SnoopRespPacketQueue::SnoopRespPacketQueue(EventManager& _em,
MasterPort& _masterPort,
RequestPort& _masterPort,
bool force_order,
const std::string _label)
: PacketQueue(_em, _label, name(_masterPort, _label), force_order),
@@ -260,7 +260,7 @@ SnoopRespPacketQueue::sendTiming(PacketPtr pkt)
return masterPort.sendTimingSnoopResp(pkt);
}
RespPacketQueue::RespPacketQueue(EventManager& _em, SlavePort& _slavePort,
RespPacketQueue::RespPacketQueue(EventManager& _em, ResponsePort& _slavePort,
bool force_order,
const std::string _label)
: PacketQueue(_em, _label, name(_slavePort, _label), force_order),

18
src/mem/packet_queue.hh
View File

@@ -224,11 +224,11 @@ class ReqPacketQueue : public PacketQueue
protected:
MasterPort& masterPort;
RequestPort& masterPort;
// Static definition so it can be called when constructing the parent
// without us being completely initialized.
static const std::string name(const MasterPort& masterPort,
static const std::string name(const RequestPort& masterPort,
const std::string& label)
{ return masterPort.name() + "-" + label; }
@@ -243,7 +243,7 @@ class ReqPacketQueue : public PacketQueue
* @param _masterPort Master port used to send the packets
* @param _label Label to push on the label stack for print request packets
*/
ReqPacketQueue(EventManager& _em, MasterPort& _masterPort,
ReqPacketQueue(EventManager& _em, RequestPort& _masterPort,
const std::string _label = "ReqPacketQueue");
virtual ~ReqPacketQueue() { }
@@ -260,11 +260,11 @@ class SnoopRespPacketQueue : public PacketQueue
protected:
MasterPort& masterPort;
RequestPort& masterPort;
// Static definition so it can be called when constructing the parent
// without us being completely initialized.
static const std::string name(const MasterPort& masterPort,
static const std::string name(const RequestPort& masterPort,
const std::string& label)
{ return masterPort.name() + "-" + label; }
@@ -280,7 +280,7 @@ class SnoopRespPacketQueue : public PacketQueue
* @param force_order Force insertion order for packets with same address
* @param _label Label to push on the label stack for print request packets
*/
SnoopRespPacketQueue(EventManager& _em, MasterPort& _masterPort,
SnoopRespPacketQueue(EventManager& _em, RequestPort& _masterPort,
bool force_order = false,
const std::string _label = "SnoopRespPacketQueue");
@@ -298,11 +298,11 @@ class RespPacketQueue : public PacketQueue
protected:
SlavePort& slavePort;
ResponsePort& slavePort;
// Static definition so it can be called when constructing the parent
// without us being completely initialized.
static const std::string name(const SlavePort& slavePort,
static const std::string name(const ResponsePort& slavePort,
const std::string& label)
{ return slavePort.name() + "-" + label; }
@@ -318,7 +318,7 @@ class RespPacketQueue : public PacketQueue
* @param force_order Force insertion order for packets with same address
* @param _label Label to push on the label stack for print request packets
*/
RespPacketQueue(EventManager& _em, SlavePort& _slavePort,
RespPacketQueue(EventManager& _em, ResponsePort& _slavePort,
bool force_order = false,
const std::string _label = "RespPacketQueue");

2
src/mem/port_proxy.hh
View File

@@ -100,7 +100,7 @@ class PortProxy : FunctionalRequestProtocol
PortProxy(SendFunctionalFunc func, unsigned int cacheLineSize) :
sendFunctional(func), _cacheLineSize(cacheLineSize)
{}
PortProxy(const MasterPort &port, unsigned int cacheLineSize) :
PortProxy(const RequestPort &port, unsigned int cacheLineSize) :
sendFunctional([&port](PacketPtr pkt)->void {
port.sendFunctional(pkt);
}), _cacheLineSize(cacheLineSize)

2
src/mem/qos/QoSMemSinkCtrl.py
View File

@@ -42,7 +42,7 @@ class QoSMemSinkCtrl(QoSMemCtrl):
type = 'QoSMemSinkCtrl'
cxx_header = "mem/qos/mem_sink.hh"
cxx_class = "QoS::MemSinkCtrl"
port = SlavePort("Slave ports")
port = ResponsePort("Response ports")
# the basic configuration of the controller architecture, note
# that each entry corresponds to a burst for the specific DRAM

8
src/mem/qport.hh
View File

@@ -55,7 +55,7 @@
* queue is a parameter to allow tailoring of the queue implementation
* (used in the cache).
*/
class QueuedSlavePort : public SlavePort
class QueuedSlavePort : public ResponsePort
{
protected:
@@ -76,7 +76,7 @@ class QueuedSlavePort : public SlavePort
*/
QueuedSlavePort(const std::string& name, SimObject* owner,
RespPacketQueue &resp_queue, PortID id = InvalidPortID) :
SlavePort(name, owner, id), respQueue(resp_queue)
ResponsePort(name, owner, id), respQueue(resp_queue)
{ }
virtual ~QueuedSlavePort() { }
@@ -103,7 +103,7 @@ class QueuedSlavePort : public SlavePort
* independent, and so each queue manages its own flow control
* (retries).
*/
class QueuedMasterPort : public MasterPort
class QueuedMasterPort : public RequestPort
{
protected:
@@ -131,7 +131,7 @@ class QueuedMasterPort : public MasterPort
ReqPacketQueue &req_queue,
SnoopRespPacketQueue &snoop_resp_queue,
PortID id = InvalidPortID) :
MasterPort(name, owner, id), reqQueue(req_queue),
RequestPort(name, owner, id), reqQueue(req_queue),
snoopRespQueue(snoop_resp_queue)
{ }

4
src/mem/ruby/network/MessageBuffer.py
View File

@@ -40,5 +40,5 @@ class MessageBuffer(SimObject):
random delays if RubySystem \
randomization flag is True)")
master = MasterPort("Master port to MessageBuffer receiver")
slave = SlavePort("Slave port from MessageBuffer sender")
master = RequestPort("Master port to MessageBuffer receiver")
slave = ResponsePort("Slave port from MessageBuffer sender")

2
src/mem/ruby/slicc_interface/AbstractController.cc
View File

@@ -373,6 +373,6 @@ AbstractController::MemoryPort::recvReqRetry()
AbstractController::MemoryPort::MemoryPort(const std::string &_name,
AbstractController *_controller,
PortID id)
: MasterPort(_name, _controller, id), controller(_controller)
: RequestPort(_name, _controller, id), controller(_controller)
{
}

2
src/mem/ruby/slicc_interface/AbstractController.hh
View File

@@ -218,7 +218,7 @@ class AbstractController : public ClockedObject, public Consumer
* Port that forwards requests and receives responses from the
* memory controller.
*/
class MemoryPort : public MasterPort
class MemoryPort : public RequestPort
{
private:
// Controller that operates this port.

2
src/mem/ruby/slicc_interface/Controller.py
View File

@@ -66,5 +66,5 @@ class RubyController(ClockedObject):
Param.Cycles(1, "Default latency for requests added to the " \
"mandatory queue on top-level controllers")
memory = MasterPort("Port for attaching a memory controller")
memory = RequestPort("Port for attaching a memory controller")
system = Param.System(Parent.any, "system object parameter")

8
src/mem/ruby/system/Sequencer.py
View File

@@ -36,10 +36,10 @@ class RubyPort(ClockedObject):
slave = VectorSlavePort("CPU slave port")
master = VectorMasterPort("CPU master port")
pio_master_port = MasterPort("Ruby mem master port")
mem_master_port = MasterPort("Ruby mem master port")
pio_slave_port = SlavePort("Ruby pio slave port")
mem_slave_port = SlavePort("Ruby memory port")
pio_master_port = RequestPort("Ruby mem master port")
mem_master_port = RequestPort("Ruby mem master port")
pio_slave_port = ResponsePort("Ruby pio slave port")
mem_slave_port = ResponsePort("Ruby memory port")
using_ruby_tester = Param.Bool(False, "")
no_retry_on_stall = Param.Bool(False, "")

4
src/mem/serial_link.cc
View File

@@ -57,7 +57,7 @@ SerialLink::SerialLinkSlavePort::SerialLinkSlavePort(const std::string& _name,
Cycles _delay, int _resp_limit,
const std::vector<AddrRange>&
_ranges)
: SlavePort(_name, &_serial_link), serial_link(_serial_link),
: ResponsePort(_name, &_serial_link), serial_link(_serial_link),
masterPort(_masterPort), delay(_delay),
ranges(_ranges.begin(), _ranges.end()),
outstandingResponses(0), retryReq(false),
@@ -70,7 +70,7 @@ SerialLink::SerialLinkMasterPort::SerialLinkMasterPort(const std::string&
_name, SerialLink& _serial_link,
SerialLinkSlavePort& _slavePort,
Cycles _delay, int _req_limit)
: MasterPort(_name, &_serial_link), serial_link(_serial_link),
: RequestPort(_name, &_serial_link), serial_link(_serial_link),
slavePort(_slavePort), delay(_delay), reqQueueLimit(_req_limit),
sendEvent([this]{ trySendTiming(); }, _name)
{

4
src/mem/serial_link.hh
View File

@@ -91,7 +91,7 @@ class SerialLink : public ClockedObject
* is responsible for. The slave port also has a buffer for the
* responses not yet sent.
*/
class SerialLinkSlavePort : public SlavePort
class SerialLinkSlavePort : public ResponsePort
{
private:
@@ -207,7 +207,7 @@ class SerialLink : public ClockedObject
* responses. The master port has a buffer for the requests not
* yet sent.
*/
class SerialLinkMasterPort : public MasterPort
class SerialLinkMasterPort : public RequestPort
{
private:

10
src/mem/snoop_filter.cc
View File

@@ -61,7 +61,7 @@ SnoopFilter::eraseIfNullEntry(SnoopFilterCache::iterator& sf_it)
}
std::pair<SnoopFilter::SnoopList, Cycles>
SnoopFilter::lookupRequest(const Packet* cpkt, const SlavePort& slave_port)
SnoopFilter::lookupRequest(const Packet* cpkt, const ResponsePort& slave_port)
{
DPRINTF(SnoopFilter, "%s: src %s packet %s\n", __func__,
slave_port.name(), cpkt->print());
@@ -240,8 +240,8 @@ SnoopFilter::lookupSnoop(const Packet* cpkt)
void
SnoopFilter::updateSnoopResponse(const Packet* cpkt,
const SlavePort& rsp_port,
const SlavePort& req_port)
const ResponsePort& rsp_port,
const ResponsePort& req_port)
{
DPRINTF(SnoopFilter, "%s: rsp %s req %s packet %s\n",
__func__, rsp_port.name(), req_port.name(), cpkt->print());
@@ -297,7 +297,7 @@ SnoopFilter::updateSnoopResponse(const Packet* cpkt,
void
SnoopFilter::updateSnoopForward(const Packet* cpkt,
const SlavePort& rsp_port, const MasterPort& req_port)
const ResponsePort& rsp_port, const RequestPort& req_port)
{
DPRINTF(SnoopFilter, "%s: rsp %s req %s packet %s\n",
__func__, rsp_port.name(), req_port.name(), cpkt->print());
@@ -333,7 +333,7 @@ SnoopFilter::updateSnoopForward(const Packet* cpkt,
}
void
SnoopFilter::updateResponse(const Packet* cpkt, const SlavePort& slave_port)
SnoopFilter::updateResponse(const Packet* cpkt, const ResponsePort& slave_port)
{
DPRINTF(SnoopFilter, "%s: src %s packet %s\n",
__func__, slave_port.name(), cpkt->print());

36
src/mem/snoop_filter.hh
View File

@@ -135,7 +135,7 @@ class SnoopFilter : public SimObject {
* @return Pair of a vector of snoop target ports and lookup latency.
*/
std::pair<SnoopList, Cycles> lookupRequest(const Packet* cpkt,
const SlavePort& slave_port);
const ResponsePort& slave_port);
/**
* For an un-successful request, revert the change to the snoop
@@ -154,8 +154,8 @@ class SnoopFilter : public SimObject {
* additional steering thanks to the snoop filter.
*
* @param cpkt Pointer to const Packet containing the snoop.
* @return Pair with a vector of SlavePorts that need snooping and a lookup
* latency.
* @return Pair with a vector of ResponsePorts that need snooping and a
* lookup latency.
*/
std::pair<SnoopList, Cycles> lookupSnoop(const Packet* cpkt);
@@ -165,12 +165,12 @@ class SnoopFilter : public SimObject {
* will update the corresponding state in the filter.
*
* @param cpkt Pointer to const Packet holding the snoop response.
* @param rsp_port SlavePort that sends the response.
* @param req_port SlavePort that made the original request and is the
* @param rsp_port ResponsePort that sends the response.
* @param req_port ResponsePort that made the original request and is the
* destination of the snoop response.
*/
void updateSnoopResponse(const Packet *cpkt, const SlavePort& rsp_port,
const SlavePort& req_port);
void updateSnoopResponse(const Packet *cpkt, const ResponsePort& rsp_port,
const ResponsePort& req_port);
/**
* Pass snoop responses that travel downward through the snoop
@@ -178,11 +178,11 @@ class SnoopFilter : public SimObject {
* additional routing happens.
*
* @param cpkt Pointer to const Packet holding the snoop response.
* @param rsp_port SlavePort that sends the response.
* @param req_port MasterPort through which the response is forwarded.
* @param rsp_port ResponsePort that sends the response.
* @param req_port RequestPort through which the response is forwarded.
*/
void updateSnoopForward(const Packet *cpkt, const SlavePort& rsp_port,
const MasterPort& req_port);
void updateSnoopForward(const Packet *cpkt, const ResponsePort& rsp_port,
const RequestPort& req_port);
/**
* Update the snoop filter with a response from below (outer /
@@ -190,10 +190,10 @@ class SnoopFilter : public SimObject {
* the snoop filter.
*
* @param cpkt Pointer to const Packet holding the snoop response.
* @param slave_port SlavePort that made the original request and
* @param slave_port ResponsePort that made the original request and
* is the target of this response.
*/
void updateResponse(const Packet *cpkt, const SlavePort& slave_port);
void updateResponse(const Packet *cpkt, const ResponsePort& slave_port);
virtual void regStats();
@@ -206,7 +206,7 @@ class SnoopFilter : public SimObject {
typedef std::bitset<SNOOP_MASK_SIZE> SnoopMask;
/**
* Per cache line item tracking a bitmask of SlavePorts who have an
* Per cache line item tracking a bitmask of ResponsePorts who have an
* outstanding request to this line (requested) or already share a
* cache line with this address (holder).
*/
@@ -239,14 +239,14 @@ class SnoopFilter : public SimObject {
/**
* Convert a single port to a corresponding, one-hot bitmask
* @param port SlavePort that should be converted.
* @param port ResponsePort that should be converted.
* @return One-hot bitmask corresponding to the port.
*/
SnoopMask portToMask(const SlavePort& port) const;
SnoopMask portToMask(const ResponsePort& port) const;
/**
* Converts a bitmask of ports into the corresponing list of ports
* @param ports SnoopMask of the requested ports
* @return SnoopList containing all the requested SlavePorts
* @return SnoopList containing all the requested ResponsePorts
*/
SnoopList maskToPortList(SnoopMask ports) const;
@@ -320,7 +320,7 @@ class SnoopFilter : public SimObject {
};
inline SnoopFilter::SnoopMask
SnoopFilter::portToMask(const SlavePort& port) const
SnoopFilter::portToMask(const ResponsePort& port) const
{
assert(port.getId() != InvalidPortID);
// if this is not a snooping port, return a zero mask

12
src/mem/token_port.cc
View File

@@ -42,7 +42,7 @@
void
TokenMasterPort::bind(Port &peer)
{
MasterPort::bind(peer);
RequestPort::bind(peer);
}
void
@@ -88,10 +88,10 @@ void
TokenSlavePort::bind(Port& peer)
{
// TokenSlavePort is allowed to bind to either TokenMasterPort or a
// MasterPort as fallback. If the type is a MasterPort, tokenMasterPort
// RequestPort as fallback. If the type is a RequestPort, tokenMasterPort
// is set to nullptr to indicate tokens should not be exchanged.
auto *token_master_port = dynamic_cast<TokenMasterPort*>(&peer);
auto *master_port = dynamic_cast<MasterPort*>(&peer);
auto *master_port = dynamic_cast<RequestPort*>(&peer);
if (!token_master_port && !master_port) {
fatal("Attempt to bind port %s to unsupported slave port %s.",
name(), peer.name());
@@ -109,7 +109,7 @@ TokenSlavePort::bind(Port& peer)
void
TokenSlavePort::unbind()
{
SlavePort::responderUnbind();
ResponsePort::responderUnbind();
tokenMasterPort = nullptr;
}
@@ -121,7 +121,7 @@ TokenSlavePort::recvRespRetry()
"Attempted to retry a response when no retry was queued!\n");
PacketPtr pkt = respQueue.front();
bool success = SlavePort::sendTimingResp(pkt);
bool success = ResponsePort::sendTimingResp(pkt);
if (success) {
respQueue.pop_front();
@@ -131,7 +131,7 @@ TokenSlavePort::recvRespRetry()
bool
TokenSlavePort::sendTimingResp(PacketPtr pkt)
{
bool success = SlavePort::sendTimingResp(pkt);
bool success = ResponsePort::sendTimingResp(pkt);
if (!success) {
respQueue.push_back(pkt);

8
src/mem/token_port.hh
View File

@@ -40,7 +40,7 @@
class TokenManager;
class TokenSlavePort;
class TokenMasterPort : public MasterPort
class TokenMasterPort : public RequestPort
{
private:
/* Manager to track tokens between this token port pair. */
@@ -49,7 +49,7 @@ class TokenMasterPort : public MasterPort
public:
TokenMasterPort(const std::string& name, SimObject* owner,
PortID id = InvalidPortID) :
MasterPort(name, owner, id), tokenManager(nullptr)
RequestPort(name, owner, id), tokenManager(nullptr)
{ }
/**
@@ -87,7 +87,7 @@ class TokenMasterPort : public MasterPort
void setTokenManager(TokenManager *_tokenManager);
};
class TokenSlavePort : public SlavePort
class TokenSlavePort : public ResponsePort
{
private:
TokenMasterPort *tokenMasterPort;
@@ -99,7 +99,7 @@ class TokenSlavePort : public SlavePort
public:
TokenSlavePort(const std::string& name, ClockedObject *owner,
PortID id = InvalidPortID) :
SlavePort(name, owner, id), tokenMasterPort(nullptr)
ResponsePort(name, owner, id), tokenMasterPort(nullptr)
{ }
~TokenSlavePort() { }

8
src/mem/xbar.cc
View File

@@ -592,8 +592,8 @@ BaseXBar::Layer<SrcType, DstType>::drain()
/**
* Crossbar layer template instantiations. Could be removed with _impl.hh
* file, but since there are only two given options (MasterPort and
* SlavePort) it seems a bit excessive at this point.
* file, but since there are only two given options (RequestPort and
* ResponsePort) it seems a bit excessive at this point.
*/
template class BaseXBar::Layer<SlavePort, MasterPort>;
template class BaseXBar::Layer<MasterPort, SlavePort>;
template class BaseXBar::Layer<ResponsePort, RequestPort>;
template class BaseXBar::Layer<RequestPort, ResponsePort>;

23
src/mem/xbar.hh
View File

@@ -165,7 +165,7 @@ class BaseXBar : public ClockedObject
/**
* Sending the actual retry, in a manner specific to the
* individual layers. Note that for a MasterPort, there is
* individual layers. Note that for a RequestPort, there is
* both a RequestLayer and a SnoopResponseLayer using the same
* port, but using different functions for the flow control.
*/
@@ -231,7 +231,7 @@ class BaseXBar : public ClockedObject
};
class ReqLayer : public Layer<SlavePort, MasterPort>
class ReqLayer : public Layer<ResponsePort, RequestPort>
{
public:
/**
@@ -241,19 +241,20 @@ class BaseXBar : public ClockedObject
* @param _xbar the crossbar this layer belongs to
* @param _name the layer's name
*/
ReqLayer(MasterPort& _port, BaseXBar& _xbar, const std::string& _name) :
ReqLayer(RequestPort& _port, BaseXBar& _xbar,
const std::string& _name) :
Layer(_port, _xbar, _name)
{}
protected:
void
sendRetry(SlavePort* retry_port) override
sendRetry(ResponsePort* retry_port) override
{
retry_port->sendRetryReq();
}
};
class RespLayer : public Layer<MasterPort, SlavePort>
class RespLayer : public Layer<RequestPort, ResponsePort>
{
public:
/**
@@ -263,20 +264,20 @@ class BaseXBar : public ClockedObject
* @param _xbar the crossbar this layer belongs to
* @param _name the layer's name
*/
RespLayer(SlavePort& _port, BaseXBar& _xbar,
RespLayer(ResponsePort& _port, BaseXBar& _xbar,
const std::string& _name) :
Layer(_port, _xbar, _name)
{}
protected:
void
sendRetry(MasterPort* retry_port) override
sendRetry(RequestPort* retry_port) override
{
retry_port->sendRetryResp();
}
};
class SnoopRespLayer : public Layer<SlavePort, MasterPort>
class SnoopRespLayer : public Layer<ResponsePort, RequestPort>
{
public:
/**
@@ -286,7 +287,7 @@ class BaseXBar : public ClockedObject
* @param _xbar the crossbar this layer belongs to
* @param _name the layer's name
*/
SnoopRespLayer(MasterPort& _port, BaseXBar& _xbar,
SnoopRespLayer(RequestPort& _port, BaseXBar& _xbar,
const std::string& _name) :
Layer(_port, _xbar, _name)
{}
@@ -294,7 +295,7 @@ class BaseXBar : public ClockedObject
protected:
void
sendRetry(SlavePort* retry_port) override
sendRetry(ResponsePort* retry_port) override
{
retry_port->sendRetrySnoopResp();
}
@@ -373,7 +374,7 @@ class BaseXBar : public ClockedObject
/** The master and slave ports of the crossbar */
std::vector<QueuedSlavePort*> slavePorts;
std::vector<MasterPort*> masterPorts;
std::vector<RequestPort*> masterPorts;
/** Port that handles requests that don't match any of the interfaces.*/
PortID defaultPortID;