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gpu-compute: update port terminology

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Change-Id: I3121c4afb1e137aebe09c1d694e9484844d02b9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32313
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Poremba <chesp3@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Emily Brickey
2020-08-04 12:22:14 -07:00
committed by Shivani Parekh
parent 1447017039
commit 6333e914d3
9 changed files with 37 additions and 36 deletions
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13
src/gpu-compute/GPU.py
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@@ -161,11 +161,12 @@ class ComputeUnit(ClockedObject):
memory_port = VectorMasterPort("Port to the memory system")
translation_port = VectorMasterPort('Port to the TLB hierarchy')
sqc_port = MasterPort("Port to the SQC (I-cache")
sqc_tlb_port = MasterPort("Port to the TLB for the SQC (I-cache)")
scalar_port = MasterPort("Port to the scalar data cache")
scalar_tlb_port = MasterPort("Port to the TLB for the scalar data cache")
gmTokenPort = MasterPort("Port to the GPU coalesecer for sharing tokens")
sqc_port = RequestPort("Port to the SQC (I-cache")
sqc_tlb_port = RequestPort("Port to the TLB for the SQC (I-cache)")
scalar_port = RequestPort("Port to the scalar data cache")
scalar_tlb_port = RequestPort("Port to the TLB for the scalar data cache")
gmTokenPort = RequestPort("Port to the GPU coalesecer for sharing tokens")
perLaneTLB = Param.Bool(False, "enable per-lane TLB")
prefetch_depth = Param.Int(0, "Number of prefetches triggered at a time"\
"(0 turns off prefetching)")
@@ -193,7 +194,7 @@ class ComputeUnit(ClockedObject):
max_cu_tokens = Param.Int(4, "Maximum number of tokens, i.e., the number"\
" of instructions that can be sent to coalescer")
ldsBus = Bridge() # the bridge between the CU and its LDS
ldsPort = MasterPort("The port that goes to the LDS")
ldsPort = RequestPort("The port that goes to the LDS")
localDataStore = Param.LdsState("the LDS for this CU")
vector_register_file = VectorParam.VectorRegisterFile("Vector register "\

2
src/gpu-compute/LdsState.py
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@@ -44,4 +44,4 @@ class LdsState(ClockedObject):
bankConflictPenalty = Param.Int(1, 'penalty per LDS bank conflict when '\
'accessing data')
banks = Param.Int(32, 'Number of LDS banks')
cuPort = SlavePort("port that goes to the compute unit")
cuPort = ResponsePort("port that goes to the compute unit")

2
src/gpu-compute/X86GPUTLB.py
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@@ -40,7 +40,7 @@ if buildEnv['FULL_SYSTEM']:
class X86PagetableWalker(SimObject):
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
port = SlavePort("Port for the hardware table walker")
port = ResponsePort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
class X86GPUTLB(ClockedObject):

4
src/gpu-compute/compute_unit.cc
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@@ -2590,7 +2590,7 @@ ComputeUnit::LDSPort::sendTimingReq(PacketPtr pkt)
computeUnit->cu_id, gpuDynInst->simdId,
gpuDynInst->wfSlotId);
return false;
} else if (!MasterPort::sendTimingReq(pkt)) {
} else if (!RequestPort::sendTimingReq(pkt)) {
// need to stall the LDS port until a recvReqRetry() is received
// this indicates that there is more space
stallPort();
@@ -2634,7 +2634,7 @@ ComputeUnit::LDSPort::recvReqRetry()
DPRINTF(GPUPort, "CU%d: retrying LDS send\n", computeUnit->cu_id);
if (!MasterPort::sendTimingReq(packet)) {
if (!RequestPort::sendTimingReq(packet)) {
// Stall port
stallPort();
DPRINTF(GPUPort, ": LDS send failed again\n");

28
src/gpu-compute/compute_unit.hh
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@@ -649,11 +649,11 @@ class ComputeUnit : public ClockedObject
GMTokenPort gmTokenPort;
/** Data access Port **/
class DataPort : public MasterPort
class DataPort : public RequestPort
{
public:
DataPort(const std::string &_name, ComputeUnit *_cu, PortID _index)
: MasterPort(_name, _cu), computeUnit(_cu),
: RequestPort(_name, _cu), computeUnit(_cu),
index(_index) { }
bool snoopRangeSent;
@@ -699,12 +699,12 @@ class ComputeUnit : public ClockedObject
};
// Scalar data cache access port
class ScalarDataPort : public MasterPort
class ScalarDataPort : public RequestPort
{
public:
ScalarDataPort(const std::string &_name, ComputeUnit *_cu,
PortID _index)
: MasterPort(_name, _cu, _index), computeUnit(_cu), index(_index)
: RequestPort(_name, _cu, _index), computeUnit(_cu), index(_index)
{
(void)index;
}
@@ -749,11 +749,11 @@ class ComputeUnit : public ClockedObject
};
// Instruction cache access port
class SQCPort : public MasterPort
class SQCPort : public RequestPort
{
public:
SQCPort(const std::string &_name, ComputeUnit *_cu, PortID _index)
: MasterPort(_name, _cu), computeUnit(_cu),
: RequestPort(_name, _cu), computeUnit(_cu),
index(_index) { }
bool snoopRangeSent;
@@ -792,11 +792,11 @@ class ComputeUnit : public ClockedObject
};
/** Data TLB port **/
class DTLBPort : public MasterPort
class DTLBPort : public RequestPort
{
public:
DTLBPort(const std::string &_name, ComputeUnit *_cu, PortID _index)
: MasterPort(_name, _cu), computeUnit(_cu),
: RequestPort(_name, _cu), computeUnit(_cu),
index(_index), stalled(false)
{ }
@@ -840,11 +840,11 @@ class ComputeUnit : public ClockedObject
virtual void recvReqRetry();
};
class ScalarDTLBPort : public MasterPort
class ScalarDTLBPort : public RequestPort
{
public:
ScalarDTLBPort(const std::string &_name, ComputeUnit *_cu)
: MasterPort(_name, _cu), computeUnit(_cu), stalled(false)
: RequestPort(_name, _cu), computeUnit(_cu), stalled(false)
{
}
@@ -868,11 +868,11 @@ class ComputeUnit : public ClockedObject
bool stalled;
};
class ITLBPort : public MasterPort
class ITLBPort : public RequestPort
{
public:
ITLBPort(const std::string &_name, ComputeUnit *_cu)
: MasterPort(_name, _cu), computeUnit(_cu), stalled(false) { }
: RequestPort(_name, _cu), computeUnit(_cu), stalled(false) { }
bool isStalled() { return stalled; }
@@ -910,11 +910,11 @@ class ComputeUnit : public ClockedObject
/**
* the port intended to communicate between the CU and its LDS
*/
class LDSPort : public MasterPort
class LDSPort : public RequestPort
{
public:
LDSPort(const std::string &_name, ComputeUnit *_cu, PortID _id)
: MasterPort(_name, _cu, _id), computeUnit(_cu)
: RequestPort(_name, _cu, _id), computeUnit(_cu)
{
}

10
src/gpu-compute/gpu_tlb.hh
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@@ -236,12 +236,12 @@ namespace X86ISA
void issueTLBLookup(PacketPtr pkt);
// CpuSidePort is the TLB Port closer to the CPU/CU side
class CpuSidePort : public SlavePort
class CpuSidePort : public ResponsePort
{
public:
CpuSidePort(const std::string &_name, GpuTLB * gpu_TLB,
PortID _index)
: SlavePort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
: ResponsePort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
protected:
GpuTLB *tlb;
@@ -263,12 +263,12 @@ namespace X86ISA
* Future action item: if we ever do real page walks, then this port
* should be connected to a RubyPort.
*/
class MemSidePort : public MasterPort
class MemSidePort : public RequestPort
{
public:
MemSidePort(const std::string &_name, GpuTLB * gpu_TLB,
PortID _index)
: MasterPort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
: RequestPort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
std::deque<PacketPtr> retries;
@@ -325,7 +325,7 @@ namespace X86ISA
// When was the req for this translation issued
uint64_t issueTime;
// Remember where this came from
std::vector<SlavePort*>ports;
std::vector<ResponsePort*>ports;
// keep track of #uncoalesced reqs per packet per TLB level;
// reqCnt per level >= reqCnt higher level

4
src/gpu-compute/lds_state.hh
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@@ -157,11 +157,11 @@ class LdsState: public ClockedObject
/**
* CuSidePort is the LDS Port closer to the CU side
*/
class CuSidePort: public SlavePort
class CuSidePort: public ResponsePort
{
public:
CuSidePort(const std::string &_name, LdsState *_ownerLds) :
SlavePort(_name, _ownerLds), ownerLds(_ownerLds)
ResponsePort(_name, _ownerLds), ownerLds(_ownerLds)
{
}

2
src/gpu-compute/tlb_coalescer.cc
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@@ -198,7 +198,7 @@ TLBCoalescer::updatePhysAddresses(PacketPtr pkt)
sender_state->hitLevel = first_hit_level;
}
SlavePort *return_port = sender_state->ports.back();
ResponsePort *return_port = sender_state->ports.back();
sender_state->ports.pop_back();
// Translation is done - Convert to a response pkt if necessary and

8
src/gpu-compute/tlb_coalescer.hh
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@@ -137,12 +137,12 @@ class TLBCoalescer : public ClockedObject
void updatePhysAddresses(PacketPtr pkt);
void regStats() override;
class CpuSidePort : public SlavePort
class CpuSidePort : public ResponsePort
{
public:
CpuSidePort(const std::string &_name, TLBCoalescer *tlb_coalescer,
PortID _index)
: SlavePort(_name, tlb_coalescer), coalescer(tlb_coalescer),
: ResponsePort(_name, tlb_coalescer), coalescer(tlb_coalescer),
index(_index) { }
protected:
@@ -165,12 +165,12 @@ class TLBCoalescer : public ClockedObject
virtual AddrRangeList getAddrRanges() const;
};
class MemSidePort : public MasterPort
class MemSidePort : public RequestPort
{
public:
MemSidePort(const std::string &_name, TLBCoalescer *tlb_coalescer,
PortID _index)
: MasterPort(_name, tlb_coalescer), coalescer(tlb_coalescer),
: RequestPort(_name, tlb_coalescer), coalescer(tlb_coalescer),
index(_index) { }
std::deque<PacketPtr> retries;