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mem: Clean up Memory Controller

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Make the actual controller more generic
    - Rename DRAMCtrl to MemCtrl
    - Rename DRAMacket to MemPacket
    - Rename dram_ctrl.cc to mem_ctrl.cc
    - Rename dram_ctrl.hh to mem_ctrl.hh
    - Create MemCtrl debug flag

Move the memory interface classes/functions to separate files
    - mem_interface.cc
    - mem_interface.hh

Change-Id: I1acba44c855776343e205e7733a7d8bbba92a82c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31654
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Wendy Elsasser
2020-07-20 23:09:21 -05:00
committed by Jason Lowe-Power
parent dab7c78eca
commit 7a28c82c6e
24 changed files with 2328 additions and 2230 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
configs/common/MemConfig.py
View File

@@ -224,11 +224,11 @@ def config_mem(options, system):
if opt_mem_type == "HMC_2500_1x32":
# The static latency of the vault controllers is estimated
# to be smaller than a full DRAM channel controller
mem_ctrl = m5.objects.DRAMCtrl(min_writes_per_switch = 8,
mem_ctrl = m5.objects.MemCtrl(min_writes_per_switch = 8,
static_backend_latency = '4ns',
static_frontend_latency = '4ns')
else:
mem_ctrl = m5.objects.DRAMCtrl()
mem_ctrl = m5.objects.MemCtrl()
# Hookup the controller to the interface and add to the list
mem_ctrl.dram = dram_intf
@@ -246,7 +246,7 @@ def config_mem(options, system):
# Create a controller if not sharing a channel with DRAM
# in which case the controller has already been created
if not opt_hybrid_channel:
mem_ctrl = m5.objects.DRAMCtrl()
mem_ctrl = m5.objects.MemCtrl()
mem_ctrl.nvm = nvm_intf
mem_ctrls.append(mem_ctrl)

2
configs/common/Options.py
View File

@@ -109,7 +109,7 @@ def addNoISAOptions(parser):
default="512MB",
help="Specify the physical memory size (single memory)")
parser.add_option("--enable-dram-powerdown", action="store_true",
help="Enable low-power states in DRAMCtrl")
help="Enable low-power states in DRAMInterface")
parser.add_option("--mem-channels-intlv", type="int", default=0,
help="Memory channels interleave")

2
configs/dram/lat_mem_rd.py
View File

@@ -130,7 +130,7 @@ for ctrl in system.mem_ctrls:
# the following assumes that we are using the native DRAM
# controller, check to be sure
if isinstance(ctrl, m5.objects.DRAMCtrl):
if isinstance(ctrl, m5.objects.MemCtrl):
# make the DRAM refresh interval sufficiently infinite to avoid
# latency spikes
ctrl.tREFI = '100s'

4
configs/dram/low_power_sweep.py
View File

@@ -110,8 +110,8 @@ args.elastic_trace_en = 0
MemConfig.config_mem(args, system)
# Sanity check for memory controller class.
if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
fatal("This script assumes the controller is a DRAMCtrl subclass")
if not isinstance(system.mem_ctrls[0], m5.objects.MemCtrl):
fatal("This script assumes the controller is a MemCtrl subclass")
if not isinstance(system.mem_ctrls[0].dram, m5.objects.DRAMInterface):
fatal("This script assumes the memory is a DRAMInterface subclass")

4
configs/dram/sweep.py
View File

@@ -115,8 +115,8 @@ MemConfig.config_mem(options, system)
# the following assumes that we are using the native DRAM
# controller, check to be sure
if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
fatal("This script assumes the controller is a DRAMCtrl subclass")
if not isinstance(system.mem_ctrls[0], m5.objects.MemCtrl):
fatal("This script assumes the controller is a MemCtrl subclass")
if not isinstance(system.mem_ctrls[0].dram, m5.objects.DRAMInterface):
fatal("This script assumes the memory is a DRAMInterface subclass")

2
configs/example/memcheck.py
View File

@@ -217,7 +217,7 @@ cfg_file.close()
proto_tester = TrafficGen(config_file = cfg_file_path)
# Set up the system along with a DRAM controller
system = System(physmem = DRAMCtrl(dram = DDR3_1600_8x8()))
system = System(physmem = MemCtrl(dram = DDR3_1600_8x8()))
system.voltage_domain = VoltageDomain(voltage = '1V')

2
configs/learning_gem5/part1/simple.py
View File

@@ -77,7 +77,7 @@ if m5.defines.buildEnv['TARGET_ISA'] == "x86":
system.cpu.interrupts[0].int_slave = system.membus.master
# Create a DDR3 memory controller and connect it to the membus
system.mem_ctrl = DRAMCtrl()
system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master

2
configs/learning_gem5/part1/two_level.py
View File

@@ -132,7 +132,7 @@ if m5.defines.buildEnv['TARGET_ISA'] == "x86":
system.system_port = system.membus.slave
# Create a DDR3 memory controller
system.mem_ctrl = DRAMCtrl()
system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master

2
configs/learning_gem5/part2/simple_cache.py
View File

@@ -76,7 +76,7 @@ system.cpu.interrupts[0].int_master = system.membus.slave
system.cpu.interrupts[0].int_slave = system.membus.master
# Create a DDR3 memory controller and connect it to the membus
system.mem_ctrl = DRAMCtrl()
system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master

2
configs/learning_gem5/part2/simple_memobj.py
View File

@@ -74,7 +74,7 @@ system.cpu.interrupts[0].int_master = system.membus.slave
system.cpu.interrupts[0].int_slave = system.membus.master
# Create a DDR3 memory controller and connect it to the membus
system.mem_ctrl = DRAMCtrl()
system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master

2
configs/learning_gem5/part3/simple_ruby.py
View File

@@ -68,7 +68,7 @@ system.mem_ranges = [AddrRange('512MB')] # Create an address range
system.cpu = [TimingSimpleCPU() for i in range(2)]
# Create a DDR3 memory controller and connect it to the membus
system.mem_ctrl = DRAMCtrl()
system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]

4
configs/nvm/sweep.py
View File

@@ -113,8 +113,8 @@ MemConfig.config_mem(options, system)
# the following assumes that we are using the native memory
# controller with an NVM interface, check to be sure
if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
fatal("This script assumes the controller is a DRAMCtrl subclass")
if not isinstance(system.mem_ctrls[0], m5.objects.MemCtrl):
fatal("This script assumes the controller is a MemCtrl subclass")
if not isinstance(system.mem_ctrls[0].nvm, m5.objects.NVMInterface):
fatal("This script assumes the memory is a NVMInterface class")

4
configs/nvm/sweep_hybrid.py
View File

@@ -126,8 +126,8 @@ MemConfig.config_mem(options, system)
# the following assumes that we are using the native controller
# with NVM and DRAM interfaces, check to be sure
if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
fatal("This script assumes the controller is a DRAMCtrl subclass")
if not isinstance(system.mem_ctrls[0], m5.objects.MemCtrl):
fatal("This script assumes the controller is a MemCtrl subclass")
if not isinstance(system.mem_ctrls[0].dram, m5.objects.DRAMInterface):
fatal("This script assumes the first memory is a DRAMInterface subclass")
if not isinstance(system.mem_ctrls[0].nvm, m5.objects.NVMInterface):

2
configs/ruby/Ruby.py
View File

@@ -133,7 +133,7 @@ def setup_memory_controllers(system, ruby, dir_cntrls, options):
dram_intf = MemConfig.create_mem_intf(mem_type, r, index,
options.num_dirs, int(math.log(options.num_dirs, 2)),
intlv_size, options.xor_low_bit)
mem_ctrl = m5.objects.DRAMCtrl(dram = dram_intf)
mem_ctrl = m5.objects.MemCtrl(dram = dram_intf)
if options.access_backing_store:
mem_ctrl.kvm_map=False

2
src/mem/DRAMInterface.py
View File

@@ -47,7 +47,7 @@ class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
class DRAMInterface(MemInterface):
type = 'DRAMInterface'
cxx_header = "mem/dram_ctrl.hh"
cxx_header = "mem/mem_interface.hh"
# scheduler page policy
page_policy = Param.PageManage('open_adaptive', "Page management policy")

12
src/mem/DRAMCtrl.py → src/mem/MemCtrl.py
View File

@@ -46,13 +46,13 @@ from m5.objects.QoSMemCtrl import *
# First-Served and a First-Row Hit then First-Come First-Served
class MemSched(Enum): vals = ['fcfs', 'frfcfs']
# DRAMCtrl is a single-channel single-ported DRAM controller model
# MemCtrl is a single-channel single-ported Memory controller model
# that aims to model the most important system-level performance
# effects of a DRAM without getting into too much detail of the DRAM
# itself.
class DRAMCtrl(QoSMemCtrl):
type = 'DRAMCtrl'
cxx_header = "mem/dram_ctrl.hh"
# effects of a memory controller, interfacing with media specific
# interfaces
class MemCtrl(QoSMemCtrl):
type = 'MemCtrl'
cxx_header = "mem/mem_ctrl.hh"
# single-ported on the system interface side, instantiate with a
# bus in front of the controller for multiple ports

2
src/mem/MemInterface.py
View File

@@ -54,7 +54,7 @@ class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
class MemInterface(AbstractMemory):
type = 'MemInterface'
abstract = True
cxx_header = "mem/dram_ctrl.hh"
cxx_header = "mem/mem_interface.hh"
# Allow the interface to set required controller buffer sizes
# each entry corresponds to a burst for the specific memory channel

2
src/mem/NVMInterface.py
View File

@@ -43,7 +43,7 @@ from m5.objects.DRAMInterface import AddrMap
# are modeled without getting into too much detail of the media itself.
class NVMInterface(MemInterface):
type = 'NVMInterface'
cxx_header = "mem/dram_ctrl.hh"
cxx_header = "mem/mem_interface.hh"
# NVM DIMM could have write buffer to offload writes
# define buffer depth, which will limit the number of pending writes

6
src/mem/SConscript
View File

@@ -46,7 +46,7 @@ Source('comm_monitor.cc')
SimObject('AbstractMemory.py')
SimObject('AddrMapper.py')
SimObject('Bridge.py')
SimObject('DRAMCtrl.py')
SimObject('MemCtrl.py')
SimObject('MemInterface.py')
SimObject('DRAMInterface.py')
SimObject('NVMInterface.py')
@@ -64,9 +64,10 @@ Source('addr_mapper.cc')
Source('bridge.cc')
Source('coherent_xbar.cc')
Source('drampower.cc')
Source('dram_ctrl.cc')
Source('external_master.cc')
Source('external_slave.cc')
Source('mem_ctrl.cc')
Source('mem_interface.cc')
Source('noncoherent_xbar.cc')
Source('packet.cc')
Source('port.cc')
@@ -120,6 +121,7 @@ DebugFlag('NVM')
DebugFlag('ExternalPort')
DebugFlag('HtmMem', 'Hardware Transactional Memory (Mem side)')
DebugFlag('LLSC')
DebugFlag('MemCtrl')
DebugFlag('MMU')
DebugFlag('MemoryAccess')
DebugFlag('PacketQueue')

1475
src/mem/mem_ctrl.cc Normal file
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File diff suppressed because it is too large Load Diff

709
src/mem/mem_ctrl.hh Normal file
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@@ -0,0 +1,709 @@
/*
* Copyright (c) 2012-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2013 Amin Farmahini-Farahani
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file
* MemCtrl declaration
*/
#ifndef __MEM_CTRL_HH__
#define __MEM_CTRL_HH__
#include <deque>
#include <string>
#include <unordered_set>
#include <utility>
#include <vector>
#include "base/callback.hh"
#include "base/statistics.hh"
#include "enums/MemSched.hh"
#include "mem/qos/mem_ctrl.hh"
#include "mem/qport.hh"
#include "params/MemCtrl.hh"
#include "sim/eventq.hh"
class DRAMInterface;
class NVMInterface;
/**
* A burst helper helps organize and manage a packet that is larger than
* the memory burst size. A system packet that is larger than the burst size
* is split into multiple packets and all those packets point to
* a single burst helper such that we know when the whole packet is served.
*/
class BurstHelper
{
public:
/** Number of bursts requred for a system packet **/
const unsigned int burstCount;
/** Number of bursts serviced so far for a system packet **/
unsigned int burstsServiced;
BurstHelper(unsigned int _burstCount)
: burstCount(_burstCount), burstsServiced(0)
{ }
};
/**
* A memory packet stores packets along with the timestamp of when
* the packet entered the queue, and also the decoded address.
*/
class MemPacket
{
public:
/** When did request enter the controller */
const Tick entryTime;
/** When will request leave the controller */
Tick readyTime;
/** This comes from the outside world */
const PacketPtr pkt;
/** MasterID associated with the packet */
const MasterID _masterId;
const bool read;
/** Does this packet access DRAM?*/
const bool dram;
/** Will be populated by address decoder */
const uint8_t rank;
const uint8_t bank;
const uint32_t row;
/**
* Bank id is calculated considering banks in all the ranks
* eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
* bankId = 8 --> rank1, bank0
*/
const uint16_t bankId;
/**
* The starting address of the packet.
* This address could be unaligned to burst size boundaries. The
* reason is to keep the address offset so we can accurately check
* incoming read packets with packets in the write queue.
*/
Addr addr;
/**
* The size of this dram packet in bytes
* It is always equal or smaller than the burst size
*/
unsigned int size;
/**
* A pointer to the BurstHelper if this MemPacket is a split packet
* If not a split packet (common case), this is set to NULL
*/
BurstHelper* burstHelper;
/**
* QoS value of the encapsulated packet read at queuing time
*/
uint8_t _qosValue;
/**
* Set the packet QoS value
* (interface compatibility with Packet)
*/
inline void qosValue(const uint8_t qv) { _qosValue = qv; }
/**
* Get the packet QoS value
* (interface compatibility with Packet)
*/
inline uint8_t qosValue() const { return _qosValue; }
/**
* Get the packet MasterID
* (interface compatibility with Packet)
*/
inline MasterID masterId() const { return _masterId; }
/**
* Get the packet size
* (interface compatibility with Packet)
*/
inline unsigned int getSize() const { return size; }
/**
* Get the packet address
* (interface compatibility with Packet)
*/
inline Addr getAddr() const { return addr; }
/**
* Return true if its a read packet
* (interface compatibility with Packet)
*/
inline bool isRead() const { return read; }
/**
* Return true if its a write packet
* (interface compatibility with Packet)
*/
inline bool isWrite() const { return !read; }
/**
* Return true if its a DRAM access
*/
inline bool isDram() const { return dram; }
MemPacket(PacketPtr _pkt, bool is_read, bool is_dram, uint8_t _rank,
uint8_t _bank, uint32_t _row, uint16_t bank_id, Addr _addr,
unsigned int _size)
: entryTime(curTick()), readyTime(curTick()), pkt(_pkt),
_masterId(pkt->masterId()),
read(is_read), dram(is_dram), rank(_rank), bank(_bank), row(_row),
bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
_qosValue(_pkt->qosValue())
{ }
};
// The memory packets are store in a multiple dequeue structure,
// based on their QoS priority
typedef std::deque<MemPacket*> MemPacketQueue;
/**
* The memory controller is a single-channel memory controller capturing
* the most important timing constraints associated with a
* contemporary controller. For multi-channel memory systems, the controller
* is combined with a crossbar model, with the channel address
* interleaving taking part in the crossbar.
*
* As a basic design principle, this controller
* model is not cycle callable, but instead uses events to: 1) decide
* when new decisions can be made, 2) when resources become available,
* 3) when things are to be considered done, and 4) when to send
* things back. The controller interfaces to media specific interfaces
* to enable flexible topoloties.
* Through these simple principles, the model delivers
* high performance, and lots of flexibility, allowing users to
* evaluate the system impact of a wide range of memory technologies.
*
* For more details, please see Hansson et al, "Simulating DRAM
* controllers for future system architecture exploration",
* Proc. ISPASS, 2014. If you use this model as part of your research
* please cite the paper.
*
*/
class MemCtrl : public QoS::MemCtrl
{
private:
// For now, make use of a queued slave port to avoid dealing with
// flow control for the responses being sent back
class MemoryPort : public QueuedSlavePort
{
RespPacketQueue queue;
MemCtrl& ctrl;
public:
MemoryPort(const std::string& name, MemCtrl& _ctrl);
protected:
Tick recvAtomic(PacketPtr pkt);
void recvFunctional(PacketPtr pkt);
bool recvTimingReq(PacketPtr);
virtual AddrRangeList getAddrRanges() const;
};
/**
* Our incoming port, for a multi-ported controller add a crossbar
* in front of it
*/
MemoryPort port;
/**
* Remember if the memory system is in timing mode
*/
bool isTimingMode;
/**
* Remember if we have to retry a request when available.
*/
bool retryRdReq;
bool retryWrReq;
/**
* Bunch of things requires to setup "events" in gem5
* When event "respondEvent" occurs for example, the method
* processRespondEvent is called; no parameters are allowed
* in these methods
*/
void processNextReqEvent();
EventFunctionWrapper nextReqEvent;
void processRespondEvent();
EventFunctionWrapper respondEvent;
/**
* Check if the read queue has room for more entries
*
* @param pkt_count The number of entries needed in the read queue
* @return true if read queue is full, false otherwise
*/
bool readQueueFull(unsigned int pkt_count) const;
/**
* Check if the write queue has room for more entries
*
* @param pkt_count The number of entries needed in the write queue
* @return true if write queue is full, false otherwise
*/
bool writeQueueFull(unsigned int pkt_count) const;
/**
* When a new read comes in, first check if the write q has a
* pending request to the same address.\ If not, decode the
* address to populate rank/bank/row, create one or mutliple
* "mem_pkt", and push them to the back of the read queue.\
* If this is the only
* read request in the system, schedule an event to start
* servicing it.
*
* @param pkt The request packet from the outside world
* @param pkt_count The number of memory bursts the pkt
* @param is_dram Does this packet access DRAM?
* translate to. If pkt size is larger then one full burst,
* then pkt_count is greater than one.
*/
void addToReadQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram);
/**
* Decode the incoming pkt, create a mem_pkt and push to the
* back of the write queue. \If the write q length is more than
* the threshold specified by the user, ie the queue is beginning
* to get full, stop reads, and start draining writes.
*
* @param pkt The request packet from the outside world
* @param pkt_count The number of memory bursts the pkt
* @param is_dram Does this packet access DRAM?
* translate to. If pkt size is larger then one full burst,
* then pkt_count is greater than one.
*/
void addToWriteQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram);
/**
* Actually do the burst based on media specific access function.
* Update bus statistics when complete.
*
* @param mem_pkt The memory packet created from the outside world pkt
*/
void doBurstAccess(MemPacket* mem_pkt);
/**
* When a packet reaches its "readyTime" in the response Q,
* use the "access()" method in AbstractMemory to actually
* create the response packet, and send it back to the outside
* world requestor.
*
* @param pkt The packet from the outside world
* @param static_latency Static latency to add before sending the packet
*/
void accessAndRespond(PacketPtr pkt, Tick static_latency);
/**
* Determine if there is a packet that can issue.
*
* @param pkt The packet to evaluate
*/
bool packetReady(MemPacket* pkt);
/**
* Calculate the minimum delay used when scheduling a read-to-write
* transision.
* @param return minimum delay
*/
Tick minReadToWriteDataGap();
/**
* Calculate the minimum delay used when scheduling a write-to-read
* transision.
* @param return minimum delay
*/
Tick minWriteToReadDataGap();
/**
* The memory schduler/arbiter - picks which request needs to
* go next, based on the specified policy such as FCFS or FR-FCFS
* and moves it to the head of the queue.
* Prioritizes accesses to the same rank as previous burst unless
* controller is switching command type.
*
* @param queue Queued requests to consider
* @param extra_col_delay Any extra delay due to a read/write switch
* @return an iterator to the selected packet, else queue.end()
*/
MemPacketQueue::iterator chooseNext(MemPacketQueue& queue,
Tick extra_col_delay);
/**
* For FR-FCFS policy reorder the read/write queue depending on row buffer
* hits and earliest bursts available in memory
*
* @param queue Queued requests to consider
* @param extra_col_delay Any extra delay due to a read/write switch
* @return an iterator to the selected packet, else queue.end()
*/
MemPacketQueue::iterator chooseNextFRFCFS(MemPacketQueue& queue,
Tick extra_col_delay);
/**
* Calculate burst window aligned tick
*
* @param cmd_tick Initial tick of command
* @return burst window aligned tick
*/
Tick getBurstWindow(Tick cmd_tick);
/**
* Used for debugging to observe the contents of the queues.
*/
void printQs() const;
/**
* Burst-align an address.
*
* @param addr The potentially unaligned address
* @param is_dram Does this packet access DRAM?
*
* @return An address aligned to a memory burst
*/
Addr burstAlign(Addr addr, bool is_dram) const;
/**
* The controller's main read and write queues,
* with support for QoS reordering
*/
std::vector<MemPacketQueue> readQueue;
std::vector<MemPacketQueue> writeQueue;
/**
* To avoid iterating over the write queue to check for
* overlapping transactions, maintain a set of burst addresses
* that are currently queued. Since we merge writes to the same
* location we never have more than one address to the same burst
* address.
*/
std::unordered_set<Addr> isInWriteQueue;
/**
* Response queue where read packets wait after we're done working
* with them, but it's not time to send the response yet. The
* responses are stored separately mostly to keep the code clean
* and help with events scheduling. For all logical purposes such
* as sizing the read queue, this and the main read queue need to
* be added together.
*/
std::deque<MemPacket*> respQueue;
/**
* Holds count of commands issued in burst window starting at
* defined Tick. This is used to ensure that the command bandwidth
* does not exceed the allowable media constraints.
*/
std::unordered_multiset<Tick> burstTicks;
/**
* Create pointer to interface of the actual dram media when connected
*/
DRAMInterface* const dram;
/**
* Create pointer to interface of the actual nvm media when connected
*/
NVMInterface* const nvm;
/**
* The following are basic design parameters of the memory
* controller, and are initialized based on parameter values.
* The rowsPerBank is determined based on the capacity, number of
* ranks and banks, the burst size, and the row buffer size.
*/
const uint32_t readBufferSize;
const uint32_t writeBufferSize;
const uint32_t writeHighThreshold;
const uint32_t writeLowThreshold;
const uint32_t minWritesPerSwitch;
uint32_t writesThisTime;
uint32_t readsThisTime;
/**
* Memory controller configuration initialized based on parameter
* values.
*/
Enums::MemSched memSchedPolicy;
/**
* Pipeline latency of the controller frontend. The frontend
* contribution is added to writes (that complete when they are in
* the write buffer) and reads that are serviced the write buffer.
*/
const Tick frontendLatency;
/**
* Pipeline latency of the backend and PHY. Along with the
* frontend contribution, this latency is added to reads serviced
* by the memory.
*/
const Tick backendLatency;
/**
* Length of a command window, used to check
* command bandwidth
*/
const Tick commandWindow;
/**
* Till when must we wait before issuing next RD/WR burst?
*/
Tick nextBurstAt;
Tick prevArrival;
/**
* The soonest you have to start thinking about the next request
* is the longest access time that can occur before
* nextBurstAt. Assuming you need to precharge, open a new row,
* and access, it is tRP + tRCD + tCL.
*/
Tick nextReqTime;
struct CtrlStats : public Stats::Group
{
CtrlStats(MemCtrl &ctrl);
void regStats() override;
MemCtrl &ctrl;
// All statistics that the model needs to capture
Stats::Scalar readReqs;
Stats::Scalar writeReqs;
Stats::Scalar readBursts;
Stats::Scalar writeBursts;
Stats::Scalar servicedByWrQ;
Stats::Scalar mergedWrBursts;
Stats::Scalar neitherReadNorWriteReqs;
// Average queue lengths
Stats::Average avgRdQLen;
Stats::Average avgWrQLen;
Stats::Scalar numRdRetry;
Stats::Scalar numWrRetry;
Stats::Vector readPktSize;
Stats::Vector writePktSize;
Stats::Vector rdQLenPdf;
Stats::Vector wrQLenPdf;
Stats::Histogram rdPerTurnAround;
Stats::Histogram wrPerTurnAround;
Stats::Scalar bytesReadWrQ;
Stats::Scalar bytesReadSys;
Stats::Scalar bytesWrittenSys;
// Average bandwidth
Stats::Formula avgRdBWSys;
Stats::Formula avgWrBWSys;
Stats::Scalar totGap;
Stats::Formula avgGap;
// per-master bytes read and written to memory
Stats::Vector masterReadBytes;
Stats::Vector masterWriteBytes;
// per-master bytes read and written to memory rate
Stats::Formula masterReadRate;
Stats::Formula masterWriteRate;
// per-master read and write serviced memory accesses
Stats::Vector masterReadAccesses;
Stats::Vector masterWriteAccesses;
// per-master read and write total memory access latency
Stats::Vector masterReadTotalLat;
Stats::Vector masterWriteTotalLat;
// per-master raed and write average memory access latency
Stats::Formula masterReadAvgLat;
Stats::Formula masterWriteAvgLat;
};
CtrlStats stats;
/**
* Upstream caches need this packet until true is returned, so
* hold it for deletion until a subsequent call
*/
std::unique_ptr<Packet> pendingDelete;
/**
* Select either the read or write queue
*
* @param is_read The current burst is a read, select read queue
* @return a reference to the appropriate queue
*/
std::vector<MemPacketQueue>& selQueue(bool is_read)
{
return (is_read ? readQueue : writeQueue);
};
/**
* Remove commands that have already issued from burstTicks
*/
void pruneBurstTick();
public:
MemCtrl(const MemCtrlParams* p);
/**
* Ensure that all interfaced have drained commands
*
* @return bool flag, set once drain complete
*/
bool allIntfDrained() const;
DrainState drain() override;
/**
* Check for command bus contention for single cycle command.
* If there is contention, shift command to next burst.
* Check verifies that the commands issued per burst is less
* than a defined max number, maxCommandsPerWindow.
* Therefore, contention per cycle is not verified and instead
* is done based on a burst window.
*
* @param cmd_tick Initial tick of command, to be verified
* @param max_cmds_per_burst Number of commands that can issue
* in a burst window
* @return tick for command issue without contention
*/
Tick verifySingleCmd(Tick cmd_tick, Tick max_cmds_per_burst);
/**
* Check for command bus contention for multi-cycle (2 currently)
* command. If there is contention, shift command(s) to next burst.
* Check verifies that the commands issued per burst is less
* than a defined max number, maxCommandsPerWindow.
* Therefore, contention per cycle is not verified and instead
* is done based on a burst window.
*
* @param cmd_tick Initial tick of command, to be verified
* @param max_multi_cmd_split Maximum delay between commands
* @param max_cmds_per_burst Number of commands that can issue
* in a burst window
* @return tick for command issue without contention
*/
Tick verifyMultiCmd(Tick cmd_tick, Tick max_cmds_per_burst,
Tick max_multi_cmd_split = 0);
/**
* Is there a respondEvent scheduled?
*
* @return true if event is scheduled
*/
bool respondEventScheduled() const { return respondEvent.scheduled(); }
/**
* Is there a read/write burst Event scheduled?
*
* @return true if event is scheduled
*/
bool requestEventScheduled() const { return nextReqEvent.scheduled(); }
/**
* restart the controller
* This can be used by interfaces to restart the
* scheduler after maintainence commands complete
*
* @param Tick to schedule next event
*/
void restartScheduler(Tick tick) { schedule(nextReqEvent, tick); }
/**
* Check the current direction of the memory channel
*
* @param next_state Check either the current or next bus state
* @return True when bus is currently in a read state
*/
bool inReadBusState(bool next_state) const;
/**
* Check the current direction of the memory channel
*
* @param next_state Check either the current or next bus state
* @return True when bus is currently in a write state
*/
bool inWriteBusState(bool next_state) const;
Port &getPort(const std::string &if_name,
PortID idx=InvalidPortID) override;
virtual void init() override;
virtual void startup() override;
virtual void drainResume() override;
protected:
Tick recvAtomic(PacketPtr pkt);
void recvFunctional(PacketPtr pkt);
bool recvTimingReq(PacketPtr pkt);
};
#endif //__MEM_CTRL_HH__

1547
src/mem/dram_ctrl.cc → src/mem/mem_interface.cc
View File

File diff suppressed because it is too large Load Diff

759
src/mem/dram_ctrl.hh → src/mem/mem_interface.hh
View File

@@ -40,11 +40,11 @@
/**
* @file
* DRAMCtrl declaration
* MemInterface declaration
*/
#ifndef __MEM_DRAM_CTRL_HH__
#define __MEM_DRAM_CTRL_HH__
#ifndef __MEM_INTERFACE_HH__
#define __MEM_INTERFACE_HH__
#include <deque>
#include <string>
@@ -54,168 +54,15 @@
#include "base/statistics.hh"
#include "enums/AddrMap.hh"
#include "enums/MemSched.hh"
#include "enums/PageManage.hh"
#include "mem/abstract_mem.hh"
#include "mem/drampower.hh"
#include "mem/qos/mem_ctrl.hh"
#include "mem/qport.hh"
#include "params/DRAMCtrl.hh"
#include "mem/mem_ctrl.hh"
#include "params/DRAMInterface.hh"
#include "params/MemInterface.hh"
#include "params/NVMInterface.hh"
#include "sim/eventq.hh"
class DRAMInterfaceParams;
class NVMInterfaceParams;
/**
* A burst helper helps organize and manage a packet that is larger than
* the DRAM burst size. A system packet that is larger than the burst size
* is split into multiple DRAM packets and all those DRAM packets point to
* a single burst helper such that we know when the whole packet is served.
*/
class BurstHelper
{
public:
/** Number of DRAM bursts requred for a system packet **/
const unsigned int burstCount;
/** Number of DRAM bursts serviced so far for a system packet **/
unsigned int burstsServiced;
BurstHelper(unsigned int _burstCount)
: burstCount(_burstCount), burstsServiced(0)
{ }
};
/**
* A DRAM packet stores packets along with the timestamp of when
* the packet entered the queue, and also the decoded address.
*/
class DRAMPacket
{
public:
/** When did request enter the controller */
const Tick entryTime;
/** When will request leave the controller */
Tick readyTime;
/** This comes from the outside world */
const PacketPtr pkt;
/** MasterID associated with the packet */
const MasterID _masterId;
const bool read;
/** Does this packet access DRAM?*/
const bool dram;
/** Will be populated by address decoder */
const uint8_t rank;
const uint8_t bank;
const uint32_t row;
/**
* Bank id is calculated considering banks in all the ranks
* eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
* bankId = 8 --> rank1, bank0
*/
const uint16_t bankId;
/**
* The starting address of the DRAM packet.
* This address could be unaligned to burst size boundaries. The
* reason is to keep the address offset so we can accurately check
* incoming read packets with packets in the write queue.
*/
Addr addr;
/**
* The size of this dram packet in bytes
* It is always equal or smaller than DRAM burst size
*/
unsigned int size;
/**
* A pointer to the BurstHelper if this DRAMPacket is a split packet
* If not a split packet (common case), this is set to NULL
*/
BurstHelper* burstHelper;
/**
* QoS value of the encapsulated packet read at queuing time
*/
uint8_t _qosValue;
/**
* Set the packet QoS value
* (interface compatibility with Packet)
*/
inline void qosValue(const uint8_t qv) { _qosValue = qv; }
/**
* Get the packet QoS value
* (interface compatibility with Packet)
*/
inline uint8_t qosValue() const { return _qosValue; }
/**
* Get the packet MasterID
* (interface compatibility with Packet)
*/
inline MasterID masterId() const { return _masterId; }
/**
* Get the packet size
* (interface compatibility with Packet)
*/
inline unsigned int getSize() const { return size; }
/**
* Get the packet address
* (interface compatibility with Packet)
*/
inline Addr getAddr() const { return addr; }
/**
* Return true if its a read packet
* (interface compatibility with Packet)
*/
inline bool isRead() const { return read; }
/**
* Return true if its a write packet
* (interface compatibility with Packet)
*/
inline bool isWrite() const { return !read; }
/**
* Return true if its a DRAM access
*/
inline bool isDram() const { return dram; }
DRAMPacket(PacketPtr _pkt, bool is_read, bool is_dram, uint8_t _rank,
uint8_t _bank, uint32_t _row, uint16_t bank_id, Addr _addr,
unsigned int _size)
: entryTime(curTick()), readyTime(curTick()), pkt(_pkt),
_masterId(pkt->masterId()),
read(is_read), dram(is_dram), rank(_rank), bank(_bank), row(_row),
bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
_qosValue(_pkt->qosValue())
{ }
};
// The DRAM packets are store in a multiple dequeue structure,
// based on their QoS priority
typedef std::deque<DRAMPacket*> DRAMPacketQueue;
/**
* General interface to memory device
* Includes functions and parameters shared across media types
@@ -259,9 +106,9 @@ class MemInterface : public AbstractMemory
};
/**
* A pointer to the parent DRAMCtrl instance
* A pointer to the parent MemCtrl instance
*/
DRAMCtrl* ctrl;
MemCtrl* ctrl;
/**
* Number of commands that can issue in the defined controller
@@ -317,13 +164,23 @@ class MemInterface : public AbstractMemory
public:
/**
* Buffer sizes for read and write queues in the controller
* These are passed to the controller on instantiation
* Defining them here allows for buffers to be resized based
* on memory type / configuration.
*/
const uint32_t readBufferSize;
const uint32_t writeBufferSize;
/** Set a pointer to the controller and initialize
* interface based on controller parameters
* @param _ctrl pointer to the parent controller
* @param command_window size of command window used to
* check command bandwidth
*/
void setCtrl(DRAMCtrl* _ctrl, unsigned int command_window);
void setCtrl(MemCtrl* _ctrl, unsigned int command_window);
/**
* Get an address in a dense range which starts from 0. The input
@@ -363,8 +220,8 @@ class MemInterface : public AbstractMemory
* @return an iterator to the selected packet, else queue.end()
* @return the tick when the packet selected will issue
*/
virtual std::pair<DRAMPacketQueue::iterator, Tick>
chooseNextFRFCFS(DRAMPacketQueue& queue, Tick min_col_at) const = 0;
virtual std::pair<MemPacketQueue::iterator, Tick>
chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const = 0;
/*
* Function to calulate unloaded latency
@@ -386,7 +243,7 @@ class MemInterface : public AbstractMemory
*
* @param Return true if RD/WR can issue
*/
virtual bool burstReady(DRAMPacket* pkt) const = 0;
virtual bool burstReady(MemPacket* pkt) const = 0;
/**
* Determine the required delay for an access to a different rank
@@ -414,13 +271,13 @@ class MemInterface : public AbstractMemory
* pkt_addr is used for the offset within the packet.
*
* @param pkt The packet from the outside world
* @param pkt_addr The starting address of the DRAM packet
* @param size The size of the DRAM packet in bytes
* @param pkt_addr The starting address of the packet
* @param size The size of the packet in bytes
* @param is_read Is the request for a read or a write to memory
* @param is_dram Is the request to a DRAM interface
* @return A DRAMPacket pointer with the decoded information
* @return A MemPacket pointer with the decoded information
*/
DRAMPacket* decodePacket(const PacketPtr pkt, Addr pkt_addr,
MemPacket* decodePacket(const PacketPtr pkt, Addr pkt_addr,
unsigned int size, bool is_read, bool is_dram);
/**
@@ -997,17 +854,6 @@ class DRAMInterface : public MemInterface
*/
std::vector<Rank*> ranks;
public:
/**
* Buffer sizes for read and write queues in the controller
* These are passed to the controller on instantiation
* Defining them here allows for buffers to be resized based
* on memory type / configuration.
*/
const uint32_t readBufferSize;
const uint32_t writeBufferSize;
/*
* @return delay between write and read commands
*/
@@ -1024,7 +870,7 @@ class DRAMInterface : public MemInterface
* @return boolean indicating burst can issue seamlessly, with no gaps
*/
std::pair<std::vector<uint32_t>, bool>
minBankPrep(const DRAMPacketQueue& queue, Tick min_col_at) const;
minBankPrep(const MemPacketQueue& queue, Tick min_col_at) const;
/*
* @return time to send a burst of data without gaps
@@ -1093,8 +939,8 @@ class DRAMInterface : public MemInterface
* @return an iterator to the selected packet, else queue.end()
* @return the tick when the packet selected will issue
*/
std::pair<DRAMPacketQueue::iterator, Tick>
chooseNextFRFCFS(DRAMPacketQueue& queue, Tick min_col_at) const override;
std::pair<MemPacketQueue::iterator, Tick>
chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const override;
/**
* Actually do the burst - figure out the latency it
@@ -1104,15 +950,15 @@ class DRAMInterface : public MemInterface
* response q from where it will eventually go back to the outside
* world.
*
* @param dram_pkt The DRAM packet created from the outside world pkt
* @param mem_pkt The packet created from the outside world pkt
* @param next_burst_at Minimum bus timing requirement from controller
* @param queue Reference to the read or write queue with the packet
* @return pair, tick when current burst is issued and
* tick when next burst can issue
*/
std::pair<Tick, Tick>
doBurstAccess(DRAMPacket* dram_pkt, Tick next_burst_at,
const std::vector<DRAMPacketQueue>& queue);
doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
const std::vector<MemPacketQueue>& queue);
/**
* Check if a burst operation can be issued to the DRAM
@@ -1122,7 +968,7 @@ class DRAMInterface : public MemInterface
* REF IDLE state
*/
bool
burstReady(DRAMPacket* pkt) const override
burstReady(MemPacket* pkt) const override
{
return ranks[pkt->rank]->inRefIdleState();
}
@@ -1309,15 +1155,6 @@ class NVMInterface : public MemInterface
// number of writes in the writeQueue for the NVM interface
uint32_t numWritesQueued;
/**
* Buffer sizes for read and write queues in the controller
* These are passed to the controller on instantiation
* Defining them here allows for buffers to be resized based
* on memory type / configuration.
*/
const uint32_t readBufferSize;
const uint32_t writeBufferSize;
/**
* Initialize the NVM interface and verify parameters
*/
@@ -1352,7 +1189,7 @@ class NVMInterface : public MemInterface
* has been updated to a non-zero value to
* account for race conditions between events
*/
bool burstReady(DRAMPacket* pkt) const override;
bool burstReady(MemPacket* pkt) const override;
/**
* This function checks if ranks are busy.
@@ -1375,8 +1212,8 @@ class NVMInterface : public MemInterface
* @return an iterator to the selected packet, else queue.end()
* @return the tick when the packet selected will issue
*/
std::pair<DRAMPacketQueue::iterator, Tick>
chooseNextFRFCFS(DRAMPacketQueue& queue, Tick min_col_at) const override;
std::pair<MemPacketQueue::iterator, Tick>
chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const override;
/**
* Add rank to rank delay to bus timing to all NVM banks in alli ranks
@@ -1391,7 +1228,7 @@ class NVMInterface : public MemInterface
/**
* Select read command to issue asynchronously
*/
void chooseRead(DRAMPacketQueue& queue);
void chooseRead(MemPacketQueue& queue);
/*
* Function to calulate unloaded access latency
@@ -1425,531 +1262,9 @@ class NVMInterface : public MemInterface
* tick when next burst can issue
*/
std::pair<Tick, Tick>
doBurstAccess(DRAMPacket* pkt, Tick next_burst_at);
doBurstAccess(MemPacket* pkt, Tick next_burst_at);
NVMInterface(const NVMInterfaceParams* _p);
};
/**
* The DRAM controller is a single-channel memory controller capturing
* the most important timing constraints associated with a
* contemporary DRAM. For multi-channel memory systems, the controller
* is combined with a crossbar model, with the channel address
* interleaving taking part in the crossbar.
*
* As a basic design principle, this controller
* model is not cycle callable, but instead uses events to: 1) decide
* when new decisions can be made, 2) when resources become available,
* 3) when things are to be considered done, and 4) when to send
* things back. Through these simple principles, the model delivers
* high performance, and lots of flexibility, allowing users to
* evaluate the system impact of a wide range of memory technologies,
* such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
*
* For more details, please see Hansson et al, "Simulating DRAM
* controllers for future system architecture exploration",
* Proc. ISPASS, 2014. If you use this model as part of your research
* please cite the paper.
*
* The low-power functionality implements a staggered powerdown
* similar to that described in "Optimized Active and Power-Down Mode
* Refresh Control in 3D-DRAMs" by Jung et al, VLSI-SoC, 2014.
*/
class DRAMCtrl : public QoS::MemCtrl
{
private:
// For now, make use of a queued slave port to avoid dealing with
// flow control for the responses being sent back
class MemoryPort : public QueuedSlavePort
{
RespPacketQueue queue;
DRAMCtrl& ctrl;
public:
MemoryPort(const std::string& name, DRAMCtrl& _ctrl);
protected:
Tick recvAtomic(PacketPtr pkt);
void recvFunctional(PacketPtr pkt);
bool recvTimingReq(PacketPtr);
virtual AddrRangeList getAddrRanges() const;
};
/**
* Our incoming port, for a multi-ported controller add a crossbar
* in front of it
*/
MemoryPort port;
/**
* Remember if the memory system is in timing mode
*/
bool isTimingMode;
/**
* Remember if we have to retry a request when available.
*/
bool retryRdReq;
bool retryWrReq;
/**
* Bunch of things requires to setup "events" in gem5
* When event "respondEvent" occurs for example, the method
* processRespondEvent is called; no parameters are allowed
* in these methods
*/
void processNextReqEvent();
EventFunctionWrapper nextReqEvent;
void processRespondEvent();
EventFunctionWrapper respondEvent;
/**
* Check if the read queue has room for more entries
*
* @param pkt_count The number of entries needed in the read queue
* @return true if read queue is full, false otherwise
*/
bool readQueueFull(unsigned int pkt_count) const;
/**
* Check if the write queue has room for more entries
*
* @param pkt_count The number of entries needed in the write queue
* @return true if write queue is full, false otherwise
*/
bool writeQueueFull(unsigned int pkt_count) const;
/**
* When a new read comes in, first check if the write q has a
* pending request to the same address.\ If not, decode the
* address to populate rank/bank/row, create one or mutliple
* "dram_pkt", and push them to the back of the read queue.\
* If this is the only
* read request in the system, schedule an event to start
* servicing it.
*
* @param pkt The request packet from the outside world
* @param pkt_count The number of DRAM bursts the pkt
* @param is_dram Does this packet access DRAM?
* translate to. If pkt size is larger then one full burst,
* then pkt_count is greater than one.
*/
void addToReadQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram);
/**
* Decode the incoming pkt, create a dram_pkt and push to the
* back of the write queue. \If the write q length is more than
* the threshold specified by the user, ie the queue is beginning
* to get full, stop reads, and start draining writes.
*
* @param pkt The request packet from the outside world
* @param pkt_count The number of DRAM bursts the pkt
* @param is_dram Does this packet access DRAM?
* translate to. If pkt size is larger then one full burst,
* then pkt_count is greater than one.
*/
void addToWriteQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram);
/**
* Actually do the burst based on media specific access function.
* Update bus statistics when complete.
*
* @param pkt The DRAM packet created from the outside world pkt
*/
void doBurstAccess(DRAMPacket* dram_pkt);
/**
* When a packet reaches its "readyTime" in the response Q,
* use the "access()" method in AbstractMemory to actually
* create the response packet, and send it back to the outside
* world requestor.
*
* @param pkt The packet from the outside world
* @param static_latency Static latency to add before sending the packet
*/
void accessAndRespond(PacketPtr pkt, Tick static_latency);
/**
* Determine if there is a packet that can issue.
*
* @param pkt The packet to evaluate
*/
bool
packetReady(DRAMPacket* pkt)
{
return (pkt->isDram() ?
dram->burstReady(pkt) : nvm->burstReady(pkt));
}
/**
* Calculate the minimum delay used when scheduling a read-to-write
* transision.
* @param return minimum delay
*/
Tick
minReadToWriteDataGap()
{
Tick dram_min = dram ? dram->minReadToWriteDataGap() : MaxTick;
Tick nvm_min = nvm ? nvm->minReadToWriteDataGap() : MaxTick;
return std::min(dram_min, nvm_min);
}
/**
* Calculate the minimum delay used when scheduling a write-to-read
* transision.
* @param return minimum delay
*/
Tick
minWriteToReadDataGap()
{
Tick dram_min = dram ? dram->minWriteToReadDataGap() : MaxTick;
Tick nvm_min = nvm ? nvm->minWriteToReadDataGap() : MaxTick;
return std::min(dram_min, nvm_min);
}
/**
* The memory schduler/arbiter - picks which request needs to
* go next, based on the specified policy such as FCFS or FR-FCFS
* and moves it to the head of the queue.
* Prioritizes accesses to the same rank as previous burst unless
* controller is switching command type.
*
* @param queue Queued requests to consider
* @param extra_col_delay Any extra delay due to a read/write switch
* @return an iterator to the selected packet, else queue.end()
*/
DRAMPacketQueue::iterator chooseNext(DRAMPacketQueue& queue,
Tick extra_col_delay);
/**
* For FR-FCFS policy reorder the read/write queue depending on row buffer
* hits and earliest bursts available in DRAM
*
* @param queue Queued requests to consider
* @param extra_col_delay Any extra delay due to a read/write switch
* @return an iterator to the selected packet, else queue.end()
*/
DRAMPacketQueue::iterator chooseNextFRFCFS(DRAMPacketQueue& queue,
Tick extra_col_delay);
/**
* Calculate burst window aligned tick
*
* @param cmd_tick Initial tick of command
* @return burst window aligned tick
*/
Tick getBurstWindow(Tick cmd_tick);
/**
* Used for debugging to observe the contents of the queues.
*/
void printQs() const;
/**
* Burst-align an address.
*
* @param addr The potentially unaligned address
* @param is_dram Does this packet access DRAM?
*
* @return An address aligned to a memory burst
*/
Addr
burstAlign(Addr addr, bool is_dram) const
{
if (is_dram)
return (addr & ~(Addr(dram->bytesPerBurst() - 1)));
else
return (addr & ~(Addr(nvm->bytesPerBurst() - 1)));
}
/**
* The controller's main read and write queues, with support for QoS reordering
*/
std::vector<DRAMPacketQueue> readQueue;
std::vector<DRAMPacketQueue> writeQueue;
/**
* To avoid iterating over the write queue to check for
* overlapping transactions, maintain a set of burst addresses
* that are currently queued. Since we merge writes to the same
* location we never have more than one address to the same burst
* address.
*/
std::unordered_set<Addr> isInWriteQueue;
/**
* Response queue where read packets wait after we're done working
* with them, but it's not time to send the response yet. The
* responses are stored separately mostly to keep the code clean
* and help with events scheduling. For all logical purposes such
* as sizing the read queue, this and the main read queue need to
* be added together.
*/
std::deque<DRAMPacket*> respQueue;
/**
* Holds count of commands issued in burst window starting at
* defined Tick. This is used to ensure that the command bandwidth
* does not exceed the allowable media constraints.
*/
std::unordered_multiset<Tick> burstTicks;
/**
* Create pointer to interface of the actual dram media when connected
*/
DRAMInterface* const dram;
/**
* Create pointer to interface of the actual nvm media when connected
*/
NVMInterface* const nvm;
/**
* The following are basic design parameters of the memory
* controller, and are initialized based on parameter values.
* The rowsPerBank is determined based on the capacity, number of
* ranks and banks, the burst size, and the row buffer size.
*/
const uint32_t readBufferSize;
const uint32_t writeBufferSize;
const uint32_t writeHighThreshold;
const uint32_t writeLowThreshold;
const uint32_t minWritesPerSwitch;
uint32_t writesThisTime;
uint32_t readsThisTime;
/**
* Memory controller configuration initialized based on parameter
* values.
*/
Enums::MemSched memSchedPolicy;
/**
* Pipeline latency of the controller frontend. The frontend
* contribution is added to writes (that complete when they are in
* the write buffer) and reads that are serviced the write buffer.
*/
const Tick frontendLatency;
/**
* Pipeline latency of the backend and PHY. Along with the
* frontend contribution, this latency is added to reads serviced
* by the DRAM.
*/
const Tick backendLatency;
/**
* Length of a command window, used to check
* command bandwidth
*/
const Tick commandWindow;
/**
* Till when must we wait before issuing next RD/WR burst?
*/
Tick nextBurstAt;
Tick prevArrival;
/**
* The soonest you have to start thinking about the next request
* is the longest access time that can occur before
* nextBurstAt. Assuming you need to precharge, open a new row,
* and access, it is tRP + tRCD + tCL.
*/
Tick nextReqTime;
struct CtrlStats : public Stats::Group
{
CtrlStats(DRAMCtrl &ctrl);
void regStats() override;
DRAMCtrl &ctrl;
// All statistics that the model needs to capture
Stats::Scalar readReqs;
Stats::Scalar writeReqs;
Stats::Scalar readBursts;
Stats::Scalar writeBursts;
Stats::Scalar servicedByWrQ;
Stats::Scalar mergedWrBursts;
Stats::Scalar neitherReadNorWriteReqs;
// Average queue lengths
Stats::Average avgRdQLen;
Stats::Average avgWrQLen;
Stats::Scalar numRdRetry;
Stats::Scalar numWrRetry;
Stats::Vector readPktSize;
Stats::Vector writePktSize;
Stats::Vector rdQLenPdf;
Stats::Vector wrQLenPdf;
Stats::Histogram rdPerTurnAround;
Stats::Histogram wrPerTurnAround;
Stats::Scalar bytesReadWrQ;
Stats::Scalar bytesReadSys;
Stats::Scalar bytesWrittenSys;
// Average bandwidth
Stats::Formula avgRdBWSys;
Stats::Formula avgWrBWSys;
Stats::Scalar totGap;
Stats::Formula avgGap;
// per-master bytes read and written to memory
Stats::Vector masterReadBytes;
Stats::Vector masterWriteBytes;
// per-master bytes read and written to memory rate
Stats::Formula masterReadRate;
Stats::Formula masterWriteRate;
// per-master read and write serviced memory accesses
Stats::Vector masterReadAccesses;
Stats::Vector masterWriteAccesses;
// per-master read and write total memory access latency
Stats::Vector masterReadTotalLat;
Stats::Vector masterWriteTotalLat;
// per-master raed and write average memory access latency
Stats::Formula masterReadAvgLat;
Stats::Formula masterWriteAvgLat;
};
CtrlStats stats;
/**
* Upstream caches need this packet until true is returned, so
* hold it for deletion until a subsequent call
*/
std::unique_ptr<Packet> pendingDelete;
/**
* Select either the read or write queue
*
* @param is_read The current burst is a read, select read queue
* @return a reference to the appropriate queue
*/
std::vector<DRAMPacketQueue>&
selQueue(bool is_read)
{
return (is_read ? readQueue : writeQueue);
};
/**
* Remove commands that have already issued from burstTicks
*/
void pruneBurstTick();
public:
DRAMCtrl(const DRAMCtrlParams* p);
/**
* Ensure that all interfaced have drained commands
*
* @return bool flag, set once drain complete
*/
bool allIntfDrained() const;
DrainState drain() override;
/**
* Check for command bus contention for single cycle command.
* If there is contention, shift command to next burst.
* Check verifies that the commands issued per burst is less
* than a defined max number, maxCommandsPerWindow.
* Therefore, contention per cycle is not verified and instead
* is done based on a burst window.
*
* @param cmd_tick Initial tick of command, to be verified
* @param max_cmds_per_burst Number of commands that can issue
* in a burst window
* @return tick for command issue without contention
*/
Tick verifySingleCmd(Tick cmd_tick, Tick max_cmds_per_burst);
/**
* Check for command bus contention for multi-cycle (2 currently)
* command. If there is contention, shift command(s) to next burst.
* Check verifies that the commands issued per burst is less
* than a defined max number, maxCommandsPerWindow.
* Therefore, contention per cycle is not verified and instead
* is done based on a burst window.
*
* @param cmd_tick Initial tick of command, to be verified
* @param max_multi_cmd_split Maximum delay between commands
* @param max_cmds_per_burst Number of commands that can issue
* in a burst window
* @return tick for command issue without contention
*/
Tick verifyMultiCmd(Tick cmd_tick, Tick max_cmds_per_burst,
Tick max_multi_cmd_split = 0);
/**
* Is there a respondEvent scheduled?
*
* @return true if event is scheduled
*/
bool respondEventScheduled() const { return respondEvent.scheduled(); }
/**
* Is there a read/write burst Event scheduled?
*
* @return true if event is scheduled
*/
bool requestEventScheduled() const { return nextReqEvent.scheduled(); }
/**
* restart the controller
* This can be used by interfaces to restart the
* scheduler after maintainence commands complete
*
* @param Tick to schedule next event
*/
void restartScheduler(Tick tick) { schedule(nextReqEvent, tick); }
/**
* Check the current direction of the memory channel
*
* @param next_state Check either the current or next bus state
* @return True when bus is currently in a read state
*/
bool inReadBusState(bool next_state) const;
/**
* Check the current direction of the memory channel
*
* @param next_state Check either the current or next bus state
* @return True when bus is currently in a write state
*/
bool inWriteBusState(bool next_state) const;
Port &getPort(const std::string &if_name,
PortID idx=InvalidPortID) override;
virtual void init() override;
virtual void startup() override;
virtual void drainResume() override;
protected:
Tick recvAtomic(PacketPtr pkt);
void recvFunctional(PacketPtr pkt);
bool recvTimingReq(PacketPtr pkt);
};
#endif //__MEM_DRAM_CTRL_HH__
#endif //__MEM_INTERFACE_HH__

4
tests/gem5/configs/base_config.py
View File

@@ -221,7 +221,7 @@ class BaseSESystem(BaseSystem):
def create_system(self):
if issubclass(self.mem_class, m5.objects.DRAMInterface):
mem_ctrl = DRAMCtrl()
mem_ctrl = MemCtrl()
mem_ctrl.dram = self.mem_class()
else:
mem_ctrl = self.mem_class()
@@ -280,7 +280,7 @@ class BaseFSSystem(BaseSystem):
if issubclass(self.mem_class, m5.objects.DRAMInterface):
mem_ctrls = []
for r in system.mem_ranges:
mem_ctrl = DRAMCtrl()
mem_ctrl = MemCtrl()
mem_ctrl.dram = self.mem_class(range = r)
mem_ctrls.append(mem_ctrl)
system.physmem = mem_ctrls