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mem: Stop "using namespace std"

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Change-Id: I26fd73f1b7d38e1e00eece12459f7a96227900ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39555
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
This commit is contained in:
Gabe Black
2021-01-21 02:43:46 -08:00
parent e24ae581ec
commit 3e628206b0
35 changed files with 247 additions and 304 deletions
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6
src/mem/abstract_mem.cc
View File

@@ -51,8 +51,6 @@
#include "mem/packet_access.hh"
#include "sim/system.hh"
using namespace std;
AbstractMemory::AbstractMemory(const Params &p) :
ClockedObject(p), range(p.range), pmemAddr(NULL),
backdoor(params().range, nullptr,
@@ -254,7 +252,7 @@ AbstractMemory::trackLoadLocked(PacketPtr pkt)
// first we check if we already have a locked addr for this
// xc. Since each xc only gets one, we just update the
// existing record with the new address.
list<LockedAddr>::iterator i;
std::list<LockedAddr>::iterator i;
for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
if (i->matchesContext(req)) {
@@ -294,7 +292,7 @@ AbstractMemory::checkLockedAddrList(PacketPtr pkt)
// Only remove records when we succeed in finding a record for (xc, addr);
// then, remove all records with this address. Failed store-conditionals do
// not blow unrelated reservations.
list<LockedAddr>::iterator i = lockedAddrList.begin();
std::list<LockedAddr>::iterator i = lockedAddrList.begin();
if (isLLSC) {
while (i != lockedAddrList.end()) {

4
src/mem/cache/base.cc vendored
View File

@@ -62,8 +62,6 @@
#include "params/WriteAllocator.hh"
#include "sim/core.hh"
using namespace std;
BaseCache::CacheResponsePort::CacheResponsePort(const std::string &_name,
BaseCache *_cache,
const std::string &_label)
@@ -908,7 +906,7 @@ BaseCache::updateCompressionData(CacheBlk *&blk, const uint64_t* data,
bool is_data_contraction = false;
const CompressionBlk::OverwriteType overwrite_type =
compression_blk->checkExpansionContraction(compression_size);
string op_name = "";
std::string op_name = "";
if (overwrite_type == CompressionBlk::DATA_EXPANSION) {
op_name = "expansion";
is_data_expansion = true;

4
src/mem/mem_ctrl.cc
View File

@@ -49,8 +49,6 @@
#include "mem/mem_interface.hh"
#include "sim/system.hh"
using namespace std;
MemCtrl::MemCtrl(const MemCtrlParams &p) :
QoS::MemCtrl(p),
port(name() + ".port", *this), isTimingMode(false),
@@ -1366,7 +1364,7 @@ MemCtrl::recvFunctional(PacketPtr pkt)
}
Port &
MemCtrl::getPort(const string &if_name, PortID idx)
MemCtrl::getPort(const std::string &if_name, PortID idx)
{
if (if_name != "port") {
return QoS::MemCtrl::getPort(if_name, idx);

27
src/mem/mem_interface.cc
View File

@@ -49,7 +49,6 @@
#include "debug/NVM.hh"
#include "sim/system.hh"
using namespace std;
using namespace Data;
MemInterface::MemInterface(const MemInterfaceParams &_p)
@@ -166,10 +165,10 @@ MemInterface::decodePacket(const PacketPtr pkt, Addr pkt_addr,
pkt_addr, size);
}
pair<MemPacketQueue::iterator, Tick>
std::pair<MemPacketQueue::iterator, Tick>
DRAMInterface::chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const
{
vector<uint32_t> earliest_banks(ranksPerChannel, 0);
std::vector<uint32_t> earliest_banks(ranksPerChannel, 0);
// Has minBankPrep been called to populate earliest_banks?
bool filled_earliest_banks = false;
@@ -278,7 +277,7 @@ DRAMInterface::chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const
DPRINTF(DRAM, "%s no available DRAM ranks found\n", __func__);
}
return make_pair(selected_pkt_it, selected_col_at);
return std::make_pair(selected_pkt_it, selected_col_at);
}
void
@@ -453,7 +452,7 @@ DRAMInterface::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_tick,
}
}
pair<Tick, Tick>
std::pair<Tick, Tick>
DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
const std::vector<MemPacketQueue>& queue)
{
@@ -711,7 +710,7 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
}
// Update bus state to reflect when previous command was issued
return make_pair(cmd_at, cmd_at + burst_gap);
return std::make_pair(cmd_at, cmd_at + burst_gap);
}
void
@@ -1034,12 +1033,12 @@ DRAMInterface::suspend()
}
}
pair<vector<uint32_t>, bool>
std::pair<std::vector<uint32_t>, bool>
DRAMInterface::minBankPrep(const MemPacketQueue& queue,
Tick min_col_at) const
{
Tick min_act_at = MaxTick;
vector<uint32_t> bank_mask(ranksPerChannel, 0);
std::vector<uint32_t> bank_mask(ranksPerChannel, 0);
// latest Tick for which ACT can occur without incurring additoinal
// delay on the data bus
@@ -1054,7 +1053,7 @@ DRAMInterface::minBankPrep(const MemPacketQueue& queue,
// determine if we have queued transactions targetting the
// bank in question
vector<bool> got_waiting(ranksPerChannel * banksPerRank, false);
std::vector<bool> got_waiting(ranksPerChannel * banksPerRank, false);
for (const auto& p : queue) {
if (p->isDram() && ranks[p->rank]->inRefIdleState())
got_waiting[p->bankId] = true;
@@ -1116,7 +1115,7 @@ DRAMInterface::minBankPrep(const MemPacketQueue& queue,
}
}
return make_pair(bank_mask, hidden_bank_prep);
return std::make_pair(bank_mask, hidden_bank_prep);
}
DRAMInterface::Rank::Rank(const DRAMInterfaceParams &_p,
@@ -2058,7 +2057,7 @@ void NVMInterface::setupRank(const uint8_t rank, const bool is_read)
}
}
pair<MemPacketQueue::iterator, Tick>
std::pair<MemPacketQueue::iterator, Tick>
NVMInterface::chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const
{
// remember if we found a hit, but one that cannit issue seamlessly
@@ -2111,7 +2110,7 @@ NVMInterface::chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const
DPRINTF(NVM, "%s no available NVM ranks found\n", __func__);
}
return make_pair(selected_pkt_it, selected_col_at);
return std::make_pair(selected_pkt_it, selected_col_at);
}
void
@@ -2263,7 +2262,7 @@ NVMInterface::burstReady(MemPacket* pkt) const {
return (read_rdy || write_rdy);
}
pair<Tick, Tick>
std::pair<Tick, Tick>
NVMInterface::doBurstAccess(MemPacket* pkt, Tick next_burst_at)
{
DPRINTF(NVM, "NVM Timing access to addr %lld, rank/bank/row %d %d %d\n",
@@ -2405,7 +2404,7 @@ NVMInterface::doBurstAccess(MemPacket* pkt, Tick next_burst_at)
stats.perBankWrBursts[pkt->bankId]++;
}
return make_pair(cmd_at, cmd_at + tBURST);
return std::make_pair(cmd_at, cmd_at + tBURST);
}
void

42
src/mem/physical.cc
View File

@@ -68,10 +68,8 @@
#endif
#endif
using namespace std;
PhysicalMemory::PhysicalMemory(const string& _name,
const vector<AbstractMemory*>& _memories,
PhysicalMemory::PhysicalMemory(const std::string& _name,
const std::vector<AbstractMemory*>& _memories,
bool mmap_using_noreserve,
const std::string& shared_backstore) :
_name(_name), size(0), mmapUsingNoReserve(mmap_using_noreserve),
@@ -111,7 +109,7 @@ PhysicalMemory::PhysicalMemory(const string& _name,
// simply do it independently, also note that this kind of
// memories are allowed to overlap in the logic address
// map
vector<AbstractMemory*> unmapped_mems{m};
std::vector<AbstractMemory*> unmapped_mems{m};
createBackingStore(m->getAddrRange(), unmapped_mems,
m->isConfReported(), m->isInAddrMap(),
m->isKvmMap());
@@ -121,8 +119,8 @@ PhysicalMemory::PhysicalMemory(const string& _name,
// iterate over the increasing addresses and chunks of contiguous
// space to be mapped to backing store, create it and inform the
// memories
vector<AddrRange> intlv_ranges;
vector<AbstractMemory*> curr_memories;
std::vector<AddrRange> intlv_ranges;
std::vector<AbstractMemory*> curr_memories;
for (const auto& r : addrMap) {
// simply skip past all memories that are null and hence do
// not need any backing store
@@ -154,7 +152,7 @@ PhysicalMemory::PhysicalMemory(const string& _name,
intlv_ranges.push_back(r.first);
curr_memories.push_back(r.second);
} else {
vector<AbstractMemory*> single_memory{r.second};
std::vector<AbstractMemory*> single_memory{r.second};
createBackingStore(r.first, single_memory,
r.second->isConfReported(),
r.second->isInAddrMap(),
@@ -183,10 +181,9 @@ PhysicalMemory::PhysicalMemory(const string& _name,
}
void
PhysicalMemory::createBackingStore(AddrRange range,
const vector<AbstractMemory*>& _memories,
bool conf_table_reported,
bool in_addr_map, bool kvm_map)
PhysicalMemory::createBackingStore(
AddrRange range, const std::vector<AbstractMemory*>& _memories,
bool conf_table_reported, bool in_addr_map, bool kvm_map)
{
panic_if(range.interleaved(),
"Cannot create backing store for interleaved range %s\n",
@@ -261,7 +258,7 @@ PhysicalMemory::getConfAddrRanges() const
// this could be done once in the constructor, but since it is unlikely to
// be called more than once the iteration should not be a problem
AddrRangeList ranges;
vector<AddrRange> intlv_ranges;
std::vector<AddrRange> intlv_ranges;
for (const auto& r : addrMap) {
if (r.second->isConfReported()) {
// if the range is interleaved then save it for now
@@ -313,11 +310,11 @@ void
PhysicalMemory::serialize(CheckpointOut &cp) const
{
// serialize all the locked addresses and their context ids
vector<Addr> lal_addr;
vector<ContextID> lal_cid;
std::vector<Addr> lal_addr;
std::vector<ContextID> lal_cid;
for (auto& m : memories) {
const list<LockedAddr>& locked_addrs = m->getLockedAddrList();
const std::list<LockedAddr>& locked_addrs = m->getLockedAddrList();
for (const auto& l : locked_addrs) {
lal_addr.push_back(l.addr);
lal_cid.push_back(l.contextId);
@@ -345,7 +342,8 @@ PhysicalMemory::serializeStore(CheckpointOut &cp, unsigned int store_id,
{
// we cannot use the address range for the name as the
// memories that are not part of the address map can overlap
string filename = name() + ".store" + to_string(store_id) + ".pmem";
std::string filename =
name() + ".store" + std::to_string(store_id) + ".pmem";
long range_size = range.size();
DPRINTF(Checkpoint, "Serializing physical memory %s with size %d\n",
@@ -356,7 +354,7 @@ PhysicalMemory::serializeStore(CheckpointOut &cp, unsigned int store_id,
SERIALIZE_SCALAR(range_size);
// write memory file
string filepath = CheckpointIn::dir() + "/" + filename.c_str();
std::string filepath = CheckpointIn::dir() + "/" + filename.c_str();
gzFile compressed_mem = gzopen(filepath.c_str(), "wb");
if (compressed_mem == NULL)
fatal("Can't open physical memory checkpoint file '%s'\n",
@@ -390,8 +388,8 @@ PhysicalMemory::unserialize(CheckpointIn &cp)
{
// unserialize the locked addresses and map them to the
// appropriate memory controller
vector<Addr> lal_addr;
vector<ContextID> lal_cid;
std::vector<Addr> lal_addr;
std::vector<ContextID> lal_cid;
UNSERIALIZE_CONTAINER(lal_addr);
UNSERIALIZE_CONTAINER(lal_cid);
for (size_t i = 0; i < lal_addr.size(); ++i) {
@@ -418,9 +416,9 @@ PhysicalMemory::unserializeStore(CheckpointIn &cp)
unsigned int store_id;
UNSERIALIZE_SCALAR(store_id);
string filename;
std::string filename;
UNSERIALIZE_SCALAR(filename);
string filepath = cp.getCptDir() + "/" + filename;
std::string filepath = cp.getCptDir() + "/" + filename;
// mmap memoryfile
gzFile compressed_mem = gzopen(filepath.c_str(), "rb");

2
src/mem/ruby/common/Consumer.cc
View File

@@ -40,8 +40,6 @@
#include "mem/ruby/common/Consumer.hh"
using namespace std;
Consumer::Consumer(ClockedObject *_em)
: m_wakeup_event([this]{ processCurrentEvent(); },
"Consumer Event", false),

8
src/mem/ruby/common/DataBlock.cc
View File

@@ -80,15 +80,13 @@ DataBlock::atomicPartial(const DataBlock &dblk, const WriteMask &mask)
void
DataBlock::print(std::ostream& out) const
{
using namespace std;
int size = RubySystem::getBlockSizeBytes();
out << "[ ";
for (int i = 0; i < size; i++) {
out << setw(2) << setfill('0') << hex << "0x" << (int)m_data[i] << " ";
out << setfill(' ');
out << std::setw(2) << std::setfill('0') << std::hex
<< "0x" << (int)m_data[i] << " " << std::setfill(' ');
}
out << dec << "]" << flush;
out << std::dec << "]" << std::flush;
}
const uint8_t*

16
src/mem/ruby/common/Histogram.cc
View File

@@ -33,8 +33,6 @@
#include "base/intmath.hh"
using namespace std;
Histogram::Histogram(int binsize, uint32_t bins)
{
m_binsize = binsize;
@@ -88,7 +86,7 @@ void
Histogram::add(int64_t value)
{
assert(value >= 0);
m_max = max(m_max, value);
m_max = std::max(m_max, value);
m_count++;
m_sumSamples += value;
@@ -116,7 +114,7 @@ Histogram::add(int64_t value)
assert(index < m_data.size());
m_data[index]++;
m_largest_bin = max(m_largest_bin, index);
m_largest_bin = std::max(m_largest_bin, index);
}
void
@@ -133,7 +131,7 @@ Histogram::add(Histogram& hist)
}
}
m_max = max(m_max, hist.getMax());
m_max = std::max(m_max, hist.getMax());
m_count += hist.size();
m_sumSamples += hist.getTotal();
m_sumSquaredSamples += hist.getSquaredTotal();
@@ -185,13 +183,13 @@ Histogram::getStandardDeviation() const
}
void
Histogram::print(ostream& out) const
Histogram::print(std::ostream& out) const
{
printWithMultiplier(out, 1.0);
}
void
Histogram::printPercent(ostream& out) const
Histogram::printPercent(std::ostream& out) const
{
if (m_count == 0) {
printWithMultiplier(out, 0.0);
@@ -201,7 +199,7 @@ Histogram::printPercent(ostream& out) const
}
void
Histogram::printWithMultiplier(ostream& out, double multiplier) const
Histogram::printWithMultiplier(std::ostream& out, double multiplier) const
{
if (m_binsize == -1) {
out << "[binsize: log2 ";
@@ -215,7 +213,7 @@ Histogram::printWithMultiplier(ostream& out, double multiplier) const
out << "average: NaN |";
out << "standard deviation: NaN |";
} else {
out << "average: " << setw(5) << ((double) m_sumSamples)/m_count
out << "average: " << std::setw(5) << ((double) m_sumSamples)/m_count
<< " | ";
out << "standard deviation: " << getStandardDeviation() << " |";
}

19
src/mem/ruby/network/MessageBuffer.cc
View File

@@ -49,7 +49,6 @@
#include "debug/RubyQueue.hh"
#include "mem/ruby/system/RubySystem.hh"
using namespace std;
using m5::stl_helpers::operator<<;
MessageBuffer::MessageBuffer(const Params &p)
@@ -254,7 +253,7 @@ MessageBuffer::enqueue(MsgPtr message, Tick current_time, Tick delta)
// Insert the message into the priority heap
m_prio_heap.push_back(message);
push_heap(m_prio_heap.begin(), m_prio_heap.end(), greater<MsgPtr>());
push_heap(m_prio_heap.begin(), m_prio_heap.end(), std::greater<MsgPtr>());
// Increment the number of messages statistic
m_buf_msgs++;
@@ -293,7 +292,7 @@ MessageBuffer::dequeue(Tick current_time, bool decrement_messages)
m_time_last_time_pop = current_time;
}
pop_heap(m_prio_heap.begin(), m_prio_heap.end(), greater<MsgPtr>());
pop_heap(m_prio_heap.begin(), m_prio_heap.end(), std::greater<MsgPtr>());
m_prio_heap.pop_back();
if (decrement_messages) {
// If the message will be removed from the queue, decrement the
@@ -340,18 +339,18 @@ MessageBuffer::recycle(Tick current_time, Tick recycle_latency)
DPRINTF(RubyQueue, "Recycling.\n");
assert(isReady(current_time));
MsgPtr node = m_prio_heap.front();
pop_heap(m_prio_heap.begin(), m_prio_heap.end(), greater<MsgPtr>());
pop_heap(m_prio_heap.begin(), m_prio_heap.end(), std::greater<MsgPtr>());
Tick future_time = current_time + recycle_latency;
node->setLastEnqueueTime(future_time);
m_prio_heap.back() = node;
push_heap(m_prio_heap.begin(), m_prio_heap.end(), greater<MsgPtr>());
push_heap(m_prio_heap.begin(), m_prio_heap.end(), std::greater<MsgPtr>());
m_consumer->scheduleEventAbsolute(future_time);
}
void
MessageBuffer::reanalyzeList(list<MsgPtr> &lt, Tick schdTick)
MessageBuffer::reanalyzeList(std::list<MsgPtr> &lt, Tick schdTick)
{
while (!lt.empty()) {
MsgPtr m = lt.front();
@@ -359,7 +358,7 @@ MessageBuffer::reanalyzeList(list<MsgPtr> &lt, Tick schdTick)
m_prio_heap.push_back(m);
push_heap(m_prio_heap.begin(), m_prio_heap.end(),
greater<MsgPtr>());
std::greater<MsgPtr>());
m_consumer->scheduleEventAbsolute(schdTick);
@@ -467,15 +466,15 @@ MessageBuffer::isDeferredMsgMapEmpty(Addr addr) const
}
void
MessageBuffer::print(ostream& out) const
MessageBuffer::print(std::ostream& out) const
{
ccprintf(out, "[MessageBuffer: ");
if (m_consumer != NULL) {
ccprintf(out, " consumer-yes ");
}
vector<MsgPtr> copy(m_prio_heap);
sort_heap(copy.begin(), copy.end(), greater<MsgPtr>());
std::vector<MsgPtr> copy(m_prio_heap);
std::sort_heap(copy.begin(), copy.end(), std::greater<MsgPtr>());
ccprintf(out, "%s] %s", copy, name());
}

30
src/mem/ruby/network/Topology.cc
View File

@@ -38,8 +38,6 @@
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
using namespace std;
const int INFINITE_LATENCY = 10000; // Yes, this is a big hack
// Note: In this file, we use the first 2*m_nodes SwitchIDs to
@@ -51,8 +49,8 @@ const int INFINITE_LATENCY = 10000; // Yes, this is a big hack
Topology::Topology(uint32_t num_nodes, uint32_t num_routers,
uint32_t num_vnets,
const vector<BasicExtLink *> &ext_links,
const vector<BasicIntLink *> &int_links)
const std::vector<BasicExtLink *> &ext_links,
const std::vector<BasicIntLink *> &int_links)
: m_nodes(MachineType_base_number(MachineType_NUM)),
m_number_of_switches(num_routers), m_vnets(num_vnets),
m_ext_link_vector(ext_links), m_int_link_vector(int_links)
@@ -68,7 +66,7 @@ Topology::Topology(uint32_t num_nodes, uint32_t num_routers,
// one for each direction.
//
// External Links
for (vector<BasicExtLink*>::const_iterator i = ext_links.begin();
for (std::vector<BasicExtLink*>::const_iterator i = ext_links.begin();
i != ext_links.end(); ++i) {
BasicExtLink *ext_link = (*i);
AbstractController *abs_cntrl = ext_link->params().ext_node;
@@ -87,7 +85,7 @@ Topology::Topology(uint32_t num_nodes, uint32_t num_routers,
}
// Internal Links
for (vector<BasicIntLink*>::const_iterator i = int_links.begin();
for (std::vector<BasicIntLink*>::const_iterator i = int_links.begin();
i != int_links.end(); ++i) {
BasicIntLink *int_link = (*i);
BasicRouter *router_src = int_link->params().src_node;
@@ -115,21 +113,21 @@ Topology::createLinks(Network *net)
for (LinkMap::const_iterator i = m_link_map.begin();
i != m_link_map.end(); ++i) {
std::pair<SwitchID, SwitchID> src_dest = (*i).first;
max_switch_id = max(max_switch_id, src_dest.first);
max_switch_id = max(max_switch_id, src_dest.second);
max_switch_id = std::max(max_switch_id, src_dest.first);
max_switch_id = std::max(max_switch_id, src_dest.second);
}
// Initialize weight, latency, and inter switched vectors
int num_switches = max_switch_id+1;
Matrix topology_weights(m_vnets,
vector<vector<int>>(num_switches,
vector<int>(num_switches, INFINITE_LATENCY)));
std::vector<std::vector<int>>(num_switches,
std::vector<int>(num_switches, INFINITE_LATENCY)));
Matrix component_latencies(num_switches,
vector<vector<int>>(num_switches,
vector<int>(m_vnets, -1)));
std::vector<std::vector<int>>(num_switches,
std::vector<int>(m_vnets, -1)));
Matrix component_inter_switches(num_switches,
vector<vector<int>>(num_switches,
vector<int>(m_vnets, 0)));
std::vector<std::vector<int>>(num_switches,
std::vector<int>(m_vnets, 0)));
// Set identity weights to zero
for (int i = 0; i < topology_weights[0].size(); i++) {
@@ -141,7 +139,7 @@ Topology::createLinks(Network *net)
// Fill in the topology weights and bandwidth multipliers
for (auto link_group : m_link_map) {
std::pair<int, int> src_dest = link_group.first;
vector<bool> vnet_done(m_vnets, 0);
std::vector<bool> vnet_done(m_vnets, 0);
int src = src_dest.first;
int dst = src_dest.second;
@@ -361,7 +359,7 @@ Topology::extend_shortest_path(Matrix &current_dist, Matrix &latencies,
int previous_minimum = minimum;
int intermediate_switch = -1;
for (int k = 0; k < nodes; k++) {
minimum = min(minimum,
minimum = std::min(minimum,
current_dist[v][i][k] + current_dist[v][k][j]);
if (previous_minimum != minimum) {
intermediate_switch = k;

27
src/mem/ruby/network/fault_model/FaultModel.cc
View File

@@ -45,8 +45,6 @@
#include "FaultModel.hh"
#include "base/logging.hh"
using namespace std;
#define MAX(a,b) ((a > b) ? (a) : (b))
@@ -98,7 +96,7 @@ FaultModel::FaultModel(const Params &p) : SimObject(p)
}
}
string
std::string
FaultModel::fault_type_to_string(int ft)
{
if (ft == data_corruption__few_bits){
@@ -247,23 +245,24 @@ FaultModel::fault_prob(int routerID,
void
FaultModel::print(void)
{
cout << "--- PRINTING configurations ---\n";
std::cout << "--- PRINTING configurations ---\n";
for (int record = 0; record < configurations.size(); record++){
cout << "(" << record << ") ";
cout << "VCs=" << configurations[record].vcs << " ";
cout << "Buff/VC=" << configurations[record].buff_per_vc << " [";
std::cout << "(" << record << ") ";
std::cout << "VCs=" << configurations[record].vcs << " ";
std::cout << "Buff/VC=" << configurations[record].buff_per_vc << " [";
for (int fault_type_num = 0;
fault_type_num < number_of_fault_types;
fault_type_num++){
cout << (100 * configurations[record].fault_type[fault_type_num]);
cout << "% ";
std::cout <<
(100 * configurations[record].fault_type[fault_type_num]);
std::cout << "% ";
}
cout << "]\n";
std::cout << "]\n";
}
cout << "--- PRINTING temperature weights ---\n";
std::cout << "--- PRINTING temperature weights ---\n";
for (int record = 0; record < temperature_weights.size(); record++){
cout << "temperature=" << record << " => ";
cout << "weight=" << temperature_weights[record];
cout << "\n";
std::cout << "temperature=" << record << " => ";
std::cout << "weight=" << temperature_weights[record];
std::cout << "\n";
}
}

16
src/mem/ruby/network/garnet/GarnetNetwork.cc
View File

@@ -45,8 +45,6 @@
#include "mem/ruby/network/garnet/Router.hh"
#include "mem/ruby/system/RubySystem.hh"
using namespace std;
/*
* GarnetNetwork sets up the routers and links and collects stats.
* Default parameters (GarnetNetwork.py) can be overwritten from command line
@@ -77,7 +75,7 @@ GarnetNetwork::GarnetNetwork(const Params &p)
}
// record the routers
for (vector<BasicRouter*>::const_iterator i = p.routers.begin();
for (std::vector<BasicRouter*>::const_iterator i = p.routers.begin();
i != p.routers.end(); ++i) {
Router* router = safe_cast<Router*>(*i);
m_routers.push_back(router);
@@ -87,7 +85,7 @@ GarnetNetwork::GarnetNetwork(const Params &p)
}
// record the network interfaces
for (vector<ClockedObject*>::const_iterator i = p.netifs.begin();
for (std::vector<ClockedObject*>::const_iterator i = p.netifs.begin();
i != p.netifs.end(); ++i) {
NetworkInterface *ni = safe_cast<NetworkInterface *>(*i);
m_nis.push_back(ni);
@@ -127,7 +125,7 @@ GarnetNetwork::init()
// FaultModel: declare each router to the fault model
if (isFaultModelEnabled()) {
for (vector<Router*>::const_iterator i= m_routers.begin();
for (std::vector<Router*>::const_iterator i= m_routers.begin();
i != m_routers.end(); ++i) {
Router* router = safe_cast<Router*>(*i);
M5_VAR_USED int router_id =
@@ -137,8 +135,8 @@ GarnetNetwork::init()
getBuffersPerDataVC(),
getBuffersPerCtrlVC());
assert(router_id == router->get_id());
router->printAggregateFaultProbability(cout);
router->printFaultVector(cout);
router->printAggregateFaultProbability(std::cout);
router->printFaultVector(std::cout);
}
}
}
@@ -524,7 +522,7 @@ GarnetNetwork::collateStats()
m_average_link_utilization +=
(double(activity) / time_delta);
vector<unsigned int> vc_load = m_networklinks[i]->getVcLoad();
std::vector<unsigned int> vc_load = m_networklinks[i]->getVcLoad();
for (int j = 0; j < vc_load.size(); j++) {
m_average_vc_load[j] += ((double)vc_load[j] / time_delta);
}
@@ -551,7 +549,7 @@ GarnetNetwork::resetStats()
}
void
GarnetNetwork::print(ostream& out) const
GarnetNetwork::print(std::ostream& out) const
{
out << "[GarnetNetwork]";
}

2
src/mem/ruby/network/garnet/InputUnit.cc
View File

@@ -35,8 +35,6 @@
#include "mem/ruby/network/garnet/Credit.hh"
#include "mem/ruby/network/garnet/Router.hh"
using namespace std;
InputUnit::InputUnit(int id, PortDirection direction, Router *router)
: Consumer(router), m_router(router), m_id(id), m_direction(direction),
m_vc_per_vnet(m_router->get_vc_per_vnet())

8
src/mem/ruby/network/garnet/NetworkInterface.cc
View File

@@ -42,8 +42,6 @@
#include "mem/ruby/network/garnet/flitBuffer.hh"
#include "mem/ruby/slicc_interface/Message.hh"
using namespace std;
NetworkInterface::NetworkInterface(const Params &p)
: ClockedObject(p), Consumer(this), m_id(p.id),
m_virtual_networks(p.virt_nets), m_vc_per_vnet(0),
@@ -120,8 +118,8 @@ NetworkInterface::addOutPort(NetworkLink *out_link,
}
void
NetworkInterface::addNode(vector<MessageBuffer *>& in,
vector<MessageBuffer *>& out)
NetworkInterface::addNode(std::vector<MessageBuffer *>& in,
std::vector<MessageBuffer *>& out)
{
inNode_ptr = in;
outNode_ptr = out;
@@ -365,7 +363,7 @@ NetworkInterface::flitisizeMessage(MsgPtr msg_ptr, int vnet)
NetDest net_msg_dest = net_msg_ptr->getDestination();
// gets all the destinations associated with this message.
vector<NodeID> dest_nodes = net_msg_dest.getAllDest();
std::vector<NodeID> dest_nodes = net_msg_dest.getAllDest();
// Number of flits is dependent on the link bandwidth available.
// This is expressed in terms of bytes/cycle or the flit size

10
src/mem/ruby/network/garnet/Router.cc
View File

@@ -39,8 +39,6 @@
#include "mem/ruby/network/garnet/NetworkLink.hh"
#include "mem/ruby/network/garnet/OutputUnit.hh"
using namespace std;
Router::Router(const Params &p)
: BasicRouter(p), Consumer(this), m_latency(p.latency),
m_virtual_networks(p.virt_nets), m_vc_per_vnet(p.vcs_per_vnet),
@@ -239,20 +237,20 @@ Router::resetStats()
}
void
Router::printFaultVector(ostream& out)
Router::printFaultVector(std::ostream& out)
{
int temperature_celcius = BASELINE_TEMPERATURE_CELCIUS;
int num_fault_types = m_network_ptr->fault_model->number_of_fault_types;
float fault_vector[num_fault_types];
get_fault_vector(temperature_celcius, fault_vector);
out << "Router-" << m_id << " fault vector: " << endl;
out << "Router-" << m_id << " fault vector: " << std::endl;
for (int fault_type_index = 0; fault_type_index < num_fault_types;
fault_type_index++) {
out << " - probability of (";
out <<
m_network_ptr->fault_model->fault_type_to_string(fault_type_index);
out << ") = ";
out << fault_vector[fault_type_index] << endl;
out << fault_vector[fault_type_index] << std::endl;
}
}
@@ -264,7 +262,7 @@ Router::printAggregateFaultProbability(std::ostream& out)
get_aggregate_fault_probability(temperature_celcius,
&aggregate_fault_prob);
out << "Router-" << m_id << " fault probability: ";
out << aggregate_fault_prob << endl;
out << aggregate_fault_prob << std::endl;
}
uint32_t

10
src/mem/ruby/network/simple/PerfectSwitch.cc
View File

@@ -39,8 +39,6 @@
#include "mem/ruby/network/simple/Switch.hh"
#include "mem/ruby/slicc_interface/Message.hh"
using namespace std;
const int PRIORITY_SWITCH_LIMIT = 128;
// Operator for helper class
@@ -69,7 +67,7 @@ PerfectSwitch::init(SimpleNetwork *network_ptr)
}
void
PerfectSwitch::addInPort(const vector<MessageBuffer*>& in)
PerfectSwitch::addInPort(const std::vector<MessageBuffer*>& in)
{
NodeID port = m_in.size();
m_in.push_back(in);
@@ -84,7 +82,7 @@ PerfectSwitch::addInPort(const vector<MessageBuffer*>& in)
}
void
PerfectSwitch::addOutPort(const vector<MessageBuffer*>& out,
PerfectSwitch::addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry)
{
// Setup link order
@@ -144,8 +142,8 @@ PerfectSwitch::operateMessageBuffer(MessageBuffer *buffer, int incoming,
Message *net_msg_ptr = NULL;
// temporary vectors to store the routing results
vector<LinkID> output_links;
vector<NetDest> output_link_destinations;
std::vector<LinkID> output_links;
std::vector<NetDest> output_link_destinations;
Tick current_time = m_switch->clockEdge();
while (buffer->isReady(current_time)) {

8
src/mem/ruby/network/simple/SimpleNetwork.cc
View File

@@ -52,8 +52,6 @@
#include "mem/ruby/network/simple/Throttle.hh"
#include "mem/ruby/profiler/Profiler.hh"
using namespace std;
SimpleNetwork::SimpleNetwork(const Params &p)
: Network(p), m_buffer_size(p.buffer_size),
m_endpoint_bandwidth(p.endpoint_bandwidth),
@@ -61,7 +59,7 @@ SimpleNetwork::SimpleNetwork(const Params &p)
networkStats(this)
{
// record the routers
for (vector<BasicRouter*>::const_iterator i = p.routers.begin();
for (std::vector<BasicRouter*>::const_iterator i = p.routers.begin();
i != p.routers.end(); ++i) {
Switch* s = safe_cast<Switch*>(*i);
m_switches.push_back(s);
@@ -180,7 +178,7 @@ SimpleNetwork::collateStats()
}
void
SimpleNetwork::print(ostream& out) const
SimpleNetwork::print(std::ostream& out) const
{
out << "[SimpleNetwork]";
}
@@ -225,4 +223,4 @@ NetworkStats::NetworkStats(Stats::Group *parent)
: Stats::Group(parent)
{
}
}

7
src/mem/ruby/network/simple/Switch.cc
View File

@@ -48,7 +48,6 @@
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/simple/SimpleNetwork.hh"
using namespace std;
using m5::stl_helpers::operator<<;
Switch::Switch(const Params &p)
@@ -70,13 +69,13 @@ Switch::init()
}
void
Switch::addInPort(const vector<MessageBuffer*>& in)
Switch::addInPort(const std::vector<MessageBuffer*>& in)
{
perfectSwitch.addInPort(in);
}
void
Switch::addOutPort(const vector<MessageBuffer*>& out,
Switch::addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry,
Cycles link_latency, int bw_multiplier)
{
@@ -86,7 +85,7 @@ Switch::addOutPort(const vector<MessageBuffer*>& out,
m_network_ptr->getEndpointBandwidth(), this);
// Create one buffer per vnet (these are intermediaryQueues)
vector<MessageBuffer*> intermediateBuffers;
std::vector<MessageBuffer*> intermediateBuffers;
for (int i = 0; i < out.size(); ++i) {
assert(m_num_connected_buffers < m_port_buffers.size());

16
src/mem/ruby/network/simple/Throttle.cc
View File

@@ -39,8 +39,6 @@
#include "mem/ruby/slicc_interface/Message.hh"
#include "mem/ruby/system/RubySystem.hh"
using namespace std;
const int MESSAGE_SIZE_MULTIPLIER = 1000;
//const int BROADCAST_SCALING = 4; // Have a 16p system act like a 64p systems
const int BROADCAST_SCALING = 1;
@@ -69,8 +67,8 @@ Throttle::Throttle(int sID, RubySystem *rs, NodeID node, Cycles link_latency,
}
void
Throttle::addLinks(const vector<MessageBuffer*>& in_vec,
const vector<MessageBuffer*>& out_vec)
Throttle::addLinks(const std::vector<MessageBuffer*>& in_vec,
const std::vector<MessageBuffer*>& out_vec)
{
assert(in_vec.size() == out_vec.size());
@@ -85,8 +83,8 @@ Throttle::addLinks(const vector<MessageBuffer*>& in_vec,
// Set consumer and description
in_ptr->setConsumer(this);
string desc = "[Queue to Throttle " + to_string(m_switch_id) + " " +
to_string(m_node) + "]";
std::string desc = "[Queue to Throttle " +
std::to_string(m_switch_id) + " " + std::to_string(m_node) + "]";
}
}
@@ -131,8 +129,8 @@ Throttle::operateVnet(int vnet, int &bw_remaining, bool &schedule_wakeup,
// Calculate the amount of bandwidth we spent on this message
int diff = m_units_remaining[vnet] - bw_remaining;
m_units_remaining[vnet] = max(0, diff);
bw_remaining = max(0, -diff);
m_units_remaining[vnet] = std::max(0, diff);
bw_remaining = std::max(0, -diff);
}
if (bw_remaining > 0 && (in->isReady(current_time) ||
@@ -245,7 +243,7 @@ Throttle::collateStats()
}
void
Throttle::print(ostream& out) const
Throttle::print(std::ostream& out) const
{
ccprintf(out, "[%i bw: %i]", m_node, getLinkBandwidth());
}

113
src/mem/ruby/profiler/AddressProfiler.cc
View File

@@ -35,7 +35,6 @@
#include "mem/ruby/profiler/Profiler.hh"
#include "mem/ruby/protocol/RubyRequest.hh"
using namespace std;
typedef AddressProfiler::AddressMap AddressMap;
using m5::stl_helpers::operator<<;
@@ -50,8 +49,8 @@ lookupTraceForAddress(Addr addr, AddressMap& record_map)
// like it could hurt.
static const AccessTraceForAddress dflt;
pair<AddressMap::iterator, bool> r =
record_map.insert(make_pair(addr, dflt));
std::pair<AddressMap::iterator, bool> r =
record_map.insert(std::make_pair(addr, dflt));
AddressMap::iterator i = r.first;
AccessTraceForAddress &access_trace = i->second;
if (r.second) {
@@ -64,8 +63,9 @@ lookupTraceForAddress(Addr addr, AddressMap& record_map)
}
void
printSorted(ostream& out, int num_of_sequencers, const AddressMap &record_map,
string description, Profiler *profiler)
printSorted(std::ostream& out, int num_of_sequencers,
const AddressMap &record_map, std::string description,
Profiler *profiler)
{
const int records_printed = 100;
@@ -82,14 +82,17 @@ printSorted(ostream& out, int num_of_sequencers, const AddressMap &record_map,
sort(sorted.begin(), sorted.end(), AccessTraceForAddress::less_equal);
out << "Total_entries_" << description << ": " << record_map.size()
<< endl;
if (profiler->getAllInstructions())
out << "Total_Instructions_" << description << ": " << misses << endl;
else
out << "Total_data_misses_" << description << ": " << misses << endl;
<< std::endl;
if (profiler->getAllInstructions()) {
out << "Total_Instructions_" << description << ": " << misses
<< std::endl;
} else {
out << "Total_data_misses_" << description << ": " << misses
<< std::endl;
}
out << "total | load store atomic | user supervisor | sharing | touched-by"
<< endl;
<< std::endl;
Histogram remaining_records(1, 100);
Histogram all_records(1, 100);
@@ -111,7 +114,8 @@ printSorted(ostream& out, int num_of_sequencers, const AddressMap &record_map,
while (counter < max && counter < records_printed) {
const AccessTraceForAddress* record = sorted[counter];
double percent = 100.0 * (record->getTotal() / double(misses));
out << description << " | " << percent << " % " << *record << endl;
out << description << " | " << percent << " % " << *record
<< std::endl;
all_records.add(record->getTotal());
all_records_log.add(record->getTotal());
counter++;
@@ -128,20 +132,20 @@ printSorted(ostream& out, int num_of_sequencers, const AddressMap &record_map,
m_touched_vec[record->getTouchedBy()]++;
m_touched_weighted_vec[record->getTouchedBy()] += record->getTotal();
}
out << endl;
out << std::endl;
out << "all_records_" << description << ": "
<< all_records << endl
<< all_records << std::endl
<< "all_records_log_" << description << ": "
<< all_records_log << endl
<< all_records_log << std::endl
<< "remaining_records_" << description << ": "
<< remaining_records << endl
<< remaining_records << std::endl
<< "remaining_records_log_" << description << ": "
<< remaining_records_log << endl
<< remaining_records_log << std::endl
<< "touched_by_" << description << ": "
<< m_touched_vec << endl
<< m_touched_vec << std::endl
<< "touched_by_weighted_" << description << ": "
<< m_touched_weighted_vec << endl
<< endl;
<< m_touched_weighted_vec << std::endl
<< std::endl;
}
AddressProfiler::AddressProfiler(int num_of_sequencers, Profiler *profiler)
@@ -168,64 +172,69 @@ AddressProfiler::setAllInstructions(bool all_instructions)
}
void
AddressProfiler::printStats(ostream& out) const
AddressProfiler::printStats(std::ostream& out) const
{
if (m_hot_lines) {
out << endl;
out << "AddressProfiler Stats" << endl;
out << "---------------------" << endl;
out << std::endl;
out << "AddressProfiler Stats" << std::endl;
out << "---------------------" << std::endl;
out << endl;
out << "sharing_misses: " << m_sharing_miss_counter << endl;
out << "getx_sharing_histogram: " << m_getx_sharing_histogram << endl;
out << "gets_sharing_histogram: " << m_gets_sharing_histogram << endl;
out << std::endl;
out << "sharing_misses: " << m_sharing_miss_counter << std::endl;
out << "getx_sharing_histogram: " << m_getx_sharing_histogram
<< std::endl;
out << "gets_sharing_histogram: " << m_gets_sharing_histogram
<< std::endl;
out << endl;
out << "Hot Data Blocks" << endl;
out << "---------------" << endl;
out << endl;
out << std::endl;
out << "Hot Data Blocks" << std::endl;
out << "---------------" << std::endl;
out << std::endl;
printSorted(out, m_num_of_sequencers, m_dataAccessTrace,
"block_address", m_profiler);
out << endl;
out << "Hot MacroData Blocks" << endl;
out << "--------------------" << endl;
out << endl;
out << std::endl;
out << "Hot MacroData Blocks" << std::endl;
out << "--------------------" << std::endl;
out << std::endl;
printSorted(out, m_num_of_sequencers, m_macroBlockAccessTrace,
"macroblock_address", m_profiler);
out << "Hot Instructions" << endl;
out << "----------------" << endl;
out << endl;
out << "Hot Instructions" << std::endl;
out << "----------------" << std::endl;
out << std::endl;
printSorted(out, m_num_of_sequencers, m_programCounterAccessTrace,
"pc_address", m_profiler);
}
if (m_all_instructions) {
out << endl;
out << "All Instructions Profile:" << endl;
out << "-------------------------" << endl;
out << endl;
out << std::endl;
out << "All Instructions Profile:" << std::endl;
out << "-------------------------" << std::endl;
out << std::endl;
printSorted(out, m_num_of_sequencers, m_programCounterAccessTrace,
"pc_address", m_profiler);
out << endl;
out << std::endl;
}
if (m_retryProfileHisto.size() > 0) {
out << "Retry Profile" << endl;
out << "-------------" << endl;
out << endl;
out << "retry_histogram_absolute: " << m_retryProfileHisto << endl;
out << "retry_histogram_write: " << m_retryProfileHistoWrite << endl;
out << "retry_histogram_read: " << m_retryProfileHistoRead << endl;
out << "Retry Profile" << std::endl;
out << "-------------" << std::endl;
out << std::endl;
out << "retry_histogram_absolute: " << m_retryProfileHisto
<< std::endl;
out << "retry_histogram_write: " << m_retryProfileHistoWrite
<< std::endl;
out << "retry_histogram_read: " << m_retryProfileHistoRead
<< std::endl;
out << "retry_histogram_percent: ";
m_retryProfileHisto.printPercent(out);
out << endl;
out << std::endl;
printSorted(out, m_num_of_sequencers, m_retryProfileMap,
"block_address", m_profiler);
out << endl;
out << std::endl;
}
}

7
src/mem/ruby/profiler/Profiler.cc
View File

@@ -77,7 +77,6 @@
#include "mem/ruby/system/Sequencer.hh"
using namespace std;
using m5::stl_helpers::operator<<;
Profiler::Profiler(const RubySystemParams &p, RubySystem *rs)
@@ -367,7 +366,7 @@ Profiler::collateStats()
}
for (uint32_t i = 0; i < MachineType_NUM; i++) {
for (map<uint32_t, AbstractController*>::iterator it =
for (std::map<uint32_t, AbstractController*>::iterator it =
m_ruby_system->m_abstract_controls[i].begin();
it != m_ruby_system->m_abstract_controls[i].end(); ++it) {
@@ -382,7 +381,7 @@ Profiler::collateStats()
}
for (uint32_t i = 0; i < MachineType_NUM; i++) {
for (map<uint32_t, AbstractController*>::iterator it =
for (std::map<uint32_t, AbstractController*>::iterator it =
m_ruby_system->m_abstract_controls[i].begin();
it != m_ruby_system->m_abstract_controls[i].end(); ++it) {
@@ -403,7 +402,7 @@ Profiler::collateStats()
}
for (uint32_t i = 0; i < MachineType_NUM; i++) {
for (map<uint32_t, AbstractController*>::iterator it =
for (std::map<uint32_t, AbstractController*>::iterator it =
m_ruby_system->m_abstract_controls[i].begin();
it != m_ruby_system->m_abstract_controls[i].end(); ++it) {

29
src/mem/ruby/profiler/StoreTrace.cc
View File

@@ -30,8 +30,6 @@
#include "sim/core.hh"
using namespace std;
bool StoreTrace::s_init = false; // Total number of store lifetimes of
// all lines
int64_t StoreTrace::s_total_samples = 0; // Total number of store
@@ -59,14 +57,14 @@ StoreTrace::~StoreTrace()
}
void
StoreTrace::print(ostream& out) const
StoreTrace::print(std::ostream& out) const
{
out << m_addr
<< " total_samples: " << m_total_samples << endl
<< "store_count: " << m_store_count << endl
<< "store_first_to_stolen: " << m_store_first_to_stolen << endl
<< "store_last_to_stolen: " << m_store_last_to_stolen << endl
<< "store_first_to_last: " << m_store_first_to_last << endl;
<< " total_samples: " << m_total_samples << std::endl
<< "store_count: " << m_store_count << std::endl
<< "store_first_to_stolen: " << m_store_first_to_stolen << std::endl
<< "store_last_to_stolen: " << m_store_last_to_stolen << std::endl
<< "store_first_to_last: " << m_store_first_to_last << std::endl;
}
void
@@ -83,13 +81,16 @@ StoreTrace::initSummary()
}
void
StoreTrace::printSummary(ostream& out)
StoreTrace::printSummary(std::ostream& out)
{
out << "total_samples: " << s_total_samples << endl;
out << "store_count: " << (*s_store_count_ptr) << endl;
out << "store_first_to_stolen: " << (*s_store_first_to_stolen_ptr) << endl;
out << "store_last_to_stolen: " << (*s_store_last_to_stolen_ptr) << endl;
out << "store_first_to_last: " << (*s_store_first_to_last_ptr) << endl;
out << "total_samples: " << s_total_samples << std::endl;
out << "store_count: " << (*s_store_count_ptr) << std::endl;
out << "store_first_to_stolen: "
<< (*s_store_first_to_stolen_ptr) << std::endl;
out << "store_last_to_stolen: "
<< (*s_store_last_to_stolen_ptr) << std::endl;
out << "store_first_to_last: " << (*s_store_first_to_last_ptr)
<< std::endl;
}
void

14
src/mem/ruby/slicc_interface/RubyRequest.cc
View File

@@ -44,17 +44,15 @@
#include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
using namespace std;
void
RubyRequest::print(ostream& out) const
RubyRequest::print(std::ostream& out) const
{
out << "[RubyRequest: ";
out << hex << "LineAddress = 0x" << m_LineAddress << dec << " ";
out << hex << "PhysicalAddress = 0x" << m_PhysicalAddress << dec << " ";
out << "Type = " << m_Type << " ";
out << hex << "ProgramCounter = 0x" << m_ProgramCounter << dec << " ";
out << "AccessMode = " << m_AccessMode << " ";
out << std::hex << "LineAddress = 0x" << m_LineAddress << std::dec << " ";
out << std::hex << "PhysicalAddress = 0x" << m_PhysicalAddress;
out << std::dec << " " << "Type = " << m_Type << " ";
out << std::hex << "ProgramCounter = 0x" << m_ProgramCounter << std::dec;
out << " " << "AccessMode = " << m_AccessMode << " ";
out << "Size = " << m_Size << " ";
out << "Prefetch = " << m_Prefetch << " ";
// out << "Time = " << getTime() << " ";

22
src/mem/ruby/structures/CacheMemory.cc
View File

@@ -52,13 +52,11 @@
#include "mem/ruby/protocol/AccessPermission.hh"
#include "mem/ruby/system/RubySystem.hh"
using namespace std;
ostream&
operator<<(ostream& out, const CacheMemory& obj)
std::ostream&
operator<<(std::ostream& out, const CacheMemory& obj)
{
obj.print(out);
out << flush;
out << std::flush;
return out;
}
@@ -446,28 +444,28 @@ CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const
}
void
CacheMemory::print(ostream& out) const
CacheMemory::print(std::ostream& out) const
{
out << "Cache dump: " << name() << endl;
out << "Cache dump: " << name() << std::endl;
for (int i = 0; i < m_cache_num_sets; i++) {
for (int j = 0; j < m_cache_assoc; j++) {
if (m_cache[i][j] != NULL) {
out << " Index: " << i
<< " way: " << j
<< " entry: " << *m_cache[i][j] << endl;
<< " entry: " << *m_cache[i][j] << std::endl;
} else {
out << " Index: " << i
<< " way: " << j
<< " entry: NULL" << endl;
<< " entry: NULL" << std::endl;
}
}
}
}
void
CacheMemory::printData(ostream& out) const
CacheMemory::printData(std::ostream& out) const
{
out << "printData() not supported" << endl;
out << "printData() not supported" << std::endl;
}
void
@@ -748,4 +746,4 @@ void
CacheMemory::profileDemandMiss()
{
cacheMemoryStats.m_demand_misses++;
}
}

4
src/mem/ruby/structures/DirectoryMemory.cc
View File

@@ -49,8 +49,6 @@
#include "mem/ruby/system/RubySystem.hh"
#include "sim/system.hh"
using namespace std;
DirectoryMemory::DirectoryMemory(const Params &p)
: SimObject(p), addrRanges(p.addr_ranges.begin(), p.addr_ranges.end())
{
@@ -149,7 +147,7 @@ DirectoryMemory::deallocate(Addr address)
}
void
DirectoryMemory::print(ostream& out) const
DirectoryMemory::print(std::ostream& out) const
{
}

7
src/mem/ruby/structures/PersistentTable.cc
View File

@@ -28,9 +28,6 @@
#include "mem/ruby/structures/PersistentTable.hh"
using namespace std;
PersistentTable::PersistentTable()
{
}
@@ -47,7 +44,7 @@ PersistentTable::persistentRequestLock(Addr address,
assert(address == makeLineAddress(address));
static const PersistentTableEntry dflt;
pair<AddressMap::iterator, bool> r =
std::pair<AddressMap::iterator, bool> r =
m_map.insert(AddressMap::value_type(address, dflt));
bool present = !r.second;
AddressMap::iterator i = r.first;
@@ -190,7 +187,7 @@ PersistentTable::countReadStarvingForAddress(Addr address) const
}
void
PersistentTable::print(ostream& out) const
PersistentTable::print(std::ostream& out) const
{
}

17
src/mem/ruby/structures/WireBuffer.cc
View File

@@ -38,15 +38,13 @@
#include "base/stl_helpers.hh"
#include "mem/ruby/system/RubySystem.hh"
using namespace std;
// Output operator definition
ostream&
operator<<(ostream& out, const WireBuffer& obj)
std::ostream&
operator<<(std::ostream& out, const WireBuffer& obj)
{
obj.print(out);
out << flush;
out << std::flush;
return out;
}
@@ -92,7 +90,7 @@ WireBuffer::dequeue(Tick current_time)
{
assert(isReady(current_time));
pop_heap(m_message_queue.begin(), m_message_queue.end(),
greater<MsgPtr>());
std::greater<MsgPtr>());
m_message_queue.pop_back();
}
@@ -113,14 +111,15 @@ WireBuffer::recycle(Tick current_time, Tick recycle_latency)
// being stuck behind something if you're not actually supposed to.
assert(isReady(current_time));
MsgPtr node = m_message_queue.front();
pop_heap(m_message_queue.begin(), m_message_queue.end(), greater<MsgPtr>());
pop_heap(m_message_queue.begin(), m_message_queue.end(),
std::greater<MsgPtr>());
Tick future_time = current_time + recycle_latency;
node->setLastEnqueueTime(future_time);
m_message_queue.back() = node;
push_heap(m_message_queue.begin(), m_message_queue.end(),
greater<MsgPtr>());
std::greater<MsgPtr>());
m_consumer_ptr->
scheduleEventAbsolute(future_time);
}
@@ -133,7 +132,7 @@ WireBuffer::isReady(Tick current_time)
}
void
WireBuffer::print(ostream& out) const
WireBuffer::print(std::ostream& out) const
{
}

6
src/mem/ruby/system/CacheRecorder.cc
View File

@@ -33,10 +33,8 @@
#include "mem/ruby/system/RubySystem.hh"
#include "mem/ruby/system/Sequencer.hh"
using namespace std;
void
TraceRecord::print(ostream& out) const
TraceRecord::print(std::ostream& out) const
{
out << "[TraceRecord: Node, " << m_cntrl_id << ", "
<< m_data_address << ", " << m_pc_address << ", "
@@ -179,7 +177,7 @@ CacheRecorder::aggregateRecords(uint8_t **buf, uint64_t total_size)
for (int i = 0; i < size; ++i) {
// Determine if we need to expand the buffer size
if (current_size + record_size > total_size) {
uint8_t* new_buf = new (nothrow) uint8_t[total_size * 2];
uint8_t* new_buf = new (std::nothrow) uint8_t[total_size * 2];
if (new_buf == NULL) {
fatal("Unable to allocate buffer of size %s\n",
total_size * 2);

8
src/mem/ruby/system/GPUCoalescer.cc
View File

@@ -54,8 +54,6 @@
#include "mem/ruby/system/RubySystem.hh"
#include "params/RubyGPUCoalescer.hh"
using namespace std;
UncoalescedTable::UncoalescedTable(GPUCoalescer *gc)
: coalescer(gc)
{
@@ -350,7 +348,7 @@ GPUCoalescer::resetStats()
}
void
GPUCoalescer::printProgress(ostream& out) const
GPUCoalescer::printProgress(std::ostream& out) const
{
}
@@ -666,7 +664,7 @@ GPUCoalescer::makeRequest(PacketPtr pkt)
template <class KEY, class VALUE>
std::ostream &
operator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map)
operator<<(std::ostream &out, const std::unordered_map<KEY, VALUE> &map)
{
out << "[";
for (auto i = map.begin(); i != map.end(); ++i)
@@ -677,7 +675,7 @@ operator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map)
}
void
GPUCoalescer::print(ostream& out) const
GPUCoalescer::print(std::ostream& out) const
{
out << "[GPUCoalescer: " << m_version
<< ", outstanding requests: " << m_outstanding_count

6
src/mem/ruby/system/HTMSequencer.cc
View File

@@ -42,8 +42,6 @@
#include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
#include "sim/system.hh"
using namespace std;
HtmCacheFailure
HTMSequencer::htmRetCodeConversion(
const HtmFailedInCacheReason ruby_ret_code)
@@ -307,7 +305,7 @@ HTMSequencer::empty() const
template <class VALUE>
std::ostream &
operator<<(ostream &out, const std::deque<VALUE> &queue)
operator<<(std::ostream &out, const std::deque<VALUE> &queue)
{
auto i = queue.begin();
auto end = queue.end();
@@ -321,7 +319,7 @@ operator<<(ostream &out, const std::deque<VALUE> &queue)
}
void
HTMSequencer::print(ostream& out) const
HTMSequencer::print(std::ostream& out) const
{
Sequencer::print(out);

21
src/mem/ruby/system/RubySystem.cc
View File

@@ -59,8 +59,6 @@
#include "sim/simulate.hh"
#include "sim/system.hh"
using namespace std;
bool RubySystem::m_randomization;
uint32_t RubySystem::m_block_size_bytes;
uint32_t RubySystem::m_block_size_bits;
@@ -172,7 +170,7 @@ RubySystem::makeCacheRecorder(uint8_t *uncompressed_trace,
uint64_t cache_trace_size,
uint64_t block_size_bytes)
{
vector<Sequencer*> sequencer_map;
std::vector<Sequencer*> sequencer_map;
Sequencer* sequencer_ptr = NULL;
for (int cntrl = 0; cntrl < m_abs_cntrl_vec.size(); cntrl++) {
@@ -219,14 +217,15 @@ RubySystem::memWriteback()
// Deschedule all prior events on the event queue, but record the tick they
// were scheduled at so they can be restored correctly later.
list<pair<Event*, Tick> > original_events;
std::list<std::pair<Event*, Tick> > original_events;
while (!eventq->empty()) {
Event *curr_head = eventq->getHead();
if (curr_head->isAutoDelete()) {
DPRINTF(RubyCacheTrace, "Event %s auto-deletes when descheduled,"
" not recording\n", curr_head->name());
} else {
original_events.push_back(make_pair(curr_head, curr_head->when()));
original_events.push_back(
std::make_pair(curr_head, curr_head->when()));
}
eventq->deschedule(curr_head);
}
@@ -249,7 +248,7 @@ RubySystem::memWriteback()
// done after setting curTick back to its original value so that events do
// not seem to be scheduled in the past.
while (!original_events.empty()) {
pair<Event*, Tick> event = original_events.back();
std::pair<Event*, Tick> event = original_events.back();
eventq->schedule(event.first, event.second);
original_events.pop_back();
}
@@ -273,11 +272,11 @@ RubySystem::memWriteback()
}
void
RubySystem::writeCompressedTrace(uint8_t *raw_data, string filename,
RubySystem::writeCompressedTrace(uint8_t *raw_data, std::string filename,
uint64_t uncompressed_trace_size)
{
// Create the checkpoint file for the memory
string thefile = CheckpointIn::dir() + "/" + filename.c_str();
std::string thefile = CheckpointIn::dir() + "/" + filename.c_str();
int fd = creat(thefile.c_str(), 0664);
if (fd < 0) {
@@ -321,7 +320,7 @@ RubySystem::serialize(CheckpointOut &cp) const
uint8_t *raw_data = new uint8_t[4096];
uint64_t cache_trace_size = m_cache_recorder->aggregateRecords(&raw_data,
4096);
string cache_trace_file = name() + ".cache.gz";
std::string cache_trace_file = name() + ".cache.gz";
writeCompressedTrace(raw_data, cache_trace_file, cache_trace_size);
SERIALIZE_SCALAR(cache_trace_file);
@@ -340,7 +339,7 @@ RubySystem::drainResume()
}
void
RubySystem::readCompressedTrace(string filename, uint8_t *&raw_data,
RubySystem::readCompressedTrace(std::string filename, uint8_t *&raw_data,
uint64_t &uncompressed_trace_size)
{
// Read the trace file
@@ -381,7 +380,7 @@ RubySystem::unserialize(CheckpointIn &cp)
uint64_t block_size_bytes = getBlockSizeBytes();
UNSERIALIZE_OPT_SCALAR(block_size_bytes);
string cache_trace_file;
std::string cache_trace_file;
uint64_t cache_trace_size = 0;
UNSERIALIZE_SCALAR(cache_trace_file);

6
src/mem/ruby/system/Sequencer.cc
View File

@@ -59,8 +59,6 @@
#include "mem/ruby/system/RubySystem.hh"
#include "sim/system.hh"
using namespace std;
Sequencer::Sequencer(const Params &p)
: RubyPort(p), m_IncompleteTimes(MachineType_NUM),
deadlockCheckEvent([this]{ wakeup(); }, "Sequencer deadlock check")
@@ -801,7 +799,7 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
template <class KEY, class VALUE>
std::ostream &
operator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map)
operator<<(std::ostream &out, const std::unordered_map<KEY, VALUE> &map)
{
for (const auto &table_entry : map) {
out << "[ " << table_entry.first << " =";
@@ -815,7 +813,7 @@ operator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map)
}
void
Sequencer::print(ostream& out) const
Sequencer::print(std::ostream& out) const
{
out << "[Sequencer: " << m_version
<< ", outstanding requests: " << m_outstanding_count

2
src/mem/ruby/system/VIPERCoalescer.cc
View File

@@ -51,8 +51,6 @@
#include "mem/ruby/system/RubySystem.hh"
#include "params/VIPERCoalescer.hh"
using namespace std;
VIPERCoalescer::VIPERCoalescer(const Params &p)
: GPUCoalescer(p),
m_cache_inv_pkt(nullptr),

11
src/mem/slicc/symbols/StateMachine.py
View File

@@ -524,11 +524,6 @@ void unset_tbe(${{self.TBEType.c_ident}}*& m_tbe_ptr);
for include_path in includes:
code('#include "${{include_path}}"')
code('''
using namespace std;
''')
# include object classes
seen_types = set()
for var in self.objects:
@@ -544,7 +539,7 @@ std::vector<Stats::Vector *> $c_ident::eventVec;
std::vector<std::vector<Stats::Vector *> > $c_ident::transVec;
// for adding information to the protocol debug trace
stringstream ${ident}_transitionComment;
std::stringstream ${ident}_transitionComment;
#ifndef NDEBUG
#define APPEND_TRANSITION_COMMENT(str) (${ident}_transitionComment << str)
@@ -978,7 +973,7 @@ $c_ident::getMemRespQueue() const
}
void
$c_ident::print(ostream& out) const
$c_ident::print(std::ostream& out) const
{
out << "[$c_ident " << m_version << "]";
}
@@ -1221,8 +1216,6 @@ $c_ident::functionalReadBuffers(PacketPtr& pkt)
code('''
using namespace std;
void
${ident}_Controller::wakeup()
{

16
src/mem/slicc/symbols/Type.py
View File

@@ -430,14 +430,12 @@ operator<<(std::ostream& out, const ${{self.c_ident}}& obj)
#include "mem/ruby/protocol/${{self.c_ident}}.hh"
#include "mem/ruby/system/RubySystem.hh"
using namespace std;
''')
code('''
/** \\brief Print the state of this object */
void
${{self.c_ident}}::print(ostream& out) const
${{self.c_ident}}::print(std::ostream& out) const
{
out << "[${{self.c_ident}}: ";
''')
@@ -584,8 +582,6 @@ std::ostream& operator<<(std::ostream& out, const ${{self.c_ident}}& obj);
#include "base/logging.hh"
#include "mem/ruby/protocol/${{self.c_ident}}.hh"
using namespace std;
''')
if self.isStateDecl:
@@ -618,16 +614,16 @@ AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj)
code('''
// Code for output operator
ostream&
operator<<(ostream& out, const ${{self.c_ident}}& obj)
std::ostream&
operator<<(std::ostream& out, const ${{self.c_ident}}& obj)
{
out << ${{self.c_ident}}_to_string(obj);
out << flush;
out << std::flush;
return out;
}
// Code to convert state to a string
string
std::string
${{self.c_ident}}_to_string(const ${{self.c_ident}}& obj)
{
switch(obj) {
@@ -649,7 +645,7 @@ ${{self.c_ident}}_to_string(const ${{self.c_ident}}& obj)
// Code to convert from a string to the enumeration
${{self.c_ident}}
string_to_${{self.c_ident}}(const string& str)
string_to_${{self.c_ident}}(const std::string& str)
{
''')