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  • 258a1ad47d arch-riscv: Use std::abs in riscv to avoid a warning. Gabe Black 2021-10-14 18:26:33 -07:00
  • fe42b599a7 cpu: Fix style in BPredUnit. Gabe Black 2021-10-14 01:54:50 -07:00
  • 212813b90a cpu: Fix style in the RAS. Gabe Black 2021-10-14 01:48:10 -07:00
  • c5ba40cfe1 mem-ruby: Add GPUonly parameter for VIPER Matthew Poremba 2021-10-21 17:31:18 -05:00
  • 55fdf4be52 mem-ruby: Add missing CPUonly check for VIPER Matthew Poremba 2021-10-21 17:27:37 -05:00
  • e1de4abdb0 scons: Fix linker flags for prof/perf builds. Gabe Black 2021-10-24 23:30:58 -07:00
  • 45cfd99ce9 scons: allow building gem5 in a nix environment Austin Harris 2021-09-11 16:18:33 -05:00
  • c594bf8e24 scons: Pull info.py generation out of SConscript and into build_tools. Gabe Black 2021-08-15 03:00:13 -07:00
  • 4a2b4f162b arch: Remove the page_size.hh switching header file. Gabe Black 2021-09-21 17:15:03 -07:00
  • 6107dd11c6 misc: Remove include of arch/page_size.hh, and fix up includes. Gabe Black 2021-09-21 17:22:54 -07:00
  • e65237a418 sim: Get rid of the now unused System::getPageBytes method. Gabe Black 2021-09-21 17:13:40 -07:00
  • 07c613ff5e dev,gpu-compute: Use a TranslationGen in DmaVirtDevice. Gabe Black 2021-09-21 17:12:00 -07:00
  • 74c246d15b mem: Add a translation generator function to EmulationPageTable. Gabe Black 2021-09-21 17:10:49 -07:00
  • fbe002bf12 arch: Make the MMU ranged translateFunction pure virtual. Gabe Black 2021-09-21 14:42:52 -07:00
  • 7155b8ba1e mem: Use the MMU's translation generator in translating proxies. Gabe Black 2021-09-20 21:37:40 -07:00
  • 1f9fc43e72 arch: Add a MMUTranslationGen class to the BaseMMU. Gabe Black 2021-09-20 21:37:24 -07:00
  • 3b48aa4d4c tests: fix bug in weekly regression Matt Sinclair 2021-10-21 16:54:42 -05:00
  • d2a684c5bd tests: Add a test for forking and switching cpus Austin Harris 2021-09-16 14:11:27 -05:00
  • 309e48c0cb arch-arm: Add fchmodat implementation to the Syscall Table Giacomo Travaglini 2021-10-13 09:22:20 +01:00
  • 16253e494e arch: Fixed Packed register view for VecPredReg Giacomo Travaglini 2021-10-21 09:56:23 +01:00
  • 645e315180 scons: Copy the value of "tags" before adding "add_tags" to it. Gabe Black 2021-10-20 09:06:24 -07:00
  • 535963c2d0 arch-arm: Fix codying style in TableWalker descriptors Giacomo Travaglini 2021-08-04 18:25:35 +01:00
  • 9f73802ea2 arch: Correct the direction of the arch->gem5 lib tag implication. Gabe Black 2021-10-20 06:58:34 -07:00
  • 741cb727ca scons: Resolve tags for source files as well as for filters. Gabe Black 2021-10-20 07:02:43 -07:00
  • 5eb4f5fe11 configs: Breakup GPU_VIPER create_system code Matthew Poremba 2021-10-20 12:52:42 -05:00
  • 2f88afdc52 sim-se: Implement fchmodat syscall Giacomo Travaglini 2021-10-13 09:03:02 +01:00
  • 847f642f0e arch-arm: Add TxSZ to PageTableOps::index Giacomo Travaglini 2021-09-08 16:17:46 +01:00
  • 1b6c050ebf arch-arm, dev-arm: Use PageTableOps in Arm TableWalker Giacomo Travaglini 2021-08-02 18:06:51 +01:00
  • 526b03407a tests: Add RISC-V Ruby boot tests Jason Lowe-Power 2021-10-12 07:31:34 -07:00
  • 5dc776399d python,configs: Add Ruby support to RISC-V board Jason Lowe-Power 2021-10-11 16:36:35 -07:00
  • 14aece4d8f python: Generalize ruby components in library Jason Lowe-Power 2021-10-11 16:34:03 -07:00
  • 3e32fd3b33 mem-ruby: Add RISC-V atomic support to Ruby Jason Lowe-Power 2021-10-11 16:30:09 -07:00
  • 2af3045e17 cpu: Move FuncUnit.py, its .cc and StaticInstFlags.py above Return. Gabe Black 2021-10-20 09:52:40 -07:00
  • f65a704296 arch: Only build GPU switching headers if building the GPU. Gabe Black 2021-10-20 05:41:20 -07:00
  • 8f33e9e34e python: Updates to improve debugging output Jason Lowe-Power 2021-10-19 10:50:07 -07:00
  • 56494ed699 python: Add check to SimObject for __init__ Jason Lowe-Power 2021-10-13 11:06:36 -07:00
  • 6d336c5635 arch-arm: Add futimesat implementation to the Syscall Table Giacomo Travaglini 2021-09-28 09:41:38 +01:00
  • 1c708f76f1 sim-se: Implement futimesat syscall Giacomo Travaglini 2021-09-28 09:39:21 +01:00
  • 4808a22dae arch-arm: Add utimes implementation to the Syscall Table Giacomo Travaglini 2021-09-28 09:15:09 +01:00
  • 3627659ccb arch-arm: Add mknodat implementation to the Syscall Table Giacomo Travaglini 2021-09-28 09:09:54 +01:00
  • b4f73b8965 sim-se: Implement mknodat syscall Giacomo Travaglini 2021-09-28 09:01:14 +01:00
  • a680b98eaf configs: Assign the host gid to the Process.gid in SE configs Giacomo Travaglini 2021-10-19 11:40:08 +01:00
  • 7eb8fb927f python: remove SimObject children on NULL assignment Nathanael Premillieu 2021-10-04 16:46:46 +02:00
  • 66a056b828 tests: add HACC to weekly regression Matt Sinclair 2021-10-17 19:08:49 -05:00
  • 73025695c7 scons: Use tags to gate ISA files and not env['TARGET_ISA']. Gabe Black 2021-09-14 18:01:14 -07:00
  • 9f92ec90ba configs,dev: Rename the riscv version of VirtIOMMIO with a Riscv prefix. Gabe Black 2021-09-14 17:43:28 -07:00
  • 0d1c80ccdb configs,tests: Add Ubuntu boot example for the gem5 library Bobby R. Bruce 2021-09-23 13:57:09 -07:00
  • 06401fa80f configs,tests: Add "Hello world" example for the gem5 library Bobby R. Bruce 2021-09-23 12:12:23 -07:00
  • 305a81aae7 arch: Consolidate common debug flags. Gabe Black 2021-09-14 03:58:46 -07:00
  • 04c9473551 scons: Make debug flags respect tags. Gabe Black 2021-09-14 03:29:38 -07:00
  • 038bf7075a scons: Use unions to prevent debug flag destruction. Gabe Black 2021-08-30 22:43:23 -07:00
  • 1b2083fc53 arch-arm: Add mknod implementation to the Syscall Table Giacomo Travaglini 2021-09-27 19:47:48 +01:00
  • dcf4e11a15 arch-arm: Add mkdirat implementation to the Syscall Table Giacomo Travaglini 2021-09-27 18:11:21 +01:00
  • a82146153a sim-se: Implement mkdirat syscall Giacomo Travaglini 2021-09-27 18:09:44 +01:00
  • 7ccb819665 tests: simplify weekly regression Matt Sinclair 2021-10-16 17:15:38 -05:00
  • a1554370ff cpu: Eliminate the unused hasBranchTarget method in StaticInst. Gabe Black 2021-10-08 03:31:42 -07:00
  • 6c9792d333 arch-arm: EL2&0 invalidations do not depend on VMID Giacomo Travaglini 2021-09-14 15:44:01 +01:00
  • 655349a9ca arch-arm: Use EL2&0 regime for invalidation only if EL2 enabled Giacomo Travaglini 2021-09-14 15:41:16 +01:00
  • f49a15e00f arch-arm: Define a Lookup structure to simplify TLB code Giacomo Travaglini 2021-08-05 10:52:49 +01:00
  • b29349671c arch-arm: EL2/EL3 TLB invalidations should ignore the ASID Giacomo Travaglini 2021-09-04 15:53:27 +01:00
  • 8fe7a740e3 arch-arm: Do not always print 0 stats in ArmTLB Giacomo Travaglini 2021-09-09 11:37:21 +01:00
  • 118677218d mem-ruby: fix typo in GPU VIPER TCC comment Matt Sinclair 2021-10-16 16:27:56 -05:00
  • 7455087ca4 python: Improve the print statements in downloader.py Bobby R. Bruce 2021-10-07 15:20:08 -07:00
  • a3f6cac410 python: Set a default resource dir to download to Bobby R. Bruce 2021-10-07 15:02:41 -07:00
  • 5c8c981cdd arch-sparc: Fix the build for SPARC. Gabe Black 2021-10-14 22:09:18 -07:00
  • 18cb3af215 cpu,tests: Replace the deprecated Stats namespace with statistics. Gabe Black 2021-10-14 22:10:46 -07:00
  • c3e98d86a2 cpu: Updating stats for GUPSGen Mahyar Samani 2021-10-13 15:50:07 -07:00
  • a2f1400e06 mem: Add a translation gen helper class. Gabe Black 2021-09-20 21:03:46 -07:00
  • 1dbc78e611 python: Update the gem5 lib downloader 'is_zipped' checker Bobby R. Bruce 2021-10-06 16:49:03 -07:00
  • 1e7a312e03 python: Rename 'artifact' to 'resources' in downloader Bobby R. Bruce 2021-10-06 16:33:45 -07:00
  • f5ea0fa3f8 python: Update gem5 lib downloader for new url_base field Bobby R. Bruce 2021-10-06 16:24:21 -07:00
  • 468765e14e tests: Re-enable 'Hello World' 32-bit tests Bobby R. Bruce 2021-10-13 17:05:48 -07:00
  • 2887a996e1 fastmodel: Don't try to "staticify" system libraries. Gabe Black 2021-10-13 23:25:01 -07:00
  • 133997d515 arch-arm: Add chdir implementation to the Syscall Table Giacomo Travaglini 2021-10-13 16:40:41 +01:00
  • 54d48c0244 sim-se, kern: Add flags parameter to unlinkat Giacomo Travaglini 2021-10-13 13:28:46 +01:00
  • 65ef21a308 sim-se: Define rmdirImpl helper Giacomo Travaglini 2021-10-11 10:13:38 +01:00
  • bad6fa679d scons: Don't explicitly list include dependencies for the cxx config. Gabe Black 2021-08-15 00:50:19 -07:00
  • 16c49af22e tests: convert all nightly GPU tests from GUID to GID Matt Sinclair 2021-10-13 12:01:58 -05:00
  • 7290bf52f3 mem: Replace SatCounter with SatCounter8 in the SHiP replacement policy. Gabe Black 2021-10-10 16:42:17 -07:00
  • 66db68359a tests: Fix the nightly GPU tests Bobby R. Bruce 2021-10-13 11:11:11 -07:00
  • eb25cbd9d7 cpu: Adding GUPSGen ClockedObject. Mahyar Samani 2021-03-04 17:53:18 -08:00
  • 86e3e52857 tests: add additional space in weekly DNNMark tests Matt Sinclair 2021-10-12 15:05:10 -05:00
  • 6133ba5f6b tests: fix LULESH weekly regression command Matt Sinclair 2021-10-01 22:28:31 -05:00
  • 1ee4c4ce43 arch-power: Replace the Loader namespace with loader. Gabe Black 2021-10-07 17:31:08 -07:00
  • 8304ed1967 base,arch-arm: Replace Stats namespace with statistics. Gabe Black 2021-10-07 17:31:51 -07:00
  • 4fe9af8d17 mem: Stop using SlavePort as a base class. Gabe Black 2021-10-08 14:39:30 -07:00
  • 2d9e742540 cpu: Stop excluding the protobuf tracer for x86. Gabe Black 2021-09-14 03:24:17 -07:00
  • ee10eb1cc6 scons: Make the SimObject list from the 'gem5 lib' tag. Gabe Black 2021-09-14 03:21:24 -07:00
  • ad944025ab scons,arch: Make the gem5 lib tag imply the current arch tag. Gabe Black 2021-09-14 02:44:35 -07:00
  • 79953cf973 scons: Add tag support to ISADesc. Gabe Black 2021-09-14 02:44:16 -07:00
  • 29705f96ee scons: Add tag support to GdbXml. Gabe Black 2021-09-14 02:43:29 -07:00
  • 7260394d4b mem: Make ruby AbstractController compatible with XBar Giacomo Travaglini 2021-09-13 10:23:19 +01:00
  • bc1438414a sparc: Stop using fp_enable_check. Gabe Black 2021-07-25 02:29:45 -07:00
  • 645c6b3ceb sparc: Stop special casing FP enable checks for full system. Gabe Black 2021-07-25 01:44:38 -07:00
  • 7d92144e1b arch,sparc: Get rid of the unused checkVecEnableFault mechanism. Gabe Black 2021-07-25 01:29:48 -07:00
  • 851e543b2f misc: Using OS::off_t in syscall signature Giacomo Travaglini 2021-10-12 18:49:59 +01:00
  • 37495f8823 misc: Using OS::size_t in syscall signature Giacomo Travaglini 2021-10-12 17:00:16 +01:00
  • 43910b5312 arch-arm: Add ftruncate implementation to the Syscall Table Giacomo Travaglini 2021-10-12 18:34:35 +01:00
  • 2644cc3cac arch-arm: Add sendto and recvfrom implementations to the Syscall Table Giacomo Travaglini 2021-10-12 18:08:31 +01:00
  • 058e4699d8 python: Fix L1 data cache size in cache components Austin Harris 2021-10-12 13:22:01 -05:00