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python: Fix L1 data cache size in cache components

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Change-Id: I96119e2a002de3904e87625a3de89abb3cc724a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51452
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Austin Harris
2021-10-12 13:22:01 -05:00
parent af73f13ac2
commit 058e4699d8
2 changed files with 2 additions and 2 deletions
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2
src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
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@@ -102,7 +102,7 @@ class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy):
]
self.l1dcaches = [
L1DCache(size=self._l1i_size)
L1DCache(size=self._l1d_size)
for i in range(board.get_processor().get_num_cores())
]
# ITLB Page walk caches

2
src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
View File

@@ -127,7 +127,7 @@ class PrivateL1PrivateL2CacheHierarchy(
for i in range(board.get_processor().get_num_cores())
]
self.l1dcaches = [
L1DCache(size=self._l1i_size)
L1DCache(size=self._l1d_size)
for i in range(board.get_processor().get_num_cores())
]
self.l2buses = [