diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
index 03150dabc7..ce04f46ecc 100644
--- a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
+++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
@@ -102,7 +102,7 @@ class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy):
         ]
 
         self.l1dcaches = [
-            L1DCache(size=self._l1i_size)
+            L1DCache(size=self._l1d_size)
             for i in range(board.get_processor().get_num_cores())
         ]
         # ITLB Page walk caches
diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
index eb4dae18be..cd55c6e5c4 100644
--- a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
+++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
@@ -127,7 +127,7 @@ class PrivateL1PrivateL2CacheHierarchy(
             for i in range(board.get_processor().get_num_cores())
         ]
         self.l1dcaches = [
-            L1DCache(size=self._l1i_size)
+            L1DCache(size=self._l1d_size)
             for i in range(board.get_processor().get_num_cores())
         ]
         self.l2buses = [