configs,dev: Rename the riscv version of VirtIOMMIO with a Riscv prefix.

This device and the file it's in have the same name as one already
defined by arm. This is basically ok when those are mutually exclusive,
but can't coexist when both ISAs can be included at the same time. This
is because the file name would put them both under
m5.objects.VirtIOMMIO, and the name of the object itself would conflict
when importing * from m5.objects.

Change-Id: I558676b7d64cc68adb2d81b070a1816aa0bea6ba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50335
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

configs/example/riscv/fs_linux.py

@@ -170,7 +170,7 @@ system.platform.clint.int_pin = system.platform.rtc.int_pin
 if args.disk_image:
     image = CowDiskImage(child=RawDiskImage(read_only=True), read_only=False)
     image.child.image_file = mdesc.disks()[0]
-    system.platform.disk = MmioVirtIO(
+    system.platform.disk = RiscvMmioVirtIO(
         vio=VirtIOBlock(image=image),
         interrupt_id=0x8,
         pio_size=4096,

src/dev/riscv/RiscvVirtIOMMIO.py

@@ -42,10 +42,10 @@ from m5.util.fdthelper import *
 from m5.objects.PlicDevice import PlicIntDevice
 from m5.objects.VirtIO import VirtIODummyDevice
 
-class MmioVirtIO(PlicIntDevice):
-    type = 'MmioVirtIO'
+class RiscvMmioVirtIO(PlicIntDevice):
+    type = 'RiscvMmioVirtIO'
     cxx_header = 'dev/riscv/vio_mmio.hh'
-    cxx_class = 'gem5::MmioVirtIO'
+    cxx_class = 'gem5::RiscvISA::MmioVirtIO'
     vio = Param.VirtIODeviceBase(VirtIODummyDevice(), "VirtIO device")
 
     def generateDeviceTree(self, state):

src/dev/riscv/SConscript

@@ -35,7 +35,7 @@ if env['TARGET_ISA'] == 'riscv':
     SimObject('PlicDevice.py')
     SimObject('Plic.py')
     SimObject('RTC.py')
-    SimObject('VirtIOMMIO.py')
+    SimObject('RiscvVirtIOMMIO.py')
 
     DebugFlag('Clint')
     DebugFlag('Plic')

src/dev/riscv/vio_mmio.cc

@@ -41,12 +41,15 @@
 #include "debug/VirtIOMMIO.hh"
 #include "dev/riscv/hifive.hh"
 #include "mem/packet_access.hh"
-#include "params/MmioVirtIO.hh"
+#include "params/RiscvMmioVirtIO.hh"
 
 namespace gem5
 {
 
-MmioVirtIO::MmioVirtIO(const MmioVirtIOParams &params)
+namespace RiscvISA
+{
+
+MmioVirtIO::MmioVirtIO(const RiscvMmioVirtIOParams &params)
     : PlicIntDevice(params),
       hostFeaturesSelect(0), guestFeaturesSelect(0), pageSize(0),
       interruptStatus(0), vio(*params.vio)
@@ -274,4 +277,6 @@ MmioVirtIO::setInterrupts(uint32_t value)
     }
 }
 
+} // namespace RiscvISA
+
 } // namespace gem5

src/dev/riscv/vio_mmio.hh

@@ -46,12 +46,15 @@
 namespace gem5
 {
 
-struct MmioVirtIOParams;
+struct RiscvMmioVirtIOParams;
+
+namespace RiscvISA
+{
 
 class MmioVirtIO : public PlicIntDevice
 {
   public:
-    MmioVirtIO(const MmioVirtIOParams &params);
+    MmioVirtIO(const RiscvMmioVirtIOParams &params);
     virtual ~MmioVirtIO();
 
   protected: // BasicPioDevice
@@ -113,6 +116,8 @@ class MmioVirtIO : public PlicIntDevice
     VirtIODeviceBase &vio;
 };
 
+} // namespace RiscvISA
+
 } // namespace gem5
 
 #endif // __DEV_ARM_VIO_MMIO_HH__

src/python/gem5/components/boards/riscv_board.py

@@ -50,7 +50,7 @@ from m5.objects import (
     HiFive,
     CowDiskImage,
     RawDiskImage,
-    MmioVirtIO,
+    RiscvMmioVirtIO,
     VirtIOBlock,
     Frequency,
     Port,
@@ -110,7 +110,7 @@ class RiscvBoard(SimpleBoard):
         self.iobus = IOXBar()
 
         # The virtio disk
-        self.disk = MmioVirtIO(
+        self.disk = RiscvMmioVirtIO(
             vio=VirtIOBlock(),
             interrupt_id=0x8,
             pio_size=4096,