tests: Add RISC-V Ruby boot tests

Change-Id: I6a173dcef974fef726991bf3db8b7355838e2d04
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51450
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

tests/gem5/configs/riscv_boot_exit_run.py

@@ -36,6 +36,7 @@ Characteristics
 import m5
 from m5.objects import Root
 
+from gem5.components.boards.riscv_board import RiscvBoard
 from gem5.components.memory.single_channel import SingleChannelDDR3_1600
 from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.processors.cpu_types import CPUTypes
@@ -66,6 +67,15 @@ parser.add_argument(
     help="The CPU type.",
 )
 
+parser.add_argument(
+    "-m",
+    "--mem-system",
+    type=str,
+    choices=("classic", "mi_example",),
+    required=True,
+    help="The memory system.",
+)
+
 parser.add_argument(
     "-t",
     "--tick-exit",
@@ -94,15 +104,24 @@ args = parser.parse_args()
 # Run a check to ensure the right version of gem5 is being used.
 requires(isa_required=ISA.RISCV)
 
-from gem5.components.cachehierarchies.classic.\
-    private_l1_private_l2_cache_hierarchy import \
-        PrivateL1PrivateL2CacheHierarchy
-from gem5.components.boards.riscv_board import RiscvBoard
+if args.mem_system == "classic":
+    from gem5.components.cachehierarchies.classic.\
+        private_l1_private_l2_cache_hierarchy import \
+            PrivateL1PrivateL2CacheHierarchy
 
-# Setup the cache hierarchy.
-cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
-    l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
-)
+    # Setup the cache hierarchy.
+    cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
+        l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
+    )
+elif args.mem_system == "mi_example":
+    from gem5.components.cachehierarchies.ruby.\
+        mi_example_cache_hierarchy import \
+            MIExampleCacheHierarchy
+
+    # Setup the cache hierarchy.
+    cache_hierarchy = MIExampleCacheHierarchy(
+        size="32KiB", assoc=8
+    )
 
 # Setup the system memory.
 memory = SingleChannelDDR3_1600()

tests/gem5/riscv-boot-tests/test_linux_boot.py

@@ -37,10 +37,12 @@ else:
 def test_boot(
     cpu: str,
     num_cpus: int,
+    cache_type: str,
     to_tick: int,
     length: str,
 ):
-    name = "{}-cpu_{}-cores_riscv-boot-test_to-tick".format(cpu, str(num_cpus))
+    name = "{}-cpu_{}-{}-cores_riscv-boot-test_to-tick".format(
+        cpu, str(num_cpus), cache_type)
 
     verifiers = []
     exit_regex = re.compile(
@@ -66,6 +68,8 @@ def test_boot(
             cpu,
             "--num-cpus",
             str(num_cpus),
+            "--mem-system",
+            cache_type,
             "--tick-exit",
             str(to_tick),
             "--override-download",
@@ -83,6 +87,7 @@ def test_boot(
 test_boot(
     cpu="atomic",
     num_cpus=1,
+    cache_type="classic",
     to_tick=10000000000,  # Simulates 1/100th of a second.
     length=constants.quick_tag,
 )
@@ -90,6 +95,15 @@ test_boot(
 test_boot(
     cpu="timing",
     num_cpus=1,
+    cache_type="classic",
+    to_tick=10000000000,
+    length=constants.quick_tag,
+)
+
+test_boot(
+    cpu="timing",
+    num_cpus=1,
+    cache_type="mi_example",
     to_tick=10000000000,
     length=constants.quick_tag,
 )
@@ -97,6 +111,7 @@ test_boot(
 test_boot(
     cpu="o3",
     num_cpus=1,
+    cache_type="classic",
     to_tick=10000000000,
     length=constants.quick_tag,
 )
@@ -104,6 +119,15 @@ test_boot(
 test_boot(
     cpu="timing",
     num_cpus=4,
+    cache_type="classic",
+    to_tick=10000000000,
+    length=constants.quick_tag,
+)
+
+test_boot(
+    cpu="timing",
+    num_cpus=4,
+    cache_type="mi_example",
     to_tick=10000000000,
     length=constants.quick_tag,
 )