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python,configs: Add Ruby support to RISC-V board

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Take out guards stopping the RISC-V board from being configured with
Ruby and update the I/O config with a check for Ruby. Also, add a
comment in the example file that Ruby is now supported.

Change-Id: Icb6e2e2d2afa377669cc2549d66197e2332f4ed9
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51449
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Jason Lowe-Power
2021-10-11 16:36:35 -07:00
committed by Jason Lowe-Power
parent 14aece4d8f
commit 5dc776399d
2 changed files with 22 additions and 17 deletions
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4
configs/example/components-library/riscv_fs.py
View File

@@ -57,7 +57,9 @@ from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierar
PrivateL1PrivateL2CacheHierarchy,
)
# Setup the cache hierarchy. PrivateL1PrivateL2 and NoCache have been tested.
# Setup the cache hierarchy.
# For classic, PrivateL1PrivateL2 and NoCache have been tested.
# For Ruby, MESI_Two_Level and MI_example have been tested.
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
)

35
src/python/gem5/components/boards/riscv_board.py
View File

@@ -89,9 +89,6 @@ class RiscvBoard(SimpleBoard):
requires(isa_required=ISA.RISCV)
if cache_hierarchy.is_ruby():
raise EnvironmentError("RiscvBoard is not compatible with Ruby")
self.workload = RiscvLinux()
# Contains a CLINT, PLIC, UART, and some functions for the dtb, etc.
@@ -124,20 +121,26 @@ class RiscvBoard(SimpleBoard):
def _setup_io_devices(self) -> None:
"""Connect the I/O devices to the I/O bus"""
for device in self._off_chip_devices:
device.pio = self.iobus.mem_side_ports
for device in self._on_chip_devices:
device.pio = self.get_cache_hierarchy().get_mem_side_port()
self.bridge = Bridge(delay="10ns")
self.bridge.mem_side_port = self.iobus.cpu_side_ports
self.bridge.cpu_side_port = (
self.get_cache_hierarchy().get_mem_side_port()
)
self.bridge.ranges = [
AddrRange(dev.pio_addr, size=dev.pio_size)
for dev in self._off_chip_devices
]
if self.get_cache_hierarchy().is_ruby():
for device in self._off_chip_devices + self._on_chip_devices:
device.pio = self.iobus.mem_side_ports
else:
for device in self._off_chip_devices:
device.pio = self.iobus.mem_side_ports
for device in self._on_chip_devices:
device.pio = self.get_cache_hierarchy().get_mem_side_port()
self.bridge = Bridge(delay="10ns")
self.bridge.mem_side_port = self.iobus.cpu_side_ports
self.bridge.cpu_side_port = (
self.get_cache_hierarchy().get_mem_side_port()
)
self.bridge.ranges = [
AddrRange(dev.pio_addr, size=dev.pio_size)
for dev in self._off_chip_devices
]
def _setup_pma(self) -> None:
"""Set the PMA devices on each core"""