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python: Generalize ruby components in library

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The Ruby protocols in the components library had some special cases for
x86 that ended up breaking other ISAs (RISC-V in my testing). This
change generalizes those scripts slightly so they will work with both
x86 and RISC-V

Change-Id: I32afa3dc6131ab3751150746f0b2c63ba4a168c6
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51448
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Jason Lowe-Power
2021-10-11 16:34:03 -07:00
committed by Jason Lowe-Power
parent 3e32fd3b33
commit 14aece4d8f
2 changed files with 14 additions and 28 deletions
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21
src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
View File

@@ -110,21 +110,14 @@ class MESITwoLevelCacheHierarchy(
board.get_clock_domain(),
)
cache.sequencer = RubySequencer(
version=i,
dcache=cache.L1Dcache,
clk_domain=cache.clk_domain,
)
if board.has_io_bus():
cache.sequencer = RubySequencer(
version=i,
dcache=cache.L1Dcache,
clk_domain=cache.clk_domain,
pio_request_port=board.get_io_bus().cpu_side_ports,
mem_request_port=board.get_io_bus().cpu_side_ports,
pio_response_port=board.get_io_bus().mem_side_ports,
)
else:
cache.sequencer = RubySequencer(
version=i,
dcache=cache.L1Dcache,
clk_domain=cache.clk_domain,
)
cache.sequencer.connectIOPorts(board.get_io_bus())
cache.ruby_system = self.ruby_system

21
src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
View File

@@ -97,21 +97,14 @@ class MIExampleCacheHierarchy(AbstractRubyCacheHierarchy):
clk_domain=board.get_clock_domain(),
)
cache.sequencer = RubySequencer(
version=i,
dcache=cache.cacheMemory,
clk_domain=cache.clk_domain,
)
if board.has_io_bus():
cache.sequencer = RubySequencer(
version=i,
dcache=cache.cacheMemory,
clk_domain=cache.clk_domain,
pio_request_port=board.get_io_bus().cpu_side_ports,
mem_request_port=board.get_io_bus().cpu_side_ports,
pio_response_port=board.get_io_bus().mem_side_ports,
)
else:
cache.sequencer = RubySequencer(
version=i,
dcache=cache.L1Dcache,
clk_domain=cache.clk_domain,
)
cache.sequencer.connectIOPorts(board.get_io_bus())
cache.ruby_system = self.ruby_system