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arch-sparc: Fix the build for SPARC.

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The fp_enable_check mechanism was removed recently, but the removal was
only partial for SPARC which broke its build. This change completes the
removal by finishing the necessary code substitutions.

Change-Id: I3a6a6cd679b08556e5e4a2a2c4e98168ee7fe1fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51673
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-14 22:09:18 -07:00
parent 18cb3af215
commit 5c8c981cdd
1 changed files with 5 additions and 5 deletions
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10
src/arch/sparc/isa/decoder.isa
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@@ -344,7 +344,7 @@ decode OP default Unknown::unknown()
0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
// 0x12 should cause an illegal instruction exception
0x13: NoPriv::rdgsr({{
fault = checkFpEnableFault(xc);
fault = checkFpEnabled(Pstate, Fprs);
if (fault)
return fault;
Rd = Gsr;
@@ -1260,11 +1260,11 @@ decode OP default Unknown::unknown()
format Trap {
0x20: Loadf::ldf({{Frds_uw = Mem_uw;}});
0x21: decode RD {
0x0: Load::ldfsr({{fault = checkFpEnableFault(xc);
0x0: Load::ldfsr({{fault = checkFpEnabled(Pstate, Fprs);
if (fault)
return fault;
Fsr = Mem_uw | Fsr<63:32>;}});
0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc);
0x1: Load::ldxfsr({{fault = checkFpEnabled(Pstate, Fprs);
if (fault)
return fault;
Fsr = Mem_udw;}});
@@ -1274,11 +1274,11 @@ decode OP default Unknown::unknown()
0x23: Loadf::lddf({{Frd_udw = Mem_udw;}});
0x24: Storef::stf({{Mem_uw = Frds_uw;}});
0x25: decode RD {
0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc);
0x0: StoreFsr::stfsr({{fault = checkFpEnabled(Pstate, Fprs);
if (fault)
return fault;
Mem_uw = Fsr<31:0>;}});
0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc);
0x1: StoreFsr::stxfsr({{fault = checkFpEnabled(Pstate, Fprs);
if (fault)
return fault;
Mem_udw = Fsr;}});