arch: Consolidate common debug flags.

Consolidate debug flags which are defined separately in multiple ISAs in
arch/SConscript instead. This will prevent conflicts when more than one
ISA can be compiled at a time.

Change-Id: I70862c403d19f04bbcbabd74dd751ca92d1ed942
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50334
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/SConscript

@@ -225,3 +225,7 @@ DebugFlag('CCRegs')
 DebugFlag('MiscRegs')
 CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'VecRegs', 'VecPredRegs',
                             'CCRegs', 'MiscRegs' ])
+
+DebugFlag('Decoder', "Decoder debug output")
+DebugFlag('Faults', "Information about faults, exceptions, interrupts, etc")
+DebugFlag('TLBVerbose')

src/arch/arm/SConscript

@@ -111,10 +111,7 @@ if env['TARGET_ISA'] == 'arm':
     DebugFlag('Arm')
     DebugFlag('ArmTme', 'Transactional Memory Extension')
     DebugFlag('Semihosting')
-    DebugFlag('Decoder', "Instructions returned by the predecoder")
-    DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
     DebugFlag('PMUVerbose', "Performance Monitor")
-    DebugFlag('TLBVerbose')
 
     # Add files generated by the ISA description.
     ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6)

src/arch/riscv/SConscript

@@ -71,7 +71,6 @@ if env['TARGET_ISA'] == 'riscv':
     SimObject('RiscvTLB.py')
 
     DebugFlag('RiscvMisc')
-    DebugFlag('TLBVerbose')
     DebugFlag('PMP')
 
     # Add in files generated by the ISA description.

src/arch/x86/SConscript

@@ -72,9 +72,7 @@ SimObject('X86MMU.py')
 SimObject('X86NativeTrace.py')
 SimObject('X86TLB.py')
 
-DebugFlag('Faults', "Trace all faults/exceptions/traps")
 DebugFlag('LocalApic', "Local APIC debugging")
-DebugFlag('Decoder', "Decoder debug output")
 DebugFlag('X86', "Generic X86 ISA debugging")
 DebugFlag('ACPI', "ACPI debugging")