diff --git a/src/arch/SConscript b/src/arch/SConscript
index ecc0ca55d4..4922bda64c 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -225,3 +225,7 @@ DebugFlag('CCRegs')
 DebugFlag('MiscRegs')
 CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'VecRegs', 'VecPredRegs',
                             'CCRegs', 'MiscRegs' ])
+
+DebugFlag('Decoder', "Decoder debug output")
+DebugFlag('Faults', "Information about faults, exceptions, interrupts, etc")
+DebugFlag('TLBVerbose')
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index fbf4a44023..c4a8b9ec05 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -111,10 +111,7 @@ if env['TARGET_ISA'] == 'arm':
     DebugFlag('Arm')
     DebugFlag('ArmTme', 'Transactional Memory Extension')
     DebugFlag('Semihosting')
-    DebugFlag('Decoder', "Instructions returned by the predecoder")
-    DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
     DebugFlag('PMUVerbose', "Performance Monitor")
-    DebugFlag('TLBVerbose')
 
     # Add files generated by the ISA description.
     ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6)
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 4861c69d6d..b9a0135dcf 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -71,7 +71,6 @@ if env['TARGET_ISA'] == 'riscv':
     SimObject('RiscvTLB.py')
 
     DebugFlag('RiscvMisc')
-    DebugFlag('TLBVerbose')
     DebugFlag('PMP')
 
     # Add in files generated by the ISA description.
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 6c9fdfa8a6..1252116269 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -72,9 +72,7 @@ SimObject('X86MMU.py')
 SimObject('X86NativeTrace.py')
 SimObject('X86TLB.py')
 
-DebugFlag('Faults', "Trace all faults/exceptions/traps")
 DebugFlag('LocalApic', "Local APIC debugging")
-DebugFlag('Decoder', "Decoder debug output")
 DebugFlag('X86', "Generic X86 ISA debugging")
 DebugFlag('ACPI', "ACPI debugging")