The GITS_CTLR.quiescent bit is used by priviledged sw to check when the
ITS has finished draining its state (all pending translations/table
walks have ended) once it has been disabled (by setting the
GITS_CTLR.enable bit to 0).
This patch is modelling this behaviour by
* Changing the reset state to enable=0, quiescent=1
* Making the GITS_CTLR.quiescent bit RO
* Updating the bit once a new translation/command is being processed
(quiescent=0) and when there are no pending translation/commands
(quiescent=1)
Change-Id: I7cfe94b25d603400364b1cdfc2d2397acf5dfad8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20257
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
(1) Two new options are added to fs_bigLITTLE.py:
- "root": disk/partition containing the rootfs (def. "/dev/vda1")
- "machine-type": hardware platform class (def. "VExpress_GEM5_V1")
+ Accepts platform classes from PlatformConfig
(2) Default kernel is not available in public uploads, force the user
to provide its own kernel instead of crashing.
Change-Id: I88283ae12cd7289e15b9277ea2cc382e9136f11c
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20148
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The previous implementation left the registers unmodified which is
technically correct since there is no defined behavior in that case or
a fault to raise. That would make what happened when the following code
consumed the result unpredictable because it would depend on what junk
values were left in the registers. This was originally not a problem
since the space of supported functions were tightly packed, but someone
added a new function with a gap without adjusting this behavior.
This change makes CPUID zero out RAX, RBX, RCX, and RDX when it fails.
That should be more predictable and cause less flakey failures.
Change-Id: If6ffb17c2969d34aff1600c0ffc32333d0b9be44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20168
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This hook will let them implement whatever additional behavior is
necessary for when the clock changes.
An alternative design for this might have made the "update" function
virtual, and required anyone overriding it to call into the base class.
I think that would be an inferior design for two reasons. First, the
subclass author might forget to call update. Second, while it might
*seem* like this would have some performance benefit since you wouldn't
call into the virtual function and then call update, incurring the
function call overhead twice, you're going to call into update once
regardless, and then you're either going to call the virtual funciton
which does nothing (the norm) or does something. In either case you
call the same functions the same number of times.
There may be a slight penalty in code size since the call to update
may be inlined in the call sights before the virtual function, and
there will almost certainly be more of those than there would be
implementations of the virtual function, but that should be negligable
when compared to gem5's size as a whole.
Change-Id: Id25a5359f2b1f7e42c6d1dcbc70a37d3ce092d38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20089
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Adding LD/ST/SWP family of instructions, LD/ST include a set of
operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN
This commit includes:
+ Instruction decode
+ Instruction functional code
+ New set of skeletons for Ex/Com/Ini/Constructor and declaration.
Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19812
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
The PCI host has an interrupt-map property which only works for a fixed
setup of parent/child interrupt/address cells, which currently overlaps
with GICv2.
We want to make this flexible, so that the interrupt-map doesn't break
if we change the interrupt/address-cells value, and the patch is aiming
in that direction. This is also needed for GICv3 DTB autogeneration,
since it is using different values than GICv2.
Change-Id: If1c661ddcbc0c277c9d6b0e44a0fd3fe2427618c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20052
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The X86 local APIC doesn't actually use the pio_addr set in the config
and instead computes what address it will respond to based on the
initial ID of the CPU it's attached to. gem5's BasicPioDevice, which
the X86LocalApic class inherits from, does not provide a default value
for that parameter and will complain if *something* isn't set. The
value used, 0x2000000000000000, is a dummy value which is the base of
the region of the physical address space set aside for messages to
local APICs from the CPU and from other local APICs.
Also, the clock for the local APIC's timer is defined to be the bus
clock. The assumption seems to be that this has a 16:1 ratio with the
CPU clock, and I vaguely remember finding that that was more or less
unofficially true, even if it isn't necessary stringently defined to
be that.
Since we were already just assuming that that ratio was correct and
always setting up the local APICs clock that way, we can do that in
the X86LocalApic class definition and remove some special x86 specific
setup that we'd otherwise need for the x86 version of the Interrupt
class. If that's not correct, it can still be overridden somewhere else
in the config.
Change-Id: I50e84f899f44b1191c2ad79d05803b44f07001f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19968
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gem5Fixture is used to define a fixture for building the gem5
binary. Most tests are expected to define their own Gem5Fixture,
however, as some might depend on the same binary (e.g.,
./build/ARM/gem5.opt), they will try to re-define a fixture for the
same target. This patchset changes Gem5Fixture to derive from
UniqueFixture.
In addition, this patchset changes the way global fixtures are
discovered to work with the new Gem5Fixture class. Instead of
enumerating them when test definitions are loaded, we do so after the
tests have been filtered according to specified tags (e.g., include
opt variant, exclude fast, debug variants).
Change-Id: Ie868a7e18ef6c3271f3c8a658229657cd43997cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19251
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This changeset adds a test to check the redirection features
added in faux-filesystem changeset. The test contains a
"chdir" system call to "/proc" which should be redirected to
"$(gem5-dir)/m5out/fs/proc" (as specified by the config files).
After "chdir", the test subsequently outputs the "/proc/cpuinfo"
file which should output a configuration of a fake cpu with
values set by a Python configuration file.
Note, the test will call "clone" once. To avoid a runtime error,
make sure that you run this test with "-n2" supplied to the
"config/example/se.py" script.
Change-Id: I505b046b7a4feddfa93a6ef0f0773ac43078cc94
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17112
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Fix problem with O3 and AMO instructions. At initial stages amo
instruction is considered a type of non-speculative store. After
the instruction has been commited and during the squash step,
acquire_release version of the AMO operation is considered speculative,
that differents results in an assert fault. This fix ensures that AMO
instructions are always considered non-speculative, during early stages
and during squas/removal of the instruction.
Change-Id: Ia0c5fbb9dc44a9991337b57eb759b1ed08e4149e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19815
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
In the current SMMUv3 model, multiple micro/mainTLB are present at the
device interface (SMMUv3SlaveInterface), caching translations specific
to a device.
Those distributed TLBs are checked for a translation before checking for
centralized TLBs (shared by devices), like the configuration cache, walk
cache etc. This means that if a hit in these TLBs occurs, there won't
be a need to enter configuration stage (which is where the STE and CD
are retrieved). So if we invalidate a cached configuration (in
ConfigCache), we need to invalidate those interface TLB entries as well,
otherwise in theory we will keep the same translation even after a
change in configuration tables.
Change-Id: I4aa36ba8392a530267517bef7562318b282bee25
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel van Tol <michiel.vantol@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19813
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
