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arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currEL

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Change-Id: I739a9be03ea5caa63540c62fd110eee86a058c4c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20252
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-08-16 14:20:50 +01:00
parent e97a1fe390
commit 20990ad5e9
7 changed files with 11 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/insts/static_inst.cc
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@@ -703,7 +703,7 @@ ArmStaticInst::checkAdvSIMDOrFPEnabled32(ThreadContext *tc,
const bool have_virtualization = ArmSystem::haveVirtualization(tc);
const bool have_security = ArmSystem::haveSecurity(tc);
const bool is_secure = inSecureState(tc);
const ExceptionLevel cur_el = opModeToEL(currOpMode(tc));
const ExceptionLevel cur_el = currEL(tc);
if (cur_el == EL0 && ELIs64(tc, EL1))
return checkFPAdvSIMDEnabled64(tc, cpsr, cpacr);

4
src/arch/arm/isa/insts/branch64.isa
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@@ -103,7 +103,7 @@ let {{
CPSR cpsr = Cpsr;
CPSR spsr = Spsr;
ExceptionLevel curr_el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
ExceptionLevel curr_el = currEL(cpsr);
switch (curr_el) {
case EL3:
newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL3);
@@ -145,7 +145,7 @@ let {{
NextAArch64 = !new_cpsr.width;
NextItState = itState(new_cpsr);
NPC = purifyTaggedAddr(newPc, xc->tcBase(),
opModeToEL((OperatingMode) (uint8_t) new_cpsr.mode));
currEL(new_cpsr));
LLSCLock = 0; // Clear exclusive monitor
SevMailbox = 1; //Set Event Register

2
src/arch/arm/isa/insts/str.isa
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@@ -114,7 +114,7 @@ let {{
auto tc = xc->tcBase();
if (badMode32(tc, static_cast<OperatingMode>(regMode))) {
return undefinedFault32(tc, opModeToEL(currOpMode(tc)));
return undefinedFault32(tc, currEL(tc));
}
CPSR cpsr = Cpsr;

4
src/arch/arm/miscregs.cc
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@@ -1117,7 +1117,7 @@ canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
switch (currEL(cpsr)) {
case EL0:
return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
miscRegInfo[reg][MISCREG_USR_NS_RD];
@@ -1140,7 +1140,7 @@ canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
// Check for SP_EL0 access while SPSEL == 0
if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
return false;
ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
ExceptionLevel el = currEL(cpsr);
if (reg == MISCREG_DAIF) {
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
if (el == EL0 && !sctlr.uma)

2
src/arch/arm/pmu.cc
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@@ -499,7 +499,7 @@ PMU::CounterState::isFiltered() const
const PMEVTYPER_t filter(this->filter);
const SCR scr(pmu.isa->readMiscRegNoEffect(MISCREG_SCR));
const CPSR cpsr(pmu.isa->readMiscRegNoEffect(MISCREG_CPSR));
const ExceptionLevel el(opModeToEL((OperatingMode)(uint8_t)cpsr.mode));
const ExceptionLevel el(currEL(cpsr));
const bool secure(inSecureState(scr, cpsr));
switch (el) {

2
src/arch/arm/tlb.cc
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@@ -1428,7 +1428,7 @@ TLB::tranTypeEL(CPSR cpsr, ArmTranslationType type)
case S1CTran:
case S1S2NsTran:
case HypMode:
return opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
return currEL(cpsr);
default:
panic("Unknown translation mode!\n");

8
src/arch/arm/utility.cc
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@@ -225,9 +225,7 @@ longDescFormatInUse(ThreadContext *tc)
RegVal
readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
{
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
const ExceptionLevel current_el =
opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
const ExceptionLevel current_el = currEL(tc);
const bool is_secure = isSecureBelowEL3(tc);
@@ -356,7 +354,7 @@ ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
bool
isBigEndian64(ThreadContext *tc)
{
switch (opModeToEL(currOpMode(tc))) {
switch (currEL(tc)) {
case EL3:
return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
case EL2:
@@ -820,7 +818,7 @@ decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
bool
SPAlignmentCheckEnabled(ThreadContext* tc)
{
switch (opModeToEL(currOpMode(tc))) {
switch (currEL(tc)) {
case EL3:
return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
case EL2: