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arch-arm: Replace direct use cpsr.el with currEL helper

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The patch is replacing it in places where the current EL could be using
AArch32, hence leading to an incorrect ExceptionLevel.

Change-Id: I99b75af2668f2c38fd88bec62e985ab7dbea80dc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20251
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-08-15 13:30:46 +01:00
parent 4ccb1ea710
commit e97a1fe390
4 changed files with 14 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/arm/faults.cc
View File

@@ -1014,7 +1014,7 @@ SupervisorTrap::routeToHyp(ThreadContext *tc) const
CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
return toHyp;
}
@@ -1536,7 +1536,7 @@ PCAlignmentFault::routeToHyp(ThreadContext *tc) const
CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
return toHyp;
}

16
src/arch/arm/insts/static_inst.cc
View File

@@ -686,7 +686,7 @@ Fault
ArmStaticInst::checkFPAdvSIMDEnabled64(ThreadContext *tc,
CPSR cpsr, CPACR cpacr) const
{
const ExceptionLevel el = (ExceptionLevel) (uint8_t)cpsr.el;
const ExceptionLevel el = currEL(tc);
if ((el == EL0 && cpacr.fpen != 0x3) ||
(el == EL1 && !(cpacr.fpen & 0x1)))
return advSIMDFPAccessTrap64(EL1);
@@ -876,19 +876,21 @@ ArmStaticInst::trapWFx(ThreadContext *tc,
bool isWfe) const
{
Fault fault = NoFault;
if (cpsr.el == EL0) {
ExceptionLevel curr_el = currEL(tc);
if (curr_el == EL0) {
fault = checkForWFxTrap32(tc, EL1, isWfe);
}
if ((fault == NoFault) &&
ArmSystem::haveEL(tc, EL2) && !inSecureState(scr, cpsr) &&
((cpsr.el == EL0) || (cpsr.el == EL1))) {
((curr_el == EL0) || (curr_el == EL1))) {
fault = checkForWFxTrap32(tc, EL2, isWfe);
}
if ((fault == NoFault) &&
ArmSystem::haveEL(tc, EL3) && cpsr.el != EL3) {
ArmSystem::haveEL(tc, EL3) && curr_el != EL3) {
fault = checkForWFxTrap32(tc, EL3, isWfe);
}
@@ -899,9 +901,9 @@ Fault
ArmStaticInst::checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const
{
bool setend_disabled(false);
ExceptionLevel pstateEL = (ExceptionLevel)(uint8_t)(cpsr.el);
ExceptionLevel pstate_el = currEL(tc);
if (pstateEL == EL2) {
if (pstate_el == EL2) {
setend_disabled = ((SCTLR)tc->readMiscRegNoEffect(MISCREG_HSCTLR)).sed;
} else {
// Please note: in the armarm pseudocode there is a distinction
@@ -923,7 +925,7 @@ ArmStaticInst::checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const
setend_disabled = ((SCTLR)tc->readMiscRegNoEffect(banked_sctlr)).sed;
}
return setend_disabled ? undefinedFault32(tc, pstateEL) :
return setend_disabled ? undefinedFault32(tc, pstate_el) :
NoFault;
}

4
src/arch/arm/interrupts.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2009, 2012-2013, 2016 ARM Limited
* Copyright (c) 2009, 2012-2013, 2016, 2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -58,7 +58,7 @@ ArmISA::Interrupts::takeInt(ThreadContext *tc, InterruptTypes int_type) const
SCR scr;
HCR hcr;
hcr = tc->readMiscReg(MISCREG_HCR);
ExceptionLevel el = (ExceptionLevel) ((uint32_t) cpsr.el);
ExceptionLevel el = currEL(tc);
bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit;
if (!highest_el_is_64)

2
src/arch/arm/utility.cc
View File

@@ -341,7 +341,7 @@ ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
// EL0 controlled by PSTATE
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
known = (cpsr.el == EL0);
known = (currEL(tc) == EL0);
aarch32 = (cpsr.width == 1);
} else {
known = true;