arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func
CAS/CASP atomic instruction implementation This change includes: + Instructions decode + new amo64.isa file where CAS/CASP main functional code is implemented + mem64.isa include Execute/complete/initiatie skeletons, contructor and declarator + Added TypedAtomic function for pair register CASP instruction Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19811 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Jordi Vaquero
@@ -306,6 +306,28 @@ class AtomicGeneric3Op : public TypedAtomicOpFunctor<T>
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std::function<void(T*, T, T)> op;
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};
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template<typename T>
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class AtomicGenericPair3Op : public TypedAtomicOpFunctor<T>
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{
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public:
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AtomicGenericPair3Op(std::array<T, 2>& _a, std::array<T, 2> _c,
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std::function<void(T*, std::array<T, 2>&, std::array<T, 2>)> _op)
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: a(_a), c(_c), op(_op)
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{}
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AtomicOpFunctor* clone() override
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{
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return new AtomicGenericPair3Op<T>(*this);
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}
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void execute(T* b) override
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{
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op(b, a, c);
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}
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private:
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std::array<T, 2> a;
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std::array<T, 2> c;
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std::function<void(T*, std::array<T, 2>&, std::array<T, 2>)> op;
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};
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}
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#endif //__ARCH_ARM_INSTS_MEM_HH__
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@@ -587,8 +587,9 @@ namespace Aarch64
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case 0x2:
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switch (size) {
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case 0x0:
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return new CASP32(machInst, rt, rnsp, rs);
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case 0x1:
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return new Unknown64(machInst);
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return new CASP64(machInst, rt, rnsp, rs);
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case 0x2:
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return new STXPW64(machInst, rs, rt, rt2, rnsp);
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case 0x3:
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@@ -600,8 +601,9 @@ namespace Aarch64
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case 0x3:
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switch (size) {
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case 0x0:
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return new CASPL32(machInst, rt, rnsp, rs);
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case 0x1:
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return new Unknown64(machInst);
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return new CASPL64(machInst, rt, rnsp, rs);
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case 0x2:
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return new STLXPW64(machInst, rs, rt, rt2, rnsp);
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case 0x3:
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@@ -639,8 +641,9 @@ namespace Aarch64
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case 0x6:
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switch (size) {
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case 0x0:
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return new CASPA32(machInst, rt, rnsp, rs);
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case 0x1:
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return new Unknown64(machInst);
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return new CASPA64(machInst, rt, rnsp, rs);
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case 0x2:
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return new LDXPW64(machInst, rt, rt2, rnsp);
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case 0x3:
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@@ -648,12 +651,12 @@ namespace Aarch64
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default:
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M5_UNREACHABLE;
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}
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case 0x7:
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switch (size) {
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case 0x0:
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return new CASPAL32(machInst, rt, rnsp, rs);
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case 0x1:
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return new Unknown64(machInst);
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return new CASPAL64(machInst, rt, rnsp, rs);
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case 0x2:
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return new LDAXPW64(machInst, rt, rt2, rnsp);
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case 0x3:
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@@ -661,7 +664,6 @@ namespace Aarch64
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default:
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M5_UNREACHABLE;
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}
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case 0x9:
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switch (size) {
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case 0x0:
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@@ -675,6 +677,32 @@ namespace Aarch64
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default:
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M5_UNREACHABLE;
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}
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case 0xa:
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switch (size) {
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case 0x0:
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return new CASB(machInst, rt, rnsp, rs);
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case 0x1:
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return new CASH(machInst, rt, rnsp, rs);
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case 0x2:
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return new CAS32(machInst, rt, rnsp, rs);
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case 0x3:
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return new CAS64(machInst, rt, rnsp, rs);
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default:
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M5_UNREACHABLE;
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}
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case 0xb:
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switch (size) {
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case 0x0:
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return new CASLB(machInst, rt, rnsp, rs);
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case 0x1:
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return new CASLH(machInst, rt, rnsp, rs);
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case 0x2:
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return new CASL32(machInst, rt, rnsp, rs);
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case 0x3:
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return new CASL64(machInst, rt, rnsp, rs);
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default:
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M5_UNREACHABLE;
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}
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case 0xd:
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switch (size) {
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case 0x0:
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@@ -688,6 +716,32 @@ namespace Aarch64
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default:
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M5_UNREACHABLE;
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}
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case 0xe:
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switch (size) {
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case 0x0:
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return new CASAB(machInst, rt, rnsp, rs);
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case 0x1:
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return new CASAH(machInst, rt, rnsp, rs);
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case 0x2:
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return new CASA32(machInst, rt, rnsp, rs);
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case 0x3:
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return new CASA64(machInst, rt, rnsp, rs);
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default:
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M5_UNREACHABLE;
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}
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case 0xf:
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switch (size) {
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case 0x0:
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return new CASALB(machInst, rt, rnsp, rs);
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case 0x1:
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return new CASALH(machInst, rt, rnsp, rs);
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case 0x2:
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return new CASAL32(machInst, rt, rnsp, rs);
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case 0x3:
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return new CASAL64(machInst, rt, rnsp, rs);
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default:
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M5_UNREACHABLE;
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}
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default:
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return new Unknown64(machInst);
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}
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401
src/arch/arm/isa/insts/amo64.isa
Normal file
401
src/arch/arm/isa/insts/amo64.isa
Normal file
@@ -0,0 +1,401 @@
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// -*- mode:c++ -*-
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// Copyright (c) 2018 Metempsy Technology Consulting
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Jordi Vaquero
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let {{
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import math
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OP_DICT = { "CAS" : 'if (a == *b){*b = c;}',
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"SWP" : '*b = c;',
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"ADD" : '*b += c;',
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"EOR" : '*b ^= c;',
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"CLR" : '*b &= ~c;',
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"SET" : '*b |= c;',
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"MAX" : '*b = std::max(*b, c);',
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"MIN" : '*b = std::min(*b, c);', }
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MASKS = { 1: 0xFF,
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2: 0xFFFF,
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4: 0xFFFFFFFF,
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8: 0xFFFFFFFFFFFFFFFF,
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}
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header_output = ""
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decoder_output = ""
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exec_output = ""
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class AtomicInst64(LoadStoreInst):
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execBase = 'AtomicInst64'
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micro = False
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def __init__(self, mnem, Name, size=4, user=False, flavor="normal",
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unsign=True, top = False, paired=False):
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super(AtomicInst64, self).__init__()
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self.name= mnem
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self.Name = Name
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self.size = size
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self.user = user
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self.flavor = flavor
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self.unsign = unsign
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self.top = top
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self.paired = paired
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self.memFlags = ["ArmISA::TLB::MustBeOne"]
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self.instFlags = ["IsAtomic"]
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self.codeBlobs = { "postacc_code" : "" }
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self.codeBlobs['usrDecl'] = ""
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# Add memory request flags where necessary
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if self.user:
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self.memFlags.append("ArmISA::TLB::UserMode")
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sz = self.size*2 if paired else self.size
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self.memFlags.append("%d" % int(math.log(sz, 2)))
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if self.micro:
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self.instFlags.append("IsMicroop")
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if self.flavor in ("release", "acquire_release", "acquire"):
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self.instFlags.append("IsMemBarrier")
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if self.flavor in ("release", "acquire_release"):
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self.instFlags.append("IsWriteBarrier")
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if self.flavor in ("acquire_release", "acquire"):
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self.instFlags.append("IsReadBarrier")
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self.memFlags.append('Request::ATOMIC_RETURN_OP')
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def emitHelper(self, base = 'Memory64', wbDecl = None, ):
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global header_output, decoder_output, exec_output
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# If this is a microop itself, don't allow anything that would
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# require further microcoding.
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if self.micro:
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assert not wbDecl
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fa_code = None
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if not self.micro :
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#and self.flavor in ("normal", "release"):
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fa_code = '''
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fault->annotate(ArmFault::SAS, %s);
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fault->annotate(ArmFault::SSE, false);
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fault->annotate(ArmFault::SRT, dest);
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fault->annotate(ArmFault::SF, %s);
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fault->annotate(ArmFault::AR, %s);
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''' % ("0" if self.size == 1 else
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"1" if self.size == 2 else
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"2" if self.size == 4 else "3",
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"true" if self.size == 8 else "false",
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"true" if self.flavor != "normal" else "false")
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sas_code = "3"
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if self.size == 1 :
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sas_code = "0"
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elif self.size == 2:
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sas_code = "1"
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elif self.size == 4:
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sas_code = "2"
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if self.paired and sas_code == "3":
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sas_code = "4"
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if self.paired and sas_code == "2":
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sas_code = "3"
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fa_code = '''
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fault->annotate(ArmFault::SAS, %s);
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fault->annotate(ArmFault::SSE, %s);
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fault->annotate(ArmFault::SRT, dest);
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fault->annotate(ArmFault::SF, %s);
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fault->annotate(ArmFault::AR, %s);
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''' % (sas_code,
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"true" if not self.unsign else "false",
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"true" if self.size == 8 else "false",
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"true" if self.flavor != "normal" else "false")
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(newHeader, newDecoder, newExec) = \
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self.fillTemplates(self.name, self.Name, self.codeBlobs,
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self.memFlags, self.instFlags,
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base, wbDecl, faCode=fa_code)
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header_output += newHeader
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decoder_output += newDecoder
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exec_output += newExec
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def buildEACode(self):
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# Address computation
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eaCode = SPAlignmentCheckCode + "EA = XBase"
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if self.size == 16:
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if self.top:
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eaCode += " + (isBigEndian64(xc->tcBase()) ? 0 : 8)"
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else:
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eaCode += " + (isBigEndian64(xc->tcBase()) ? 8 : 0)"
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if not self.post:
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eaCode += self.offset
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eaCode += ";"
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self.codeBlobs["ea_code"] = eaCode
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class AtomicSingleOp(AtomicInst64):
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decConstBase = 'AmoOp'
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base = 'ArmISA::MemoryEx64'
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writeback = True
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post = False
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execBase = 'AmoOp'
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def __init__(self, *args, **kargs):
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super(AtomicSingleOp, self).__init__(*args, **kargs)
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self.suffix = buildMemSuffix(not self.unsign, self.size)
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if self.size == 8:
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self.res = 'XResult_ud' #if self.unsign else 'XResult_sd'
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self.des = 'XDest_ud' #if self.unsign else 'XDest_sd'
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self.tp = 'uint64_t' if self.unsign else 'int64_t'
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self.utp = 'uint64_t'
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self.suffix = '_sd' if not self.unsign else '_ud'
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elif self.size == 4:
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self.res = 'XResult_uw' #if self.unsign else 'XResult_sw'
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self.des = 'XDest_uw' #if self.unsign else 'XDest_sw'
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self.tp = 'uint32_t' if self.unsign else 'int32_t'
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self.utp = 'uint32_t'
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elif self.size == 2:
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self.res = 'XResult_uh' #if self.unsign else 'XResult_sh'
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self.des = 'XDest_uh' #if self.unsign else 'XDest_sh'
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self.tp = 'uint16_t' if self.unsign else 'int16_t'
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self.utp = 'uint16_t'
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elif self.size == 1:
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self.res = 'XResult_ub' #if self.unsign else 'XResult_sb'
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self.des = 'XDest_ub' #if self.unsign else 'XDest_sb'
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self.tp = 'uint8_t' if self.unsign else 'int8_t'
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self.utp = 'uint8_t'
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self.offset = ""
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store_res = '''
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%(result)s = cSwap(Mem%(suffix)s,
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isBigEndian64(xc->tcBase()));
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'''
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store_res = store_res % {"result":self.res, "suffix":self.suffix}
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self.codeBlobs["postacc_code"] = \
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store_res + " SevMailbox = 1; LLSCLock = 0;"
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def emit(self, op):
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self.buildEACode()
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usrDecl = "%(type)s valRs;\n" % {'type': self.tp}
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self.codeBlobs['usrDecl'] = usrDecl
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opcode = "valRs = cSwap(%(dest)s,"\
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" isBigEndian64(xc->tcBase()));\n"
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opcode += "TypedAtomicOpFunctor<%(type)s> *amo_op = "\
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"new AtomicGeneric3Op<%(type)s>(Mem%(suffix)s,"\
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" valRs, [](%(type)s* b, %(type)s a,"\
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" %(type)s c){ %(op)s });\n"
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opcode = opcode % {"suffix": self.suffix,
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"type": self.tp ,
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"dest": self.des,
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"op": op}
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self.codeBlobs['amo_code'] = opcode
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accCode = "Mem%(suffix)s = cSwap(%(result)s,"\
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" isBigEndian64(xc->tcBase()));"
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accCode = accCode % { "result": self.res, "type":self.tp,
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"suffix": self.suffix}
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self.codeBlobs["memacc_code"] = accCode
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self.emitHelper(self.base)
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AtomicSingleOp("cas", "CAS64", 8, unsign=True,
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flavor="normal").emit(OP_DICT['CAS'])
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AtomicSingleOp("casa", "CASA64", 8, unsign=True,
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flavor="acquire").emit(OP_DICT['CAS'])
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AtomicSingleOp("casal", "CASAL64", 8, unsign=True,
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flavor="acquire_release").emit(OP_DICT['CAS'])
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AtomicSingleOp("casl", "CASL64", 8, unsign=True,
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flavor="release").emit(OP_DICT['CAS'])
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AtomicSingleOp("casb", "CASB", 1, unsign=True,
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flavor="normal").emit(OP_DICT['CAS'])
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AtomicSingleOp("casab", "CASAB", 1, unsign=True,
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flavor="acquire").emit(OP_DICT['CAS'])
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AtomicSingleOp("casalb", "CASALB", 1, unsign=True,
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flavor="acquire_release").emit(OP_DICT['CAS'])
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AtomicSingleOp("caslb", "CASLB", 1, unsign=True,
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flavor="release").emit(OP_DICT['CAS'])
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AtomicSingleOp("cash", "CASH", 2, unsign=True,
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flavor="normal").emit(OP_DICT['CAS'])
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AtomicSingleOp("casah", "CASAH", 2, unsign=True,
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flavor="acquire").emit(OP_DICT['CAS'])
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AtomicSingleOp("casalh", "CASALH", 2, unsign=True,
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flavor="acquire_release").emit(OP_DICT['CAS'])
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AtomicSingleOp("caslh", "CASLH", 2, unsign=True,
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flavor="release").emit(OP_DICT['CAS'])
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AtomicSingleOp("cas", "CAS32", 4, unsign=True,
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flavor="normal").emit(OP_DICT['CAS'])
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AtomicSingleOp("casa", "CASA32", 4, unsign=True,
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flavor="acquire").emit(OP_DICT['CAS'])
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AtomicSingleOp("casal", "CASAL32", 4, unsign=True,
|
||||
flavor="acquire_release").emit(OP_DICT['CAS'])
|
||||
AtomicSingleOp("casl", "CASL32", 4, unsign=True,
|
||||
flavor="release").emit(OP_DICT['CAS'])
|
||||
|
||||
class CasPair64(AtomicInst64):
|
||||
decConstBase = 'AmoPairOp'
|
||||
base = 'ArmISA::MemoryEx64'
|
||||
writeback = True
|
||||
post = False
|
||||
execBase = 'AmoOp'
|
||||
|
||||
def __init__(self, *args, **kargs):
|
||||
super(CasPair64, self).__init__(*args, **kargs)
|
||||
self.paired = True
|
||||
self.offset = ""
|
||||
if self.size == 8:
|
||||
self.res = 'XResult_ud'
|
||||
self.des = 'XDest_ud'
|
||||
self.tp = 'std::array<uint64_t, 2>'
|
||||
self.suffix = "_tud"
|
||||
store_res = '''
|
||||
%(result)s = cSwap(Mem%(suffix)s[0],
|
||||
isBigEndian64(xc->tcBase()));
|
||||
uint64_t result2 = cSwap(Mem%(suffix)s[1],
|
||||
isBigEndian64(xc->tcBase()));
|
||||
xc->setIntRegOperand(this, r2_dst, (result2)
|
||||
& mask(aarch64 ? 64 : 32));
|
||||
'''
|
||||
elif self.size == 4:
|
||||
self.res = 'Result_uw'
|
||||
self.des = 'WDest_uw'
|
||||
self.tp = 'uint64_t'
|
||||
self.suffix = "_ud"
|
||||
store_res = '''
|
||||
uint64_t data = cSwap(Mem%(suffix)s,
|
||||
isBigEndian64(xc->tcBase()));
|
||||
%(result)s = isBigEndian64(xc->tcBase())
|
||||
? (data >> 32)
|
||||
: (uint32_t)data;
|
||||
uint32_t result2 = isBigEndian64(xc->tcBase())
|
||||
? (uint32_t)data
|
||||
: (data >> 32);
|
||||
xc->setIntRegOperand(this, r2_dst, (result2) &
|
||||
mask(aarch64 ? 64 : 32));
|
||||
'''
|
||||
|
||||
store_res = store_res % {"result":self.res, "suffix":self.suffix}
|
||||
usrDecl = "%(type)s valRs;\n" % {'type': self.tp}
|
||||
self.codeBlobs['usrDecl'] = usrDecl
|
||||
self.codeBlobs["postacc_code"] = \
|
||||
store_res + " SevMailbox = 1; LLSCLock = 0;"
|
||||
|
||||
def emit(self):
|
||||
self.buildEACode()
|
||||
|
||||
# Code that actually handles the access
|
||||
|
||||
if self.size == 4:
|
||||
accCode = \
|
||||
"uint32_t result2 = ((xc->readIntRegOperand(this, r2_src))"\
|
||||
" & mask(aarch64 ? 64 : 32)) ;\n"\
|
||||
" uint32_t dest2 = ((xc->readIntRegOperand(this, d2_src)) "\
|
||||
" & mask(aarch64 ? 64 : 32)) ;"
|
||||
accCode += '''
|
||||
uint64_t data = dest2;
|
||||
data = isBigEndian64(xc->tcBase())
|
||||
? ((uint64_t(WDest_uw) << 32) | data)
|
||||
: ((data << 32) | WDest_uw);
|
||||
valRs = cSwap(data, isBigEndian64(xc->tcBase()));
|
||||
uint64_t data2 = result2 ;
|
||||
data2 = isBigEndian64(xc->tcBase())
|
||||
? ((uint64_t(Result_uw) << 32) | data2)
|
||||
: ((data2 << 32) | Result_uw);
|
||||
Mem_ud = cSwap(data2, isBigEndian64(xc->tcBase()));
|
||||
'''
|
||||
|
||||
opcode = "TypedAtomicOpFunctor<%(type)s> *amo_op = "\
|
||||
"new AtomicGeneric3Op<%(type)s>(Mem%(suffix)s,"\
|
||||
" valRs, [](%(type)s* b, %(type)s a,"\
|
||||
" %(type)s c){ %(op)s });\n"
|
||||
|
||||
elif self.size == 8:
|
||||
accCode = ""\
|
||||
"uint64_t result2 = ((xc->readIntRegOperand(this, r2_src))"\
|
||||
" & mask(aarch64 ? 64 : 32)) ;\n"\
|
||||
" uint64_t dest2 = ((xc->readIntRegOperand(this, d2_src)) "\
|
||||
" & mask(aarch64 ? 64 : 32)) ;"
|
||||
accCode += '''
|
||||
// This temporary needs to be here so that the parser
|
||||
// will correctly identify this instruction as a store.
|
||||
std::array<uint64_t, 2> temp;
|
||||
temp[0] = cSwap(XDest_ud,isBigEndian64(xc->tcBase()));
|
||||
temp[1] = cSwap(dest2,isBigEndian64(xc->tcBase()));
|
||||
valRs = temp;
|
||||
std::array<uint64_t, 2> temp2;
|
||||
temp2[0] = cSwap(XResult_ud,isBigEndian64(xc->tcBase()));
|
||||
temp2[1] = cSwap(result2,isBigEndian64(xc->tcBase()));
|
||||
Mem_tud = temp2;
|
||||
'''
|
||||
|
||||
opcode = "TypedAtomicOpFunctor<uint64_t> *amo_op = "\
|
||||
"new AtomicGenericPair3Op<uint64_t>(Mem_tud, "\
|
||||
"valRs, [](uint64_t* b, std::array<uint64_t,2> a,"\
|
||||
'''
|
||||
std::array<uint64_t,2> c){
|
||||
if(a[0]==b[0] && a[1]==b[1]){
|
||||
b[0] = c[0]; b[1] = c[1];
|
||||
}
|
||||
});'''
|
||||
|
||||
opcode = opcode % { "suffix" : self.suffix,
|
||||
"type": self.tp,
|
||||
"op": OP_DICT['CAS']}
|
||||
self.codeBlobs['amo_code'] = opcode
|
||||
self.codeBlobs["memacc_code"] = accCode % {"type": self.tp}
|
||||
|
||||
# Push it out to the output files
|
||||
self.emitHelper(self.base)
|
||||
|
||||
CasPair64("casp", "CASP64", 8, flavor="normal", paired=True).emit()
|
||||
CasPair64("caspa", "CASPA64", 8, flavor="acquire", paired=True).emit()
|
||||
CasPair64("caspal", "CASPAL64", 8, flavor="acquire_release",
|
||||
paired=True).emit()
|
||||
CasPair64("caspl", "CASPL64", 8, flavor="release", paired=True).emit()
|
||||
|
||||
CasPair64("casp", "CASP32", 4, flavor="normal", paired=True).emit()
|
||||
CasPair64("caspa", "CASPA32", 4, flavor="acquire", paired=True).emit()
|
||||
CasPair64("caspal", "CASPAL32", 4, flavor="acquire_release",
|
||||
paired=True).emit()
|
||||
CasPair64("caspl", "CASPL32", 4, flavor="release", paired=True).emit()
|
||||
|
||||
}};
|
||||
@@ -43,6 +43,9 @@
|
||||
//Useful bits shared by memory instructions
|
||||
##include "mem.isa"
|
||||
|
||||
//AArch64 atomic operations
|
||||
##include "amo64.isa"
|
||||
|
||||
//Loads of a single item
|
||||
##include "ldr.isa"
|
||||
|
||||
|
||||
@@ -729,3 +729,212 @@ def template LoadStoreLitU64Constructor {{
|
||||
setExcAcRel(exclusive, acrel);
|
||||
}
|
||||
}};
|
||||
|
||||
// Atomic operations in memory
|
||||
|
||||
def template AmoOpExecute {{
|
||||
Fault %(class_name)s::execute(ExecContext *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Addr EA;
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(ea_code)s;
|
||||
|
||||
%(usrDecl)s;
|
||||
if (fault == NoFault) {
|
||||
%(memacc_code)s;
|
||||
}
|
||||
|
||||
%(amo_code)s
|
||||
assert(amo_op);
|
||||
|
||||
if (fault == NoFault) {
|
||||
fault = amoMemAtomic(xc, traceData, Mem, EA,
|
||||
memAccessFlags, amo_op);
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(postacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(op_wb)s;
|
||||
}
|
||||
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
def template AmoOpInitiateAcc {{
|
||||
Fault %(class_name)s::initiateAcc(ExecContext *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Addr EA;
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(op_src_decl)s;
|
||||
%(op_rd)s;
|
||||
%(ea_code)s;
|
||||
%(usrDecl)s;
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(memacc_code)s;
|
||||
}
|
||||
|
||||
%(amo_code)s;
|
||||
|
||||
assert(amo_op);
|
||||
if (fault == NoFault) {
|
||||
fault = initiateMemAMO(xc, traceData, EA, Mem, memAccessFlags,
|
||||
amo_op);
|
||||
}
|
||||
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
def template AmoOpCompleteAcc {{
|
||||
Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
|
||||
// ARM instructions will not have a pkt if the predicate is false
|
||||
getMem(pkt, Mem, traceData);
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(postacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(op_wb)s;
|
||||
}
|
||||
|
||||
return fault;
|
||||
}
|
||||
|
||||
}};
|
||||
|
||||
def template AmoOpDeclare {{
|
||||
class %(class_name)s : public %(base_class)s
|
||||
{
|
||||
public:
|
||||
|
||||
/// Constructor.
|
||||
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
|
||||
IntRegIndex _base, IntRegIndex _result);
|
||||
|
||||
Fault execute(ExecContext *, Trace::InstRecord *) const override;
|
||||
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
|
||||
Fault completeAcc(PacketPtr, ExecContext *,
|
||||
Trace::InstRecord *) const override;
|
||||
|
||||
void
|
||||
annotateFault(ArmFault *fault) override
|
||||
{
|
||||
%(fa_code)s
|
||||
}
|
||||
};
|
||||
}};
|
||||
|
||||
|
||||
def template AmoOpConstructor {{
|
||||
%(class_name)s::%(class_name)s(ExtMachInst machInst,
|
||||
IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
|
||||
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
||||
_dest, _base, _result)
|
||||
{
|
||||
%(constructor)s;
|
||||
|
||||
}
|
||||
}};
|
||||
|
||||
def template AmoPairOpDeclare {{
|
||||
class %(class_name)s : public %(base_class)s
|
||||
{
|
||||
public:
|
||||
uint32_t d2_src ;
|
||||
uint32_t r2_src ;
|
||||
uint32_t r2_dst ;
|
||||
/// Constructor.
|
||||
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
|
||||
IntRegIndex _base, IntRegIndex _result);
|
||||
|
||||
Fault execute(ExecContext *, Trace::InstRecord *) const override;
|
||||
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
|
||||
Fault completeAcc(PacketPtr, ExecContext *,
|
||||
Trace::InstRecord *) const override;
|
||||
|
||||
void
|
||||
annotateFault(ArmFault *fault) override
|
||||
{
|
||||
%(fa_code)s
|
||||
}
|
||||
};
|
||||
}};
|
||||
|
||||
|
||||
def template AmoPairOpConstructor {{
|
||||
%(class_name)s::%(class_name)s(ExtMachInst machInst,
|
||||
IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
|
||||
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
||||
_dest, _base, _result)
|
||||
{
|
||||
%(constructor)s;
|
||||
|
||||
uint32_t d2 = RegId(IntRegClass, dest).index() + 1 ;
|
||||
uint32_t r2 = RegId(IntRegClass, result).index() + 1 ;
|
||||
|
||||
d2_src = _numSrcRegs ;
|
||||
_srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, d2);
|
||||
r2_src = _numSrcRegs ;
|
||||
_srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, r2);
|
||||
r2_dst = _numDestRegs ;
|
||||
_destRegIdx[_numDestRegs++] = RegId(IntRegClass, r2);
|
||||
|
||||
}
|
||||
}};
|
||||
|
||||
def template AmoArithmeticOpDeclare {{
|
||||
class %(class_name)s : public %(base_class)s
|
||||
{
|
||||
public:
|
||||
bool isXZR ;
|
||||
/// Constructor.
|
||||
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
|
||||
IntRegIndex _base, IntRegIndex _result);
|
||||
|
||||
Fault execute(ExecContext *, Trace::InstRecord *) const override;
|
||||
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
|
||||
Fault completeAcc(PacketPtr, ExecContext *,
|
||||
Trace::InstRecord *) const override;
|
||||
|
||||
void
|
||||
annotateFault(ArmFault *fault) override
|
||||
{
|
||||
%(fa_code)s
|
||||
}
|
||||
};
|
||||
}};
|
||||
|
||||
def template AmoArithmeticOpConstructor {{
|
||||
%(class_name)s::%(class_name)s(ExtMachInst machInst,
|
||||
IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
|
||||
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
||||
_dest, _base, _result)
|
||||
{
|
||||
%(constructor)s;
|
||||
isXZR = false;
|
||||
uint32_t r2 = RegId(IntRegClass, dest).index() ;
|
||||
if (r2 == 31){
|
||||
flags[IsReadBarrier] = false;
|
||||
isXZR = true;
|
||||
}
|
||||
}
|
||||
}};
|
||||
|
||||
Reference in New Issue
Block a user