arch-arm: adding register control flags enabling LSE implementation

Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in ID registers and add have_lse variable into arm system.

Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/ArmSystem.py

@@ -86,6 +86,8 @@ class ArmSystem(System):
         "True if SVE is implemented (ARMv8)")
     sve_vl = Param.SveVectorLength(1,
         "SVE vector length in quadwords (128-bit)")
+    have_lse = Param.Bool(True,
+        "True if LSE is implemented (ARMv8.1)")
     have_pan = Param.Bool(True,
         "True if Priviledge Access Never is implemented (ARMv8.1)")
 

src/arch/arm/isa.cc

@@ -93,6 +93,7 @@ ISA::ISA(Params *p)
         haveSVE = system->haveSVE();
         havePAN = system->havePAN();
         sveVL = system->sveVL();
+        haveLSE = system->haveLSE();
     } else {
         highestELIs64 = true; // ArmSystem::highestELIs64 does the same
         haveSecurity = haveLPAE = haveVirtualization = false;
@@ -102,6 +103,7 @@ ISA::ISA(Params *p)
         haveSVE = true;
         havePAN = false;
         sveVL = p->sve_vl_se;
+        haveLSE = true;
     }
 
     // Initial rename mode depends on highestEL
@@ -393,6 +395,10 @@ ISA::initID64(const ArmISAParams *p)
     miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
         miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
         haveCrypto ? 0x1112 : 0x0);
+    // LSE
+    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
+        miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
+        haveLSE ? 0x2 : 0x0);
     // PAN
     miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
         miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,

src/arch/arm/isa.hh

@@ -95,6 +95,7 @@ namespace ArmISA
         bool haveGICv3CPUInterface;
         uint8_t physAddrRange;
         bool haveSVE;
+        bool haveLSE;
         bool havePAN;
 
         /** SVE vector length in quadwords */
@@ -687,6 +688,7 @@ namespace ArmISA
             SERIALIZE_SCALAR(physAddrRange);
             SERIALIZE_SCALAR(haveSVE);
             SERIALIZE_SCALAR(sveVL);
+            SERIALIZE_SCALAR(haveLSE);
             SERIALIZE_SCALAR(havePAN);
         }
         void unserialize(CheckpointIn &cp)
@@ -704,6 +706,7 @@ namespace ArmISA
             UNSERIALIZE_SCALAR(physAddrRange);
             UNSERIALIZE_SCALAR(haveSVE);
             UNSERIALIZE_SCALAR(sveVL);
+            UNSERIALIZE_SCALAR(haveLSE);
             UNSERIALIZE_SCALAR(havePAN);
         }
 

src/arch/arm/system.cc

@@ -73,6 +73,7 @@ ArmSystem::ArmSystem(Params *p)
       _haveLargeAsid64(p->have_large_asid_64),
       _haveSVE(p->have_sve),
       _sveVL(p->sve_vl),
+      _haveLSE(p->have_lse),
       _havePAN(p->have_pan),
       _m5opRange(p->m5ops_base ?
                  RangeSize(p->m5ops_base, 0x10000) :

src/arch/arm/system.hh

@@ -130,6 +130,11 @@ class ArmSystem : public System
     /** SVE vector length at reset, in quadwords */
     const unsigned _sveVL;
 
+    /**
+     * True if LSE is implemented (ARMv8.1)
+     */
+    const bool _haveLSE;
+
     /** True if Priviledge Access Never is implemented */
     const unsigned _havePAN;
 
@@ -244,6 +249,9 @@ class ArmSystem : public System
     /** Returns the SVE vector length at reset, in quadwords */
     unsigned sveVL() const { return _sveVL; }
 
+    /** Returns true if LSE is implemented (ARMv8.1) */
+    bool haveLSE() const { return _haveLSE; }
+
     /** Returns true if Priviledge Access Never is implemented */
     bool havePAN() const { return _havePAN; }