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mem-ruby, arch-hsail: Removed hit latency from VIPERCoalescer

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Removed the dcache hit latency from VIPERCoalescer so HSAIL_X86
compiles after commit 496d5ed3e1

Change-Id: I050a58d90f0f6356824c3c3bcb3f0b3c76d145e0
Signed-off-by: Pablo Prieto <pablo.prieto@unican.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19148
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Pablo Prieto
2019-06-06 16:33:26 +02:00
committed by Anthony Gutierrez
parent c7f18da6b0
commit 4bcb6023f1
1 changed files with 24 additions and 8 deletions
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32
src/mem/ruby/system/VIPERCoalescer.cc
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@@ -213,12 +213,16 @@ VIPERCoalescer::invL1()
for (int i = 0; i < size; i++) {
Addr addr = m_dataCache_ptr->getAddressAtIdx(i);
// Evict Read-only data
RubyRequestType request_type = RubyRequestType_REPLACEMENT;
std::shared_ptr<RubyRequest> msg = std::make_shared<RubyRequest>(
clockEdge(), addr, (uint8_t*) 0, 0, 0,
RubyRequestType_REPLACEMENT, RubyAccessMode_Supervisor,
request_type, RubyAccessMode_Supervisor,
nullptr);
assert(m_mandatory_q_ptr != NULL);
m_mandatory_q_ptr->enqueue(msg, clockEdge(), m_data_cache_hit_latency);
Tick latency = cyclesToTicks(
m_controller->mandatoryQueueLatency(request_type));
assert(latency > 0);
m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
m_outstanding_inv++;
}
DPRINTF(GPUCoalescer,
@@ -240,12 +244,16 @@ VIPERCoalescer::wbL1()
for (int i = 0; i < size; i++) {
Addr addr = m_dataCache_ptr->getAddressAtIdx(i);
// Write dirty data back
RubyRequestType request_type = RubyRequestType_FLUSH;
std::shared_ptr<RubyRequest> msg = std::make_shared<RubyRequest>(
clockEdge(), addr, (uint8_t*) 0, 0, 0,
RubyRequestType_FLUSH, RubyAccessMode_Supervisor,
request_type, RubyAccessMode_Supervisor,
nullptr);
assert(m_mandatory_q_ptr != NULL);
m_mandatory_q_ptr->enqueue(msg, clockEdge(), m_data_cache_hit_latency);
Tick latency = cyclesToTicks(
m_controller->mandatoryQueueLatency(request_type));
assert(latency > 0);
m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
m_outstanding_wb++;
}
DPRINTF(GPUCoalescer,
@@ -264,24 +272,32 @@ VIPERCoalescer::invwbL1()
for (int i = 0; i < size; i++) {
Addr addr = m_dataCache_ptr->getAddressAtIdx(i);
// Evict Read-only data
RubyRequestType request_type = RubyRequestType_REPLACEMENT;
std::shared_ptr<RubyRequest> msg = std::make_shared<RubyRequest>(
clockEdge(), addr, (uint8_t*) 0, 0, 0,
RubyRequestType_REPLACEMENT, RubyAccessMode_Supervisor,
request_type, RubyAccessMode_Supervisor,
nullptr);
assert(m_mandatory_q_ptr != NULL);
m_mandatory_q_ptr->enqueue(msg, clockEdge(), m_data_cache_hit_latency);
Tick latency = cyclesToTicks(
m_controller->mandatoryQueueLatency(request_type));
assert(latency > 0);
m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
m_outstanding_inv++;
}
// Walk the cache
for (int i = 0; i< size; i++) {
Addr addr = m_dataCache_ptr->getAddressAtIdx(i);
// Write dirty data back
RubyRequestType request_type = RubyRequestType_FLUSH;
std::shared_ptr<RubyRequest> msg = std::make_shared<RubyRequest>(
clockEdge(), addr, (uint8_t*) 0, 0, 0,
RubyRequestType_FLUSH, RubyAccessMode_Supervisor,
request_type, RubyAccessMode_Supervisor,
nullptr);
assert(m_mandatory_q_ptr != NULL);
m_mandatory_q_ptr->enqueue(msg, clockEdge(), m_data_cache_hit_latency);
Tick latency = cyclesToTicks(
m_controller->mandatoryQueueLatency(request_type));
assert(latency > 0);
m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
m_outstanding_wb++;
}
}