This patch adds a subset (rv64*) of RISC-V assembly tests. The original
riscv-test project can be found here:
https://github.com/riscv/riscv-tests. The riscv-test project is under the
BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE)
and is maintained separately from gem5 project.
The tests have been slightly modified to work in gem5 SE mode:
(1) Removed a trap handler used in riscv-tests for bare-metal systems
(2) Instead of throwing an exception, the tests call the exit syscall
with
the exit code of
- '0' if SUCCESS
- Failed test case's number (non-zero) if FAILURE
The exit code can be captured after a simuation completes.
In addition to original RISC-V assembly tests, this patch adds several
assembly tests specifically for AMO, LR, SC and system calls. Those
tests target a multi-core system.
(1) rv64uamt: multi-threaded tests for A-extension instructions
(2) rv64samt: multi-threaded tests for clone and futex system calls
This patch also makes the style checker ignore RISC-V assembly test
directory. The assembly tests are maintained in an external project
that does not follow the gem5 coding conventions.
Please find more details in the README file included in this patch.
Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0
Reviewed-on: https://gem5-review.googlesource.com/6703
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
The class re-uses the existing MSHR and write queue. At the moment
every single access is handled by the cache, even uncacheable
accesses, and nothing is forwarded.
This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>
Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
Reviewed-on: https://gem5-review.googlesource.com/8291
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Prior to this changeset the bootloader rom (instantiated as a
SimpleMemory) in ruby Arm systems was treated as an IO device and it
was fronted by a DMA controller. This changeset moves the bootloader
rom and adds it to the system as another memory with a dedicated
directory controller.
Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Simple program that spawns threads equal to the number of CPU cores and
has some false sharing for testing coherence protocols.
Change-Id: I5be907fd6fea9a8b8e80b63785d186619be41354
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8901
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Starting with version 3, scons imposes using the print function instead
of the print statement in code it processes. To get things building
again, this change moves all python code within gem5 to use the
function version. Another change by another author separately made this
same change to the site_tools and site_init.py files.
Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0
Reviewed-on: https://gem5-review.googlesource.com/8761
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
This patch makes use of ImmOp's polymorphism to remove unnecessary
casting from the implementations of arithmetic instructions with
immediate operands and to remove the CUIOp format by combining it with
the CIOp format (compressed arithmetic instructions with immediate
operands). Interestingly, RISC-V specifies that instructions with
unsigned immediate operands still need to sign-extend the immediates
from 12 (or 20) bits to 64 bits, so that is left alone.
Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16
Reviewed-on: https://gem5-review.googlesource.com/6401
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
This patch adds two regression tests that execute the script in the
configs dir for triggering low power mode transitions. A separate
test is required for each page policy because for close-adaptive
page policy the DRAM goes into the Precharge Power-down mode while
for open-adaptive page policy it goes into the Activate Power-down
mode.
Change-Id: Iad61af23f132db046f2857cc3ef64b2bf42cf5e4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5726
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This patch updates the binaries and results for hello and insttest
regressions using the compressed extension.
Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e
Reviewed-on: https://gem5-review.googlesource.com/4042
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This patch adds instruction tests for the RV64C extension
implementation. It also updates existing executables for the latest
riscv-tools now that they are compatible.
[Update for changes to parents.]
Change-Id: Id4cfd966a8cae39b0d728b02849622fd00ee7e0e
Reviewed-on: https://gem5-review.googlesource.com/3862
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Previously ARM binaries were by default compiled with the MI_example
protocol. The MI_example protocol cannot properly support load/store
exclusive instructions and therefore it cannot be used to simulate
multicore ARM systems. This change changes to MOESI_CMP_directory as
the default ruby protocol for ARM systems.
Change-Id: I942d950ba466aea9a75f3d8764f9f3eddd0c3baa
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2906
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Update the "Hello, world!" executable for RISC-V to use the latest GNU
Linux toolchain and fix the stats accordingly.
Change-Id: I5ff3d7f4bb41b10170038b8c07492f15bb54a022
Reviewed-on: https://gem5-review.googlesource.com/3560
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Use the PyBind11 wrapping infrastructure instead of SWIG to generate
wrappers for functionality that needs to be exported to Python. This
has several benefits:
* PyBind11 can be redistributed with gem5, which means that we have
full control of the version used. This avoid a large number of
hard-to-debug SWIG issues we have seen in the past.
* PyBind11 doesn't rely on a custom C++ parser, instead it relies on
wrappers being explicitly declared in C++. The leads to slightly
more boiler-plate code in manually created wrappers, but doesn't
doesn't increase the overall code size. A big benefit is that this
avoids strange compilation errors when SWIG doesn't understand
modern language features.
* Unlike SWIG, there is no risk that the wrapper code incorporates
incorrect type casts (this has happened on numerous occasions in
the past) since these will result in compile-time errors.
As a part of this change, the mechanism to define exported methods has
been redesigned slightly. New methods can be exported either by
declaring them in the SimObject declaration and decorating them with
the cxxMethod decorator or by adding an instance of
PyBindMethod/PyBindProperty to the cxx_exports class variable. The
decorator has the added benefit of making it possible to add a
docstring and naming the method's parameters.
The new wrappers have the following known issues:
* Global events can't be memory managed correctly. This was the
case in SWIG as well.
Change-Id: I88c5a95b6cf6c32fa9e1ad31dfc08b2e8199a763
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Andrew Bardsley <andrew.bardsley@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2231
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The test sub-command in tests.py incorrectly accepts various
formatting options in its usage string. These options aren't needed
since the test command doesn't produce any output.
Change-Id: I6d4731aa32a25a2286aa66548eaa0154a9392f79
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2840
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Some of the functions in the Linux toolchain that allocate memory make
use of paired LR and SC instructions, which didn't work properly for
that toolchain. This patch fixes that so attempting to use those
functions doesn't cause an endless loop of failed SC instructions.
Change-Id: If27696323dd6229a0277818e3744fbdf7180fca7
Reviewed-on: https://gem5-review.googlesource.com/2340
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain
(riscv64-unknown-elf-*) due to incorrect assumptions made in the initial
setup of the user stack in SE mode. This patch fixes that by referring
to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and
setting up the stack according to how it does it. Now binaries compiled
using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as
well.
[Update for recent changes to MemState to add accessors and mutators to
get its members.]
Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285
Reviewed-on: https://gem5-review.googlesource.com/2305
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865f
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The following CL changed the stats:
commit 43418e7f81
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 13:07:43 2017 -0600
syscall-emul: Move memState into its own file
It would be a good idea to try to figure out why, since it doesn't *look* like
this change was intended to move things around in memory or otherwise change
simulated behavior.
Change-Id: I0173ffdfb680a91b8c91f2bf5d7f72c76e7a8b63
Reviewed-on: https://gem5-review.googlesource.com/2655
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The change below changed the stats for the o3 version of the 40.m5threads
regression.
commit 2367198921
Author: Brandon Potter <brandon.potter@amd.com>
Date: Mon Feb 27 14:10:15 2017 -0500
syscall_emul: [PATCH 15/22] add clone/execve for threading and
multiprocess simulations
Change-Id: I601c58d8d1453cf93f2065ea5816b63b553610e0
Reviewed-on: https://gem5-review.googlesource.com/2652
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The name of the stat was changed in the following change which broke all the
reference outputs.
commit 2367198921
Author: Brandon Potter <brandon.potter@amd.com>
Date: Mon Feb 27 14:10:15 2017 -0500
syscall_emul: [PATCH 15/22] add clone/execve for threading and
multiprocess simulations
Change-Id: Id98b085ccae098c50c434ad81a72beee46084f40
Reviewed-on: https://gem5-review.googlesource.com/2651
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The following change removed a write to an integer register when completing
a system call. This changed the reference statistics slightly.
commit 073cb26607
Author: Brandon Potter <brandon.potter@amd.com>
Date: Mon Feb 27 14:10:02 2017 -0500
syscall_emul: [patch 14/22] adds identifier system calls
Change-Id: I3bee42ab826dd9cbc49aab34340da57caf4f045d
Reviewed-on: https://gem5-review.googlesource.com/2650
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The change below introduced some new op classes which have their own stats,
and the counts the instructions used to be under have gone down.
commit 6c72c35519
Author: Fernando Endo <fernando.endo2@gmail.com>
Date: Sat Oct 15 14:58:45 2016 -0500
cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
Change-Id: Ifa3a279493f503585a7b2cbb2785b106e24184bb
Reviewed-on: https://gem5-review.googlesource.com/2648
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This was emptied accidentally by the CL below. A lot of other files were too,
but those were eventually refilled.
commit 62b6ff22ec
Author: Curtis Dunham <Curtis.Dunham@arm.com>
Date: Tue May 31 11:07:18 2016 +0100
stats: update for snoop filter tweak
Change-Id: I34aefca51a92a6a98f6a8fdbdab7106cc1fff171
Reviewed-on: https://gem5-review.googlesource.com/2641
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
With this change, the test script will output a warning when it reads
an incomplete (e.g., when a regression is still running) or corrupt
status file instead of throwing an exception. When the scipt is used
to show the results the corrupt file is skipped; when it is used to
test if all regressions run successfully it will return an error value
(2).
Change-Id: Ie7d9b457b200e3abc7ae6238e3efbf3d18cf4297
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2320
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
It's currently possible to change the log level in gem5 by tweaking a
set of global variables. These variables are currently exposed to
Python using SWIG. This mechanism is far from ideal for two reasons:
First, changing the log level requires that the Python world enables
or disables individual levels. Ideally, this should be a single call
where a log level is selected. Second, exporting global variables is
poorly supported by most Python frameworks. SWIG puts variables in
their own namespace and PyBind doesn't seem to support it at all.
This changeset refactors the logging code to create a more abstract
interface. Each log level is associated with an instance of a Logger
class. This class contains common functionality, an enable flag, and a
verbose flag.
Available LogLevels are described by the LogLevel class. Lower log
levels are used for more critical messages (PANIC being level 0) and
higher levels for less critical messages. The highest log level that
is printed is controlled by calling Logger:setLevel().
Change-Id: I31e44299d242d953197a8e62679250c91d6ef776
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The EIOProcess class was removed recently and it was the only other class
which derived from Process. Since every Process invocation is also a
LiveProcess invocation, it makes sense to simplify the organization by
combining the fields from LiveProcess into Process.
Names of DRAM configurations were updated to reflect both
the channel and device data width.
Previous naming format was:
<DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>
The following nomenclature is now used:
<DEVICE_TYPE>_<DATA_RATE>_<n>x<w>
where n = The number of devices per rank on the channel
x = Device width
Total channel width can be calculated by n*w
Example:
A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
n = 16
w = 4
The resulting configuration name is:
DDR4_2400_16x4
Updated scripts to match new naming convention.
Added unique configurations for DDR4 for:
1) 16x4
2) 8x8
3) 4x16
Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Provides a helpful error when tests.py is invoked without the gem5 binary.
Before:
Running 0 tests
After:
gem5 binary 'quick/...' not an executable file
Change-Id: I1566802206c9e21ca89bd03e91db22844168a085
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
The system calls tested in rv64i.cpp in RISC-V's insttest suite have
different behavior depending on the operating system and file system they
are run on. This patch ignores the output of those tests and only
ensures that the instructions in RV64I complete successfully.
[Change deletion of ECALL test to block comment.]
[Restore ECALL test but remove test output to test only for completion
without error.]
[Update patch description and again try to push EMPTY files for rv64i
tests.]
