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tests: Add tests for DRAM low power modes

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This patch adds two regression tests that execute the script in the
configs dir for triggering low power mode transitions. A separate
test is required for each page policy because for close-adaptive
page policy the DRAM goes into the Precharge Power-down mode while
for open-adaptive page policy it goes into the Activate Power-down
mode.

Change-Id: Iad61af23f132db046f2857cc3ef64b2bf42cf5e4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5726
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Radhika Jagtap
2016-12-16 16:55:37 +00:00
committed by Andreas Sandberg
parent b549de4707
commit 1695c9933b
15 changed files with 42073 additions and 1060 deletions
Download Patch File Download Diff File Expand all files Collapse all files

68
tests/configs/dram-lowp.py Normal file
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@@ -0,0 +1,68 @@
# Copyright (c) 2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2015 Jason Lowe-Power
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Radhika Jagtap
# Jason Lowe-Power
# Andreas Hansson
#
# A wrapper around configs/dram/low_power_sweep.py
# For some reason, this is implicitly needed by run.py
root = None
import m5
def run_test(root):
# Called from tests/run.py
# Set the working directory in case we are executing from
# outside gem5's source tree
import os
os.chdir(os.path.join(os.path.dirname(__file__), "../"))
# The path to this script is the only parameter. Delete it so
# we can execute the script that we want to execute.
import sys
del sys.argv[1:]
# Add a specific page policy and specify the number of ranks
sys.argv.append('-p%s' % page_policy)
sys.argv.append('-r 2')
# Execute the script we are wrapping
execfile(srcpath('configs/dram/low_power_sweep.py'), globals())

56
tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/config.ini
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@@ -80,30 +80,30 @@ transition_latency=100000
[system.mem_ctrls]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
IDD0=0.055
IDD02=0.0
IDD2N=0.032
IDD2N2=0.0
IDD2P0=0.0
IDD2P02=0.0
IDD2P1=0.032
IDD2P12=0.0
IDD3N=0.038
IDD3N2=0.0
IDD3P0=0.0
IDD3P02=0.0
IDD3P1=0.038
IDD3P12=0.0
IDD4R=0.157
IDD4R2=0.0
IDD4W=0.125
IDD4W2=0.0
IDD5=0.235
IDD52=0.0
IDD6=0.02
IDD62=0.0
VDD=1.5
VDD2=0.0
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
@@ -192,6 +192,7 @@ voltage_domain=system.voltage_domain
[system.ruby.dir_cntrl0]
type=Directory_Controller
children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory
addr_ranges=0:268435455:5:0:0:0
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
@@ -220,10 +221,8 @@ memory=system.mem_ctrls.port
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
addr_ranges=0:268435455:5:0:0:0
eventq_index=0
numa_high_bit=5
size=268435456
version=0
[system.ruby.dir_cntrl0.dmaRequestToDir]
type=MessageBuffer
@@ -275,6 +274,7 @@ randomization=false
[system.ruby.l1_cntrl0]
type=L1Cache_Controller
children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer
addr_ranges=0:18446744073709551615:0:0:0:0
buffer_size=0
cacheMemory=system.ruby.l1_cntrl0.cacheMemory
cache_response_latency=12
@@ -1187,5 +1187,5 @@ slave=system.system_port
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000
voltage=1.0

3
tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/simerr
View File

@@ -4,5 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
info: Entering event queue @ 0. Starting simulation...
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

13
tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/simout
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@@ -1,13 +1,12 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simerr
Redirecting stdout to build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby/simout
Redirecting stderr to build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:45
gem5 executing on e108600-lin, pid 28072
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby
gem5 compiled Nov 15 2017 18:28:23
gem5 started Nov 15 2017 18:28:28
gem5 executing on e108600-lin, pid 19889
command line: /work/andsan01/outgoing/gem5/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby --stats-file 'text://stats.txt?desc=False' -re /work/andsan01/outgoing/gem5/tests/testing/../run.py quick/se/60.rubytest/null/none/rubytest-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 39431 because Ruby Tester completed

710
tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/stats.txt
View File

@@ -1,287 +1,287 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000039 # Number of seconds simulated
sim_ticks 39431 # Number of ticks simulated
final_tick 39431 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_tick_rate 995299 # Simulator tick rate (ticks/s)
host_mem_usage 392160 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60224 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 60224 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 60032 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 60032 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 941 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 941 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 938 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 938 # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::ruby.dir_cntrl0 1527326215 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 1527326215 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 1522456950 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 1522456950 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 3049783166 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 3049783166 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 941 # Number of read requests accepted
system.mem_ctrls.writeReqs 938 # Number of write requests accepted
system.mem_ctrls.readBursts 941 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 938 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM 50560 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 9664 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 49728 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 60224 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 60032 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 151 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 134 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 259 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 247 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 238 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 46 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 258 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 243 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 232 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 44 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
system.mem_ctrls.totGap 39357 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 941 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 938 # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 461 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 328 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 36 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 47 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 48 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 49 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 49 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 52 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 49 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 49 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 49 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 51 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 67 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 48 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 48 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 48 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 48 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 48 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples 108 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 925.629630 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 827.187599 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 260.509945 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 4 3.70% 3.70% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 3 2.78% 6.48% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 2 1.85% 8.33% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 2 1.85% 10.19% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 1 0.93% 11.11% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 1 0.93% 12.04% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 1 0.93% 12.96% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 3 2.78% 15.74% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 91 84.26% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 108 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 48 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 16.229167 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 16.080832 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 2.837736 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::14-15 10 20.83% 20.83% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-17 37 77.08% 97.92% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::34-35 1 2.08% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 48 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 48 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean 16.187500 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 16.181743 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev 0.445127 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 40 83.33% 83.33% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::17 7 14.58% 97.92% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 1 2.08% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 48 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 14435 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 29445 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 3950 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 18.27 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat 37.27 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 1282.24 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 1261.14 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 1527.33 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 1522.46 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 19.87 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 10.02 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 9.85 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.68 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 25.86 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 690 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 766 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 87.34 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 95.27 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 20.95 # Average gap between requests
system.mem_ctrls.pageHitRate 91.34 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 792540 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 417312 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 9024960 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 6489504 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 9767064 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 64896 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.actPowerDownEnergy 8135040 # Energy for active power-down per rank (pJ)
system.mem_ctrls_0.prePowerDownEnergy 1152 # Energy for precharge power-down per rank (pJ)
system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.mem_ctrls_0.totalEnergy 37765668 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 957.765920 # Core power per rank (mW)
system.mem_ctrls_0.totalIdleTime 17819 # Total Idle time Per DRAM Rank
system.mem_ctrls_0.memoryStateTime::IDLE 29 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states
system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 3 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 20259 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 17840 # Time in different power states
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ)
system.mem_ctrls_1.selfRefreshEnergy 5662320 # Energy for self refresh per rank (pJ)
system.mem_ctrls_1.totalEnergy 13008816 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 329.913418 # Core power per rank (mW)
system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank
system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states
system.mem_ctrls_1.memoryStateTime::SREF 23593 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 1878 # delay histogram for all message
system.ruby.delayHist::mean 0.221512 # delay histogram for all message
system.ruby.delayHist::stdev 1.129790 # delay histogram for all message
system.ruby.delayHist | 1808 96.27% 96.27% | 0 0.00% 96.27% | 1 0.05% 96.33% | 0 0.00% 96.33% | 0 0.00% 96.33% | 0 0.00% 96.33% | 69 3.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 1878 # delay histogram for all message
sim_seconds 0.000039
sim_ticks 39431
final_tick 39431
sim_freq 1000000000
host_tick_rate 701018
host_mem_usage 390584
host_seconds 0.06
system.voltage_domain.voltage 1
system.clk_domain.clock 1
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 39431
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60224
system.mem_ctrls.bytes_read::total 60224
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 60032
system.mem_ctrls.bytes_written::total 60032
system.mem_ctrls.num_reads::ruby.dir_cntrl0 941
system.mem_ctrls.num_reads::total 941
system.mem_ctrls.num_writes::ruby.dir_cntrl0 938
system.mem_ctrls.num_writes::total 938
system.mem_ctrls.bw_read::ruby.dir_cntrl0 1527326215
system.mem_ctrls.bw_read::total 1527326215
system.mem_ctrls.bw_write::ruby.dir_cntrl0 1522456950
system.mem_ctrls.bw_write::total 1522456950
system.mem_ctrls.bw_total::ruby.dir_cntrl0 3049783166
system.mem_ctrls.bw_total::total 3049783166
system.mem_ctrls.readReqs 941
system.mem_ctrls.writeReqs 938
system.mem_ctrls.readBursts 941
system.mem_ctrls.writeBursts 938
system.mem_ctrls.bytesReadDRAM 50560
system.mem_ctrls.bytesReadWrQ 9664
system.mem_ctrls.bytesWritten 49728
system.mem_ctrls.bytesReadSys 60224
system.mem_ctrls.bytesWrittenSys 60032
system.mem_ctrls.servicedByWrQ 151
system.mem_ctrls.mergedWrBursts 134
system.mem_ctrls.neitherReadNorWriteReqs 0
system.mem_ctrls.perBankRdBursts::0 259
system.mem_ctrls.perBankRdBursts::1 247
system.mem_ctrls.perBankRdBursts::2 238
system.mem_ctrls.perBankRdBursts::3 46
system.mem_ctrls.perBankRdBursts::4 0
system.mem_ctrls.perBankRdBursts::5 0
system.mem_ctrls.perBankRdBursts::6 0
system.mem_ctrls.perBankRdBursts::7 0
system.mem_ctrls.perBankRdBursts::8 0
system.mem_ctrls.perBankRdBursts::9 0
system.mem_ctrls.perBankRdBursts::10 0
system.mem_ctrls.perBankRdBursts::11 0
system.mem_ctrls.perBankRdBursts::12 0
system.mem_ctrls.perBankRdBursts::13 0
system.mem_ctrls.perBankRdBursts::14 0
system.mem_ctrls.perBankRdBursts::15 0
system.mem_ctrls.perBankWrBursts::0 258
system.mem_ctrls.perBankWrBursts::1 243
system.mem_ctrls.perBankWrBursts::2 232
system.mem_ctrls.perBankWrBursts::3 44
system.mem_ctrls.perBankWrBursts::4 0
system.mem_ctrls.perBankWrBursts::5 0
system.mem_ctrls.perBankWrBursts::6 0
system.mem_ctrls.perBankWrBursts::7 0
system.mem_ctrls.perBankWrBursts::8 0
system.mem_ctrls.perBankWrBursts::9 0
system.mem_ctrls.perBankWrBursts::10 0
system.mem_ctrls.perBankWrBursts::11 0
system.mem_ctrls.perBankWrBursts::12 0
system.mem_ctrls.perBankWrBursts::13 0
system.mem_ctrls.perBankWrBursts::14 0
system.mem_ctrls.perBankWrBursts::15 0
system.mem_ctrls.numRdRetry 0
system.mem_ctrls.numWrRetry 0
system.mem_ctrls.totGap 39357
system.mem_ctrls.readPktSize::0 0
system.mem_ctrls.readPktSize::1 0
system.mem_ctrls.readPktSize::2 0
system.mem_ctrls.readPktSize::3 0
system.mem_ctrls.readPktSize::4 0
system.mem_ctrls.readPktSize::5 0
system.mem_ctrls.readPktSize::6 941
system.mem_ctrls.writePktSize::0 0
system.mem_ctrls.writePktSize::1 0
system.mem_ctrls.writePktSize::2 0
system.mem_ctrls.writePktSize::3 0
system.mem_ctrls.writePktSize::4 0
system.mem_ctrls.writePktSize::5 0
system.mem_ctrls.writePktSize::6 938
system.mem_ctrls.rdQLenPdf::0 461
system.mem_ctrls.rdQLenPdf::1 328
system.mem_ctrls.rdQLenPdf::2 1
system.mem_ctrls.rdQLenPdf::3 0
system.mem_ctrls.rdQLenPdf::4 0
system.mem_ctrls.rdQLenPdf::5 0
system.mem_ctrls.rdQLenPdf::6 0
system.mem_ctrls.rdQLenPdf::7 0
system.mem_ctrls.rdQLenPdf::8 0
system.mem_ctrls.rdQLenPdf::9 0
system.mem_ctrls.rdQLenPdf::10 0
system.mem_ctrls.rdQLenPdf::11 0
system.mem_ctrls.rdQLenPdf::12 0
system.mem_ctrls.rdQLenPdf::13 0
system.mem_ctrls.rdQLenPdf::14 0
system.mem_ctrls.rdQLenPdf::15 0
system.mem_ctrls.rdQLenPdf::16 0
system.mem_ctrls.rdQLenPdf::17 0
system.mem_ctrls.rdQLenPdf::18 0
system.mem_ctrls.rdQLenPdf::19 0
system.mem_ctrls.rdQLenPdf::20 0
system.mem_ctrls.rdQLenPdf::21 0
system.mem_ctrls.rdQLenPdf::22 0
system.mem_ctrls.rdQLenPdf::23 0
system.mem_ctrls.rdQLenPdf::24 0
system.mem_ctrls.rdQLenPdf::25 0
system.mem_ctrls.rdQLenPdf::26 0
system.mem_ctrls.rdQLenPdf::27 0
system.mem_ctrls.rdQLenPdf::28 0
system.mem_ctrls.rdQLenPdf::29 0
system.mem_ctrls.rdQLenPdf::30 0
system.mem_ctrls.rdQLenPdf::31 0
system.mem_ctrls.wrQLenPdf::0 1
system.mem_ctrls.wrQLenPdf::1 1
system.mem_ctrls.wrQLenPdf::2 1
system.mem_ctrls.wrQLenPdf::3 1
system.mem_ctrls.wrQLenPdf::4 1
system.mem_ctrls.wrQLenPdf::5 1
system.mem_ctrls.wrQLenPdf::6 1
system.mem_ctrls.wrQLenPdf::7 1
system.mem_ctrls.wrQLenPdf::8 1
system.mem_ctrls.wrQLenPdf::9 1
system.mem_ctrls.wrQLenPdf::10 1
system.mem_ctrls.wrQLenPdf::11 1
system.mem_ctrls.wrQLenPdf::12 1
system.mem_ctrls.wrQLenPdf::13 1
system.mem_ctrls.wrQLenPdf::14 1
system.mem_ctrls.wrQLenPdf::15 1
system.mem_ctrls.wrQLenPdf::16 2
system.mem_ctrls.wrQLenPdf::17 36
system.mem_ctrls.wrQLenPdf::18 47
system.mem_ctrls.wrQLenPdf::19 48
system.mem_ctrls.wrQLenPdf::20 49
system.mem_ctrls.wrQLenPdf::21 49
system.mem_ctrls.wrQLenPdf::22 52
system.mem_ctrls.wrQLenPdf::23 49
system.mem_ctrls.wrQLenPdf::24 49
system.mem_ctrls.wrQLenPdf::25 49
system.mem_ctrls.wrQLenPdf::26 51
system.mem_ctrls.wrQLenPdf::27 67
system.mem_ctrls.wrQLenPdf::28 48
system.mem_ctrls.wrQLenPdf::29 48
system.mem_ctrls.wrQLenPdf::30 48
system.mem_ctrls.wrQLenPdf::31 48
system.mem_ctrls.wrQLenPdf::32 48
system.mem_ctrls.wrQLenPdf::33 0
system.mem_ctrls.wrQLenPdf::34 0
system.mem_ctrls.wrQLenPdf::35 0
system.mem_ctrls.wrQLenPdf::36 0
system.mem_ctrls.wrQLenPdf::37 0
system.mem_ctrls.wrQLenPdf::38 0
system.mem_ctrls.wrQLenPdf::39 0
system.mem_ctrls.wrQLenPdf::40 0
system.mem_ctrls.wrQLenPdf::41 0
system.mem_ctrls.wrQLenPdf::42 0
system.mem_ctrls.wrQLenPdf::43 0
system.mem_ctrls.wrQLenPdf::44 0
system.mem_ctrls.wrQLenPdf::45 0
system.mem_ctrls.wrQLenPdf::46 0
system.mem_ctrls.wrQLenPdf::47 0
system.mem_ctrls.wrQLenPdf::48 0
system.mem_ctrls.wrQLenPdf::49 0
system.mem_ctrls.wrQLenPdf::50 0
system.mem_ctrls.wrQLenPdf::51 0
system.mem_ctrls.wrQLenPdf::52 0
system.mem_ctrls.wrQLenPdf::53 0
system.mem_ctrls.wrQLenPdf::54 0
system.mem_ctrls.wrQLenPdf::55 0
system.mem_ctrls.wrQLenPdf::56 0
system.mem_ctrls.wrQLenPdf::57 0
system.mem_ctrls.wrQLenPdf::58 0
system.mem_ctrls.wrQLenPdf::59 0
system.mem_ctrls.wrQLenPdf::60 0
system.mem_ctrls.wrQLenPdf::61 0
system.mem_ctrls.wrQLenPdf::62 0
system.mem_ctrls.wrQLenPdf::63 0
system.mem_ctrls.bytesPerActivate::samples 108
system.mem_ctrls.bytesPerActivate::mean 925.629630
system.mem_ctrls.bytesPerActivate::gmean 827.187599
system.mem_ctrls.bytesPerActivate::stdev 260.509945
system.mem_ctrls.bytesPerActivate::0-127 4 3.70% 3.70%
system.mem_ctrls.bytesPerActivate::128-255 3 2.78% 6.48%
system.mem_ctrls.bytesPerActivate::256-383 2 1.85% 8.33%
system.mem_ctrls.bytesPerActivate::384-511 2 1.85% 10.19%
system.mem_ctrls.bytesPerActivate::512-639 1 0.93% 11.11%
system.mem_ctrls.bytesPerActivate::640-767 1 0.93% 12.04%
system.mem_ctrls.bytesPerActivate::768-895 1 0.93% 12.96%
system.mem_ctrls.bytesPerActivate::896-1023 3 2.78% 15.74%
system.mem_ctrls.bytesPerActivate::1024-1151 91 84.26% 100.00%
system.mem_ctrls.bytesPerActivate::total 108
system.mem_ctrls.rdPerTurnAround::samples 48
system.mem_ctrls.rdPerTurnAround::mean 16.229167
system.mem_ctrls.rdPerTurnAround::gmean 16.080832
system.mem_ctrls.rdPerTurnAround::stdev 2.837736
system.mem_ctrls.rdPerTurnAround::14-15 10 20.83% 20.83%
system.mem_ctrls.rdPerTurnAround::16-17 37 77.08% 97.92%
system.mem_ctrls.rdPerTurnAround::34-35 1 2.08% 100.00%
system.mem_ctrls.rdPerTurnAround::total 48
system.mem_ctrls.wrPerTurnAround::samples 48
system.mem_ctrls.wrPerTurnAround::mean 16.187500
system.mem_ctrls.wrPerTurnAround::gmean 16.181743
system.mem_ctrls.wrPerTurnAround::stdev 0.445127
system.mem_ctrls.wrPerTurnAround::16 40 83.33% 83.33%
system.mem_ctrls.wrPerTurnAround::17 7 14.58% 97.92%
system.mem_ctrls.wrPerTurnAround::18 1 2.08% 100.00%
system.mem_ctrls.wrPerTurnAround::total 48
system.mem_ctrls.totQLat 14435
system.mem_ctrls.totMemAccLat 29445
system.mem_ctrls.totBusLat 3950
system.mem_ctrls.avgQLat 18.27
system.mem_ctrls.avgBusLat 5.00
system.mem_ctrls.avgMemAccLat 37.27
system.mem_ctrls.avgRdBW 1282.24
system.mem_ctrls.avgWrBW 1261.14
system.mem_ctrls.avgRdBWSys 1527.33
system.mem_ctrls.avgWrBWSys 1522.46
system.mem_ctrls.peakBW 12800.00
system.mem_ctrls.busUtil 19.87
system.mem_ctrls.busUtilRead 10.02
system.mem_ctrls.busUtilWrite 9.85
system.mem_ctrls.avgRdQLen 1.68
system.mem_ctrls.avgWrQLen 25.86
system.mem_ctrls.readRowHits 690
system.mem_ctrls.writeRowHits 766
system.mem_ctrls.readRowHitRate 87.34
system.mem_ctrls.writeRowHitRate 95.27
system.mem_ctrls.avgGap 20.95
system.mem_ctrls.pageHitRate 91.34
system.mem_ctrls_0.actEnergy 792540
system.mem_ctrls_0.preEnergy 417312
system.mem_ctrls_0.readEnergy 9024960
system.mem_ctrls_0.writeEnergy 6489504
system.mem_ctrls_0.refreshEnergy 3073200.000000
system.mem_ctrls_0.actBackEnergy 9767064
system.mem_ctrls_0.preBackEnergy 64896
system.mem_ctrls_0.actPowerDownEnergy 8135040
system.mem_ctrls_0.prePowerDownEnergy 1152
system.mem_ctrls_0.selfRefreshEnergy 0
system.mem_ctrls_0.totalEnergy 37765668
system.mem_ctrls_0.averagePower 957.765920
system.mem_ctrls_0.totalIdleTime 17819
system.mem_ctrls_0.memoryStateTime::IDLE 29
system.mem_ctrls_0.memoryStateTime::REF 1300
system.mem_ctrls_0.memoryStateTime::SREF 0
system.mem_ctrls_0.memoryStateTime::PRE_PDN 3
system.mem_ctrls_0.memoryStateTime::ACT 20259
system.mem_ctrls_0.memoryStateTime::ACT_PDN 17840
system.mem_ctrls_1.actEnergy 0
system.mem_ctrls_1.preEnergy 0
system.mem_ctrls_1.readEnergy 0
system.mem_ctrls_1.writeEnergy 0
system.mem_ctrls_1.refreshEnergy 1229280.000000
system.mem_ctrls_1.actBackEnergy 224352
system.mem_ctrls_1.preBackEnergy 3002880
system.mem_ctrls_1.actPowerDownEnergy 0
system.mem_ctrls_1.prePowerDownEnergy 2889984
system.mem_ctrls_1.selfRefreshEnergy 6214560
system.mem_ctrls_1.totalEnergy 13561056
system.mem_ctrls_1.averagePower 343.918643
system.mem_ctrls_1.totalIdleTime 7526
system.mem_ctrls_1.memoryStateTime::IDLE 7786
system.mem_ctrls_1.memoryStateTime::REF 526
system.mem_ctrls_1.memoryStateTime::SREF 23593
system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526
system.mem_ctrls_1.memoryStateTime::ACT 0
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0
system.pwrStateResidencyTicks::UNDEFINED 39431
system.cpu.pwrStateResidencyTicks::UNDEFINED 39431
system.ruby.clk_domain.clock 1
system.ruby.pwrStateResidencyTicks::UNDEFINED 39431
system.ruby.delayHist::bucket_size 1
system.ruby.delayHist::max_bucket 9
system.ruby.delayHist::samples 1878
system.ruby.delayHist::mean 0.221512
system.ruby.delayHist::stdev 1.129790
system.ruby.delayHist | 1808 96.27% 96.27% | 0 0.00% 96.27% | 1 0.05% 96.33% | 0 0.00% 96.33% | 0 0.00% 96.33% | 0 0.00% 96.33% | 69 3.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.delayHist::total 1878
system.ruby.outstanding_req_hist_seqr::bucket_size 2
system.ruby.outstanding_req_hist_seqr::max_bucket 19
system.ruby.outstanding_req_hist_seqr::samples 997
@@ -315,39 +315,39 @@ system.ruby.miss_latency_hist_seqr::stdev 106.107284
system.ruby.miss_latency_hist_seqr | 2 0.21% 0.21% | 7 0.74% 0.96% | 6 0.64% 1.60% | 71 7.55% 9.15% | 434 46.17% 55.32% | 354 37.66% 92.98% | 33 3.51% 96.49% | 33 3.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 940
system.ruby.Directory.incomplete_times_seqr 940
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.023788 # Average number of messages in buffer
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.997388 # Average number of cycles messages are stalled in this MB
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.047652 # Average number of messages in buffer
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 16.301050 # Average number of cycles messages are stalled in this MB
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.023864 # Average number of messages in buffer
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.998250 # Average number of cycles messages are stalled in this MB
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.047652 # Average number of messages in buffer
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.998276 # Average number of cycles messages are stalled in this MB
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.cacheMemory.demand_hits 42 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 941 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 983 # Number of cache demand accesses
system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.023788 # Average number of messages in buffer
system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 7.382152 # Average number of cycles messages are stalled in this MB
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 13.964749 # Average number of messages in buffer
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 523.362675 # Average number of cycles messages are stalled in this MB
system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.095303 # Average number of messages in buffer
system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999797 # Average number of cycles messages are stalled in this MB
system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.023839 # Average number of messages in buffer
system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.986686 # Average number of cycles messages are stalled in this MB
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 14 # Number of times a store aliased with a pending load
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 141 # Number of times a store aliased with a pending store
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 15 # Number of times a load aliased with a pending store
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.023788 # Average number of messages in buffer
system.ruby.network.routers0.port_buffers03.avg_stall_time 6.385068 # Average number of cycles messages are stalled in this MB
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.023839 # Average number of messages in buffer
system.ruby.network.routers0.port_buffers04.avg_stall_time 5.988740 # Average number of cycles messages are stalled in this MB
system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.261894 # Average number of messages in buffer
system.ruby.network.routers0.port_buffers07.avg_stall_time 11.303840 # Average number of cycles messages are stalled in this MB
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.023788
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.997388
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.047652
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 16.301050
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.023864
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.998250
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.047652
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.998276
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 39431
system.ruby.l1_cntrl0.cacheMemory.demand_hits 42
system.ruby.l1_cntrl0.cacheMemory.demand_misses 941
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 983
system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.023788
system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 7.382152
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 13.964749
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 523.362675
system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.095303
system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999797
system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.023839
system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.986686
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 39431
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 14
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 141
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 15
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 39431
system.ruby.memctrl_clk_domain.clock 3
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.023788
system.ruby.network.routers0.port_buffers03.avg_stall_time 6.385068
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.023839
system.ruby.network.routers0.port_buffers04.avg_stall_time 5.988740
system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.261894
system.ruby.network.routers0.port_buffers07.avg_stall_time 11.303840
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 39431
system.ruby.network.routers0.percent_links_utilized 11.905607
system.ruby.network.routers0.msg_count.Control::2 941
system.ruby.network.routers0.msg_count.Data::2 938
@@ -357,13 +357,13 @@ system.ruby.network.routers0.msg_bytes.Control::2 7528
system.ruby.network.routers0.msg_bytes.Data::2 67536
system.ruby.network.routers0.msg_bytes.Response_Data::4 67680
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7504
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.047652 # Average number of messages in buffer
system.ruby.network.routers1.port_buffers02.avg_stall_time 15.301709 # Average number of cycles messages are stalled in this MB
system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.029063 # Average number of messages in buffer
system.ruby.network.routers1.port_buffers06.avg_stall_time 2.396226 # Average number of cycles messages are stalled in this MB
system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.023864 # Average number of messages in buffer
system.ruby.network.routers1.port_buffers07.avg_stall_time 1.996450 # Average number of cycles messages are stalled in this MB
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.047652
system.ruby.network.routers1.port_buffers02.avg_stall_time 15.301709
system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.029063
system.ruby.network.routers1.port_buffers06.avg_stall_time 2.396226
system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.023864
system.ruby.network.routers1.port_buffers07.avg_stall_time 1.996450
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 39431
system.ruby.network.routers1.percent_links_utilized 11.910045
system.ruby.network.routers1.msg_count.Control::2 941
system.ruby.network.routers1.msg_count.Data::2 938
@@ -373,25 +373,25 @@ system.ruby.network.routers1.msg_bytes.Control::2 7528
system.ruby.network.routers1.msg_bytes.Data::2 67536
system.ruby.network.routers1.msg_bytes.Response_Data::4 67752
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7504
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.047652 # Average number of messages in buffer
system.ruby.network.int_link_buffers02.avg_stall_time 12.303383 # Average number of cycles messages are stalled in this MB
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.023788 # Average number of messages in buffer
system.ruby.network.int_link_buffers08.avg_stall_time 3.393513 # Average number of cycles messages are stalled in this MB
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.023864 # Average number of messages in buffer
system.ruby.network.int_link_buffers09.avg_stall_time 2.994598 # Average number of cycles messages are stalled in this MB
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.023788 # Average number of messages in buffer
system.ruby.network.int_link_buffers13.avg_stall_time 5.387934 # Average number of cycles messages are stalled in this MB
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.023839 # Average number of messages in buffer
system.ruby.network.int_link_buffers14.avg_stall_time 4.990744 # Average number of cycles messages are stalled in this MB
system.ruby.network.int_link_buffers17.avg_buf_msgs 0.047652 # Average number of messages in buffer
system.ruby.network.int_link_buffers17.avg_stall_time 14.302318 # Average number of cycles messages are stalled in this MB
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.023788 # Average number of messages in buffer
system.ruby.network.routers2.port_buffers03.avg_stall_time 4.390749 # Average number of cycles messages are stalled in this MB
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.023864 # Average number of messages in buffer
system.ruby.network.routers2.port_buffers04.avg_stall_time 3.992696 # Average number of cycles messages are stalled in this MB
system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.047652 # Average number of messages in buffer
system.ruby.network.routers2.port_buffers07.avg_stall_time 13.302876 # Average number of cycles messages are stalled in this MB
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.047652
system.ruby.network.int_link_buffers02.avg_stall_time 12.303383
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.023788
system.ruby.network.int_link_buffers08.avg_stall_time 3.393513
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.023864
system.ruby.network.int_link_buffers09.avg_stall_time 2.994598
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.023788
system.ruby.network.int_link_buffers13.avg_stall_time 5.387934
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.023839
system.ruby.network.int_link_buffers14.avg_stall_time 4.990744
system.ruby.network.int_link_buffers17.avg_buf_msgs 0.047652
system.ruby.network.int_link_buffers17.avg_stall_time 14.302318
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.023788
system.ruby.network.routers2.port_buffers03.avg_stall_time 4.390749
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.023864
system.ruby.network.routers2.port_buffers04.avg_stall_time 3.992696
system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.047652
system.ruby.network.routers2.port_buffers07.avg_stall_time 13.302876
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 39431
system.ruby.network.routers2.percent_links_utilized 11.907509
system.ruby.network.routers2.msg_count.Control::2 941
system.ruby.network.routers2.msg_count.Data::2 938
@@ -401,7 +401,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 7528
system.ruby.network.routers2.msg_bytes.Data::2 67536
system.ruby.network.routers2.msg_bytes.Response_Data::4 67680
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7504
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 39431
system.ruby.network.msg_count.Control 2823
system.ruby.network.msg_count.Data 2814
system.ruby.network.msg_count.Response_Data 2821
@@ -410,7 +410,7 @@ system.ruby.network.msg_byte.Control 22584
system.ruby.network.msg_byte.Data 202608
system.ruby.network.msg_byte.Response_Data 203112
system.ruby.network.msg_byte.Writeback_Control 22512
system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states
system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 39431
system.ruby.network.routers0.throttle0.link_utilization 11.913215
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 940
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 938
@@ -441,18 +441,18 @@ system.ruby.network.routers2.throttle1.msg_count.Control::2 941
system.ruby.network.routers2.throttle1.msg_count.Data::2 938
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 7528
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 67536
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 940 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 940 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 940 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::samples 938 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::mean 0.443497 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::stdev 1.567923 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 868 92.54% 92.54% | 0 0.00% 92.54% | 1 0.11% 92.64% | 0 0.00% 92.64% | 0 0.00% 92.64% | 0 0.00% 92.64% | 69 7.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 938 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_1::bucket_size 1
system.ruby.delayVCHist.vnet_1::max_bucket 9
system.ruby.delayVCHist.vnet_1::samples 940
system.ruby.delayVCHist.vnet_1 | 940 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.delayVCHist.vnet_1::total 940
system.ruby.delayVCHist.vnet_2::bucket_size 1
system.ruby.delayVCHist.vnet_2::max_bucket 9
system.ruby.delayVCHist.vnet_2::samples 938
system.ruby.delayVCHist.vnet_2::mean 0.443497
system.ruby.delayVCHist.vnet_2::stdev 1.567923
system.ruby.delayVCHist.vnet_2 | 868 92.54% 92.54% | 0 0.00% 92.54% | 1 0.11% 92.64% | 0 0.00% 92.64% | 0 0.00% 92.64% | 0 0.00% 92.64% | 69 7.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.delayVCHist.vnet_2::total 938
system.ruby.LD.latency_hist_seqr::bucket_size 128
system.ruby.LD.latency_hist_seqr::max_bucket 1279
system.ruby.LD.latency_hist_seqr::samples 51

52
tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
View File

@@ -57,12 +57,12 @@ voltage_domain=system.clk_domain.voltage_domain
[system.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000
voltage=1.0
[system.cpu]
type=TrafficGen
clk_domain=system.clk_domain
config_file=/work/curdun01/gem5-external.hg/tests/testing/../../tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
config_file=/work/andsan01/outgoing/gem5/tests/testing/../../tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
default_p_state=UNDEFINED
elastic_req=false
eventq_index=0
@@ -131,30 +131,30 @@ slave=system.cpu.port
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
IDD0=0.055
IDD02=0.0
IDD2N=0.032
IDD2N2=0.0
IDD2P0=0.0
IDD2P02=0.0
IDD2P1=0.032
IDD2P12=0.0
IDD3N=0.038
IDD3N2=0.0
IDD3P0=0.0
IDD3P02=0.0
IDD3P1=0.038
IDD3P12=0.0
IDD4R=0.157
IDD4R2=0.0
IDD4W=0.125
IDD4W2=0.0
IDD5=0.235
IDD52=0.0
IDD6=0.02
IDD62=0.0
VDD=1.5
VDD2=0.0
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0

1
tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simerr
View File

@@ -1 +1,2 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
info: Entering event queue @ 0. Starting simulation...

9
tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout
View File

@@ -3,11 +3,10 @@ Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 13 2016 20:37:50
gem5 started Oct 13 2016 20:38:05
gem5 executing on e108600-lin, pid 342
command line: /work/curdun01/gem5-external.hg/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.tgen/null/none/tgen-dram-ctrl
gem5 compiled Nov 15 2017 18:28:23
gem5 started Nov 15 2017 18:28:28
gem5 executing on e108600-lin, pid 19888
command line: /work/andsan01/outgoing/gem5/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl --stats-file 'text://stats.txt?desc=False' -re /work/andsan01/outgoing/gem5/tests/testing/../run.py quick/se/70.tgen/null/none/tgen-dram-ctrl
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 100000000000 because simulate() limit reached

1276
tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
View File

File diff suppressed because it is too large Load Diff

20407
tests/quick/se/80.dram-closepage/ref/null/none/dram-lowp/stats.txt Normal file
View File

File diff suppressed because it is too large Load Diff

38
tests/quick/se/80.dram-closepage/test.py Normal file
View File

@@ -0,0 +1,38 @@
# Copyright (c) 2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Radhika Jagtap
page_policy = 'close_adaptive'

20459
tests/quick/se/80.dram-openpage/ref/null/none/dram-lowp/stats.txt Normal file
View File

File diff suppressed because it is too large Load Diff

38
tests/quick/se/80.dram-openpage/test.py Normal file
View File

@@ -0,0 +1,38 @@
# Copyright (c) 2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Radhika Jagtap
page_policy = 'open_adaptive'

1
tests/testing/tests.py
View File

@@ -156,6 +156,7 @@ generic_configs = (
'memtest-filter',
'tgen-simple-mem',
'tgen-dram-ctrl',
'dram-lowp',
'learning-gem5-p1-simple',
'learning-gem5-p1-two-level',