arch-riscv,tests: Add insttests for RV64C
This patch adds instruction tests for the RV64C extension implementation. It also updates existing executables for the latest riscv-tools now that they are compatible. [Update for changes to parents.] Change-Id: Id4cfd966a8cae39b0d728b02849622fd00ee7e0e Reviewed-on: https://gem5-review.googlesource.com/3862 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Alec Roelke
@@ -27,9 +27,9 @@
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# Authors: Alec Roelke
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CXX=riscv64-unknown-linux-gnu-g++
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CFLAGS=--std=c++11 -O3 -static
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CFLAGS=-std=gnu++11 -O3 -static -march=rv64gc
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TARGETS=rv64i rv64m rv64a rv64f rv64d
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TARGETS=rv64i rv64m rv64a rv64f rv64d rv64c
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PREFIX=../../bin/riscv/linux
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BIN=insttest
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@@ -44,6 +44,7 @@ rv64m: rv64m.cpp
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rv64a: rv64a.cpp
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rv64f: rv64f.cpp
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rv64d: rv64d.cpp
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rv64c: rv64c.cpp
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clean:
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-rm $(PREFIX)-*/$(BIN)
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@@ -72,7 +72,6 @@ expect(const T& expected, std::function<T()> func,
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} else {
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cout << "\033[1;31mFAIL\033[0m (expected " << expected << "; found " <<
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result << ")" << endl;
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exit(1);
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}
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}
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256
tests/test-progs/insttest/src/riscv/rv64c.cpp
Normal file
256
tests/test-progs/insttest/src/riscv/rv64c.cpp
Normal file
@@ -0,0 +1,256 @@
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/*
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* Copyright (c) 2017 The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer;
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||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Alec Roelke
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*/
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#include <limits>
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#include "insttest.h"
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#include "rv64c.h"
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#include "rv64d.h"
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int main()
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{
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using namespace insttest;
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using namespace std;
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// C.LWSP
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expect<bool>(true, []{
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uint64_t lw = 0, lwsp = -1;
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int64_t i = 16;
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asm volatile("lw %0,%2(sp);"
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"c.lwsp %1,%2(sp);"
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: "=r" (lw), "=r" (lwsp)
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: "i" (i));
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return lw == lwsp;
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}, "c.lwsp");
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// C.LDSP
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expect<bool>(true, []{
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uint64_t ld = 0, ldsp = -1;
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int64_t i = 8;
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asm volatile("ld %0,%2(sp);"
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"c.ldsp %1,%2(sp);"
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: "=r" (ld), "=r" (ldsp)
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: "i" (i));
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return ld == ldsp;
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}, "c.ldsp");
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// C.FLDSP
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expect<bool>(true, []{
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double fld = 0.0, fldsp = -1.0;
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int64_t i = 32;
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asm volatile("fld %0,%2(sp);"
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"c.fldsp %1,%2(sp);"
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: "=f" (fld), "=f" (fldsp)
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: "i" (i));
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return D::bits(fld) == D::bits(fldsp);
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}, "c.fldsp");
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// C.SWSP
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expect<bool>(true, []{
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int64_t value = -1, result = 0;
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asm volatile("addi sp,sp,-8;"
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"c.swsp %1,8(sp);"
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"lw %0,8(sp);"
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"addi sp,sp,8;"
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: "=r" (result)
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: "r" (value)
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: "memory");
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return value == result;
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}, "c.swsp");
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// C.SDSP
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expect<bool>(true, []{
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int64_t value = -1, result = 0;
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asm volatile("addi sp,sp,-8;"
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"c.sdsp %1,8(sp);"
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"ld %0,8(sp);"
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"addi sp,sp,8;"
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: "=r" (result)
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: "r" (value)
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: "memory");
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return value == result;
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}, "c.sdsp");
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// C.FSDSP
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expect<bool>(true, []{
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double value = 0.1, result = numeric_limits<double>::signaling_NaN();
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asm volatile("addi sp,sp,-8;"
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"c.fsdsp %1,8(sp);"
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"fld %0,8(sp);"
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"addi sp,sp,8;"
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: "=f" (result)
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: "f" (value)
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: "memory");
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return value == result;
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}, "c.fsdsp");
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// C.LW, C.LD, C.FLD
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expect<int64_t>(458752,
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[]{return C::c_load<int32_t, int64_t>(0x00070000);},
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"c.lw, positive");
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expect<int64_t>(numeric_limits<int32_t>::min(),
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[]{return C::c_load<int32_t, int64_t>(0x80000000);},
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"c.lw, negative");
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expect<int64_t>(30064771072,
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[]{return C::c_load<int64_t, int64_t>(30064771072);}, "c.ld");
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expect<double>(3.1415926, []{return C::c_load<double, double>(3.1415926);},
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"c.fld");
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// C.SW, C.SD, C.FSD
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expect<uint32_t>(0xFFFFFFFF, []{return C::c_store<int32_t>(-1);}, "c.sw");
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expect<uint64_t>(-1, []{return C::c_store<int64_t>(-1);}, "c.sd");
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expect<double>(1.61803398875,
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[]{return C::c_store<double>(1.61803398875);}, "c.fsd");
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// C.J, C.JR, C.JALR
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expect<bool>(true, []{return C::c_j();}, "c.j");
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expect<bool>(true, []{return C::c_jr();}, "c.jr");
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expect<bool>(true, []{return C::c_jalr();}, "c.jalr");
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// C.BEQZ
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expect<bool>(true, []{return C::c_beqz(0);}, "c.beqz, zero");
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expect<bool>(false, []{return C::c_beqz(7);}, "c.beqz, not zero");
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// C.BNEZ
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expect<bool>(true, []{return C::c_bnez(15);}, "c.bnez, not zero");
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expect<bool>(false, []{return C::c_bnez(0);}, "c.bnez, zero");
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// C.LI
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expect<int64_t>(1, []{return C::c_li(1);}, "c.li");
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expect<int64_t>(-1, []{return C::c_li(-1);}, "c.li, sign extend");
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// C.LUI
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expect<int64_t>(4096, []{return C::c_lui(1);}, "c.lui");
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// Note that sign extension can't be tested here because apparently the
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// compiler doesn't allow the 6th (sign) bit of the immediate to be 1
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// C.ADDI
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expect<int64_t>(15, []{return C::c_addi(7, 8);}, "c.addi");
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// C.ADDIW
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expect<int64_t>(15, []{return C::c_addiw(8, 7);}, "c.addiw");
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expect<int64_t>(1, []{return C::c_addiw(0xFFFFFFFF, 2);},
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"c.addiw, overflow");
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expect<int64_t>(1, []{return C::c_addiw(0x100000001, 0);},
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"c.addiw, truncate");
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// C.ADDI16SP
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expect<bool>(true, []{
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uint64_t sp = 0, rd = 0;
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const int16_t i = 4;
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asm volatile("mv %0,sp;"
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"c.addi16sp sp,%2;"
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"mv %1,sp;"
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"mv sp,%0;"
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: "+r" (sp), "=r" (rd)
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: "i" (i*16));
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return rd == sp + i*16;
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}, "c.addi16sp");
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// C.ADDI4SPN
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expect<bool>(true, []{
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uint64_t sp = 0, rd = 0;
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const int16_t i = 3;
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asm volatile("mv %0,sp;"
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"c.addi4spn %1,sp,%2;"
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: "=r" (sp), "=r" (rd)
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: "i" (i*4));
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return rd == sp + i*4;
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}, "c.addi4spn");
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// C.SLLI
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expect<uint64_t>(16, []{return C::c_slli(1, 4);}, "c.slli");
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expect<uint64_t>(0, []{return C::c_slli(8, 61);}, "c.slli, overflow");
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// C.SRLI
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expect<uint64_t>(4, []{return C::c_srli(128, 5);}, "c.srli");
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expect<uint64_t>(0, []{return C::c_srli(128, 8);}, "c.srli, overflow");
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expect<uint64_t>(1, []{return C::c_srli(-1, 63);}, "c.srli, -1");
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// C.SRAI
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expect<uint64_t>(4, []{return C::c_srai(128, 5);}, "c.srai");
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expect<uint64_t>(0, []{return C::c_srai(128, 8);}, "c.srai, overflow");
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expect<uint64_t>(-1, []{return C::c_srai(-2, 63);}, "c.srai, -1");
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// C.ANDI
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expect<uint64_t>(0, []{return C::c_andi(-1, 0);}, "c.andi (0)");
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expect<uint64_t>(0x1234567812345678ULL,
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[]{return C::c_andi(0x1234567812345678ULL, -1);}, "c.andi (1)");
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// C.MV
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expect<int64_t>(1024, []{return C::c_mv(1024);}, "c.mv");
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// C.ADD
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expect<int64_t>(15, []{return C::c_add(10, 5);}, "c.add");
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// C.AND
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expect<uint64_t>(0, []{return C::c_and(-1, 0);}, "c.and (0)");
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expect<uint64_t>(0x1234567812345678ULL,
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[]{return C::c_and(0x1234567812345678ULL, -1);}, "c.and (-1)");
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// C.OR
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expect<uint64_t>(-1,
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[]{return C::c_or(0xAAAAAAAAAAAAAAAAULL,
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0x5555555555555555ULL);},
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"c.or (1)");
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expect<uint64_t>(0xAAAAAAAAAAAAAAAAULL,
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[]{return C::c_or(0xAAAAAAAAAAAAAAAAULL,
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0xAAAAAAAAAAAAAAAAULL);},
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"c.or (A)");
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// C.XOR
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expect<uint64_t>(-1,
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[]{return C::c_xor(0xAAAAAAAAAAAAAAAAULL,
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0x5555555555555555ULL);},
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"c.xor (1)");
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expect<uint64_t>(0,
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[]{return C::c_xor(0xAAAAAAAAAAAAAAAAULL,
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0xAAAAAAAAAAAAAAAAULL);},
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"c.xor (0)");
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// C.SUB
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expect<int64_t>(65535, []{return C::c_sub(65536, 1);}, "c.sub");
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// C.ADDW
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expect<int64_t>(1073742078, []{return C::c_addw(0x3FFFFFFF, 255);},
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"c.addw");
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expect<int64_t>(-1, []{return C::c_addw(0x7FFFFFFF, 0x80000000);},
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"c.addw, overflow");
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expect<int64_t>(65536, []{return C::c_addw(0xFFFFFFFF0000FFFFLL, 1);},
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"c.addw, truncate");
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// C.SUBW
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expect<int64_t>(65535, []{return C::c_subw(65536, 1);}, "c.subw");
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expect<int64_t>(-1, []{return C::c_subw(0x7FFFFFFF, 0x80000000);},
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"c.subw, \"overflow\"");
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expect<int64_t>(0,
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[]{return C::c_subw(0xAAAAAAAAFFFFFFFFULL,0x55555555FFFFFFFFULL);},
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"c.subw, truncate");
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}
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268
tests/test-progs/insttest/src/riscv/rv64c.h
Normal file
268
tests/test-progs/insttest/src/riscv/rv64c.h
Normal file
@@ -0,0 +1,268 @@
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/*
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* Copyright (c) 2017 The University of Virginia
|
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* All rights reserved.
|
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*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
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*
|
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* Authors: Alec Roelke
|
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*/
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#pragma once
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#include <cstdint>
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#include <type_traits>
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#include "insttest.h"
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#define CIOP(op, r, imm) asm volatile(op " %0,%1" : "+r" (r) : "i" (imm));
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#define CROP(op, rd, rs) asm volatile(op " %0,%1" : "+r" (rd) : "r" (rs))
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namespace C
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{
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inline int64_t
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c_li(const int8_t imm)
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{
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int64_t rd = 0;
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CIOP("c.li", rd, imm);
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return rd;
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}
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inline int64_t
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c_lui(const int8_t imm)
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{
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int64_t rd = 0;
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CIOP("c.lui", rd, imm);
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return rd;
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}
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inline int64_t
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c_addi(int64_t r, const int8_t imm)
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{
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CIOP("c.addi", r, imm);
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return r;
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}
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inline int64_t
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c_addiw(int64_t r, const int8_t imm)
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{
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CIOP("c.addiw", r, imm);
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return r;
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}
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inline uint64_t
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c_addi4spn(const int16_t imm)
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{
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uint64_t rd = 0;
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asm volatile("c.addi4spn %0,sp,%1" : "=r" (rd) : "i" (imm));
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return rd;
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}
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inline uint64_t
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c_slli(uint64_t r, uint8_t shamt)
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{
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CIOP("c.slli", r, shamt);
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return r;
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}
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inline uint64_t
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c_srli(uint64_t r, uint8_t shamt)
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{
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CIOP("c.srli", r, shamt);
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return r;
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}
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inline int64_t
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c_srai(int64_t r, uint8_t shamt)
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{
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CIOP("c.srai", r, shamt);
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return r;
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}
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inline uint64_t
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c_andi(uint64_t r, uint8_t imm)
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{
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CIOP("c.andi", r, imm);
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return r;
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}
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inline int64_t
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c_mv(int64_t rs)
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{
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int64_t rd = 0;
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CROP("c.mv", rd, rs);
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return rd;
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}
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inline int64_t
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c_add(int64_t rd, int64_t rs)
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{
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CROP("c.add", rd, rs);
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return rd;
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}
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inline uint64_t
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c_and(int64_t rd, int64_t rs)
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{
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CROP("c.and", rd, rs);
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return rd;
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}
|
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inline uint64_t
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c_or(int64_t rd, int64_t rs)
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{
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CROP("c.or", rd, rs);
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return rd;
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}
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inline uint64_t
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c_xor(int64_t rd, int64_t rs)
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{
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CROP("c.xor", rd, rs);
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return rd;
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}
|
||||
|
||||
inline int64_t
|
||||
c_sub(int64_t rd, int64_t rs)
|
||||
{
|
||||
CROP("c.sub", rd, rs);
|
||||
return rd;
|
||||
}
|
||||
|
||||
inline int64_t
|
||||
c_addw(int64_t rd, int64_t rs)
|
||||
{
|
||||
CROP("c.addw", rd, rs);
|
||||
return rd;
|
||||
}
|
||||
|
||||
inline int64_t
|
||||
c_subw(int64_t rd, int64_t rs)
|
||||
{
|
||||
CROP("c.subw", rd, rs);
|
||||
return rd;
|
||||
}
|
||||
|
||||
template<typename M, typename R> inline R
|
||||
c_load(M m)
|
||||
{
|
||||
R r = 0;
|
||||
switch (sizeof(M))
|
||||
{
|
||||
case 4:
|
||||
asm volatile("c.lw %0,0(%1)" : "=r" (r) : "r" (&m) : "memory");
|
||||
break;
|
||||
case 8:
|
||||
if (std::is_floating_point<M>::value)
|
||||
asm volatile("c.fld %0,0(%1)" : "=f" (r) : "r" (&m) : "memory");
|
||||
else
|
||||
asm volatile("c.ld %0,0(%1)" : "=r" (r) : "r" (&m) : "memory");
|
||||
break;
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
||||
template<typename M> inline M
|
||||
c_store(const M& rs)
|
||||
{
|
||||
M mem = 0;
|
||||
switch (sizeof(M))
|
||||
{
|
||||
case 4:
|
||||
asm volatile("c.sw %0,0(%1)" : : "r" (rs), "r" (&mem) : "memory");
|
||||
break;
|
||||
case 8:
|
||||
if (std::is_floating_point<M>::value)
|
||||
asm volatile("c.fsd %0,0(%1)" : : "f" (rs), "r" (&mem) : "memory");
|
||||
else
|
||||
asm volatile("c.sd %0,0(%1)" : : "r" (rs), "r" (&mem) : "memory");
|
||||
break;
|
||||
}
|
||||
return mem;
|
||||
}
|
||||
|
||||
inline bool
|
||||
c_j()
|
||||
{
|
||||
asm volatile goto("c.j %l[jallabel]" : : : : jallabel);
|
||||
return false;
|
||||
jallabel:
|
||||
return true;
|
||||
}
|
||||
|
||||
inline bool
|
||||
c_jr()
|
||||
{
|
||||
uint64_t a = 0;
|
||||
asm volatile("auipc %0,0;"
|
||||
"c.addi %0,12;"
|
||||
"c.jr %0;"
|
||||
"addi %0,zero,0;"
|
||||
"addi %0,%0,0;"
|
||||
: "+r" (a));
|
||||
return a > 0;
|
||||
}
|
||||
|
||||
inline bool
|
||||
c_jalr()
|
||||
{
|
||||
int64_t a = 0;
|
||||
asm volatile("auipc %0,0;"
|
||||
"c.addi %0,12;"
|
||||
"c.jalr %0;"
|
||||
"addi %0,zero,0;"
|
||||
"sub %0,ra,%0;"
|
||||
: "+r" (a)
|
||||
:
|
||||
: "ra");
|
||||
return a == -4;
|
||||
}
|
||||
|
||||
inline bool
|
||||
c_beqz(int64_t a)
|
||||
{
|
||||
asm volatile goto("c.beqz %0,%l[beqlabel]"
|
||||
:
|
||||
: "r" (a)
|
||||
:
|
||||
: beqlabel);
|
||||
return false;
|
||||
beqlabel:
|
||||
return true;
|
||||
}
|
||||
|
||||
inline bool
|
||||
c_bnez(int64_t a)
|
||||
{
|
||||
asm volatile goto("c.bnez %0,%l[beqlabel]"
|
||||
:
|
||||
: "r" (a)
|
||||
:
|
||||
: beqlabel);
|
||||
return false;
|
||||
beqlabel:
|
||||
return true;
|
||||
}
|
||||
|
||||
} // namespace C
|
||||
Reference in New Issue
Block a user