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arch-riscv: Add support for compressed extension RV64C

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This patch adds compatibility with the 64-bit compressed extension to
the RISC-V ISA, RV64C.  Current versions of the toolchain may use
compressed instructions in glibc by default, which can only be
overridden by recompiling the entire toolchain (simply adding
"-march=rv64g" or "-march=rv64imafd" when compiling a binary is not
sufficient to use uncompressed instructions in glibc functions in the
binary).

[Update diassembly generation for new RegId type.]
[Rebase onto master.]

Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4
Reviewed-on: https://gem5-review.googlesource.com/3860
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
This commit is contained in:
Alec Roelke
2017-06-14 17:33:29 -04:00
parent 63d4005a29
commit 7e6a35374a
10 changed files with 1908 additions and 1404 deletions
Download Patch File Download Diff File Expand all files Collapse all files

61
src/arch/riscv/decoder.cc
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@@ -1,5 +1,6 @@
/*
* Copyright (c) 2012 Google
* Copyright (c) The University of Virginia
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,13 +27,71 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
* Alec Roelke
*/
#include "arch/riscv/decoder.hh"
#include "arch/riscv/types.hh"
#include "debug/Decode.hh"
namespace RiscvISA
{
GenericISA::BasicDecodeCache Decoder::defaultCache;
void
Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
{
DPRINTF(Decode, "Getting bytes 0x%08x from address %#x\n",
inst, pc.pc());
bool aligned = pc.pc() % sizeof(MachInst) == 0;
if (mid) {
assert(!aligned);
emi |= (inst & 0xFFFF) << 16;
instDone = true;
} else {
MachInst instChunk = aligned ? inst & 0xFFFF :
(inst & 0xFFFF0000) >> 16;
if (aligned) {
emi = (inst & 0x3) < 0x3 ? instChunk : inst;
instDone = true;
} else {
emi = instChunk;
instDone = (instChunk & 0x3) < 0x3;
}
}
mid = !instDone;
}
StaticInstPtr
Decoder::decode(ExtMachInst mach_inst, Addr addr)
{
DPRINTF(Decode, "Decoding instruction 0x%08x at address %#x\n",
mach_inst, addr);
if (instMap.find(mach_inst) != instMap.end())
return instMap[mach_inst];
else {
StaticInstPtr si = decodeInst(mach_inst);
instMap[mach_inst] = si;
return si;
}
}
StaticInstPtr
Decoder::decode(RiscvISA::PCState &nextPC)
{
if (!instDone)
return nullptr;
instDone = false;
if ((emi & 0x3) < 0x3) {
nextPC.compressed(true);
nextPC.npc(nextPC.pc() + sizeof(MachInst)/2);
} else {
nextPC.compressed(false);
nextPC.npc(nextPC.pc() + sizeof(MachInst));
}
return decode(emi, nextPC.instAddr());
}
}

64
src/arch/riscv/decoder.hh
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@@ -1,5 +1,6 @@
/*
* Copyright (c) 2012 Google
* Copyright (c) 2017 The University of Virginia
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,16 +27,19 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
* Alec Roelke
*/
#ifndef __ARCH_RISCV_DECODER_HH__
#define __ARCH_RISCV_DECODER_HH__
#include "arch/generic/decode_cache.hh"
#include "arch/riscv/isa_traits.hh"
#include "arch/riscv/types.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "debug/Decode.hh"
namespace RiscvISA
{
@@ -43,73 +47,39 @@ namespace RiscvISA
class ISA;
class Decoder
{
private:
DecodeCache::InstMap instMap;
bool mid;
protected:
//The extended machine instruction being generated
ExtMachInst emi;
bool instDone;
public:
Decoder(ISA* isa = nullptr) : instDone(false)
Decoder(ISA* isa=nullptr)
: mid(false), emi(NoopMachInst), instDone(false)
{}
void
process()
{
}
void
reset()
{
instDone = false;
}
void process() {}
void reset() { instDone = false; }
//Use this to give data to the decoder. This should be used
//when there is control flow.
void
moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
{
emi = inst;
instDone = true;
}
bool
needMoreBytes()
{
return true;
}
bool
instReady()
{
return instDone;
}
void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
bool needMoreBytes() { return true; }
bool instReady() { return instDone; }
void takeOverFrom(Decoder *old) {}
protected:
/// A cache of decoded instruction objects.
static GenericISA::BasicDecodeCache defaultCache;
public:
StaticInstPtr decodeInst(ExtMachInst mach_inst);
/// Decode a machine instruction.
/// @param mach_inst The binary instruction to decode.
/// @retval A pointer to the corresponding StaticInst object.
StaticInstPtr
decode(ExtMachInst mach_inst, Addr addr)
{
return defaultCache.decode(this, mach_inst, addr);
}
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
StaticInstPtr
decode(RiscvISA::PCState &nextPC)
{
if (!instDone)
return nullptr;
instDone = false;
return decode(emi, nextPC.instAddr());
}
StaticInstPtr decode(RiscvISA::PCState &nextPC);
};
} // namespace RiscvISA

26
src/arch/riscv/isa/bitfields.isa
View File

@@ -35,8 +35,8 @@
// Bitfield definitions.
//
def bitfield OPCODE <6:0>;
def bitfield NONOPCODE <31:7>;
def bitfield QUADRANT <1:0>;
def bitfield OPCODE <6:2>;
// R-Type
def bitfield ALL <31:0>;
@@ -69,7 +69,7 @@ def bitfield BIMM12BITS10TO5 <30:25>;
// UJ-Type
def bitfield UJIMMBITS10TO1 <30:21>;
def bitfield UJIMMBIT11 <20>;
def bitfield UJIMMBIT11 <20>;
def bitfield UJIMMBITS19TO12 <19:12>;
// System
@@ -90,3 +90,23 @@ def bitfield FUNCT2 <26:25>;
def bitfield AMOFUNCT <31:27>;
def bitfield AQ <26>;
def bitfield RL <25>;
// Compressed
def bitfield COPCODE <15:13>;
def bitfield CFUNCT1 <12>;
def bitfield CFUNCT2HIGH <11:10>;
def bitfield CFUNCT2LOW <6:5>;
def bitfield RC1 <11:7>;
def bitfield RC2 <6:2>;
def bitfield RP1 <9:7>;
def bitfield RP2 <4:2>;
def bitfield FC1 <11:7>;
def bitfield FC2 <6:2>;
def bitfield FP2 <4:2>;
def bitfield CJUMPIMM <12:2>;
def bitfield CIMM8 <12:5>;
def bitfield CIMM6 <12:7>;
def bitfield CIMM5 <6:2>;
def bitfield CIMM3 <12:10>;
def bitfield CIMM2 <6:5>;
def bitfield CIMM1 <12>;

2967
src/arch/riscv/isa/decoder.isa
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File diff suppressed because it is too large Load Diff

102
src/arch/riscv/isa/formats/compressed.isa Normal file
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@@ -0,0 +1,102 @@
// -*- mode:c++ -*-
// Copyright (c) 2015 RISC-V Foundation
// Copyright (c) 2017 The University of Virginia
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Alec Roelke
output header {{
/**
* Base class for compressed operations that work only on registers
*/
class CompRegOp : public RiscvStaticInst
{
protected:
/// Constructor
CompRegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
: RiscvStaticInst(mnem, _machInst, __opClass)
{}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
registerName(_srcRegIdx[0]);
return ss.str();
}
}};
def format CROp(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};
def format CIOp(imm_code, code, *opt_flags) {{
regs = ['_destRegIdx[0]','_srcRegIdx[0]']
iop = InstObjParams(name, Name, 'ImmOp',
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
header_output = ImmDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = ImmExecute.subst(iop)
}};
def format CUIOp(imm_code, code, *opt_flags) {{
regs = ['_destRegIdx[0]','_srcRegIdx[0]']
iop = InstObjParams(name, Name, 'UImmOp',
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
header_output = ImmDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = ImmExecute.subst(iop)
}};
def format CompressedLoad(ldisp_code, memacc_code,
ea_code, mem_flags=[], inst_flags=[]) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ldisp_code, ea_code, memacc_code, mem_flags,
inst_flags, 'Load', exec_template_base='Load')
}};
def format CompressedStore(sdisp_code, memacc_code,
ea_code, mem_flags=[], inst_flags=[]) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, sdisp_code, ea_code, memacc_code, mem_flags,
inst_flags, 'Store', exec_template_base='Store')
}};

5
src/arch/riscv/isa/formats/formats.isa
View File

@@ -33,11 +33,14 @@
// Include the basic format
##include "basic.isa"
//Include the type formats
// Include the type formats
##include "standard.isa"
##include "mem.isa"
##include "fp.isa"
##include "amo.isa"
// Include formats for nonstandard extensions
##include "compressed.isa"
// Include the unknown
##include "unknown.isa"

41
src/arch/riscv/isa/formats/mem.isa
View File

@@ -46,11 +46,8 @@ output header {{
/// Constructor
Load(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: RiscvStaticInst(mnem, _machInst, __opClass), ldisp(IMM12)
{
if (IMMSIGN > 0)
ldisp |= ~((uint64_t)0xFFF);
}
: RiscvStaticInst(mnem, _machInst, __opClass), ldisp(0)
{}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -68,9 +65,9 @@ output header {{
/// Constructor
Store(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: RiscvStaticInst(mnem, _machInst, __opClass), sdisp(IMM5)
: RiscvStaticInst(mnem, _machInst, __opClass), sdisp(0)
{
sdisp |= IMM7 << 5;
sdisp = IMM5 | (IMM7 << 5);
if (IMMSIGN > 0)
sdisp |= ~((uint64_t)0xFFF);
}
@@ -143,6 +140,7 @@ def template LoadStoreConstructor {{
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
%(constructor)s;
%(offset_code)s;
}
}};
@@ -168,16 +166,17 @@ def template EACompExecute {{
}};
let {{
def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
base_class, postacc_code='', decode_template=BasicDecode,
def LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
inst_flags, base_class, postacc_code='', decode_template=BasicDecode,
exec_template_base=''):
# Make sure flags are in lists (convert to lists if not).
mem_flags = makeList(mem_flags)
inst_flags = makeList(inst_flags) # + ['IsNonSpeculative']
inst_flags = makeList(inst_flags)
iop = InstObjParams(name, Name, base_class,
{ 'ea_code':ea_code, 'memacc_code':memacc_code,
'postacc_code':postacc_code }, inst_flags)
{'offset_code': offset_code, 'ea_code': ea_code,
'memacc_code': memacc_code, 'postacc_code': postacc_code },
inst_flags)
if mem_flags:
mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
@@ -342,14 +341,24 @@ def template StoreCompleteAcc {{
def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[],
inst_flags=[]) {{
offset_code = """
ldisp = IMM12;
if (IMMSIGN > 0)
ldisp |= ~((uint64_t)0xFFF);
"""
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
'Load', exec_template_base='Load')
LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
inst_flags, 'Load', exec_template_base='Load')
}};
def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[],
inst_flags=[]) {{
offset_code = """
sdisp = IMM5 | (IMM7 << 5);
if (IMMSIGN > 0)
sdisp |= ~((uint64_t)0xFFF);
"""
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
'Store', exec_template_base='Store')
LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
inst_flags, 'Store', exec_template_base='Store')
}};

2
src/arch/riscv/isa/includes.isa
View File

@@ -65,6 +65,7 @@ output decoder {{
#include "sim/full_system.hh"
using namespace RiscvISA;
using namespace std;
}};
output exec {{
@@ -90,4 +91,5 @@ output exec {{
#include "sim/system.hh"
using namespace RiscvISA;
using namespace std;
}};

12
src/arch/riscv/isa/operands.isa
View File

@@ -49,6 +49,12 @@ def operands {{
'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2),
'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3),
'Rt': ('IntReg', 'ud', 'AMOTempReg', 'IsInteger', 4),
'Rc1': ('IntReg', 'ud', 'RC1', 'IsInteger', 2),
'Rc2': ('IntReg', 'ud', 'RC2', 'IsInteger', 3),
'Rp1': ('IntReg', 'ud', 'RP1 + 8', 'IsInteger', 2),
'Rp2': ('IntReg', 'ud', 'RP2 + 8', 'IsInteger', 3),
'ra': ('IntReg', 'ud', 'ReturnAddrReg', 'IsInteger', 1),
'sp': ('IntReg', 'ud', 'StackPointerReg', 'IsInteger', 2),
'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1),
@@ -58,6 +64,12 @@ def operands {{
'Fs2_bits': ('FloatReg', 'ud', 'FS2', 'IsFloating', 3),
'Fs3': ('FloatReg', 'df', 'FS3', 'IsFloating', 4),
'Fs3_bits': ('FloatReg', 'ud', 'FS3', 'IsFloating', 4),
'Fc1': ('FloatReg', 'df', 'FC1', 'IsFloating', 1),
'Fc1_bits': ('FloatReg', 'ud', 'FC1', 'IsFloating', 1),
'Fc2': ('FloatReg', 'df', 'FC2', 'IsFloatReg', 2),
'Fc2_bits': ('FloatReg', 'ud', 'FC2', 'IsFloating', 2),
'Fp2': ('FloatReg', 'df', 'FP2 + 8', 'IsFloating', 2),
'Fp2_bits': ('FloatReg', 'ud', 'FP2 + 8', 'IsFloating', 2),
#Memory Operand
'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5),

32
src/arch/riscv/types.hh
View File

@@ -12,7 +12,7 @@
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2016 The University of Virginia
* Copyright (c) 2017 The University of Virginia
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -50,11 +50,35 @@
namespace RiscvISA
{
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
typedef GenericISA::UPCState<MachInst> PCState;
class PCState : public GenericISA::UPCState<MachInst>
{
private:
bool _compressed;
public:
PCState() : UPCState() { _compressed = false; }
PCState(Addr val) : UPCState(val) { _compressed = false; }
void compressed(bool c) { _compressed = c; }
bool compressed() { return _compressed; }
bool
branching() const
{
if (_compressed) {
return npc() != pc() + sizeof(MachInst)/2 ||
nupc() != upc() + 1;
} else {
return npc() != pc() + sizeof(MachInst) ||
nupc() != upc() + 1;
}
}
};
}
#endif // __ARCH_RISCV_TYPES_HH__
#endif // __ARCH_RISCV_TYPES_HH__