stats: Add a boat load of stats to the SPARC solaris boot regression.
A large number of stats were added by the following change:
commit 5350879f49
Author: David Guillen Fandos <david.guillen@arm.com>
Date: Mon Jun 6 17:16:43 2016 +0100
pwr: Add power states to ClockedObject
Change-Id: Iec32bb7f701db0a09be26fe5ffb2812385f972c2
Reviewed-on: https://gem5-review.googlesource.com/2642
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Gabe Black
@@ -14,13 +14,14 @@ children=bridge clk_domain cpu cpu_clk_domain disk0 dvfs_handler hypervisor_desc
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boot_osflags=a
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cache_line_size=64
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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exit_on_work_items=false
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hypervisor_addr=1099243257856
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hypervisor_bin=/dist/m5/system/binaries/q_new.bin
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hypervisor_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin
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hypervisor_desc=system.hypervisor_desc
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hypervisor_desc_addr=133446500352
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hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
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hypervisor_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin
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init_param=0
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kernel=
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kernel_addr_check=true
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@@ -34,17 +35,22 @@ multi_thread=false
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num_work_ids=16
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nvram=system.nvram
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nvram_addr=133429198848
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nvram_bin=/dist/m5/system/binaries/nvram1
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nvram_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1
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openboot_addr=1099243716608
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openboot_bin=/dist/m5/system/binaries/openboot_new.bin
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openboot_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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partition_desc=system.partition_desc
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partition_desc_addr=133445976064
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partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
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readfile=/z/stever/hg/gem5/tests/halt.sh
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partition_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin
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readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
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reset_addr=1099243192320
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reset_bin=/dist/m5/system/binaries/reset_new.bin
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reset_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin
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rom=system.rom
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symbolfile=
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thermal_components=
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thermal_model=Null
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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@@ -57,8 +63,12 @@ system_port=system.membus.slave[0]
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[system.bridge]
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type=Bridge
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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delay=100
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eventq_index=0
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
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req_size=16
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resp_size=16
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@@ -80,6 +90,7 @@ branchPred=Null
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checker=Null
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clk_domain=system.cpu_clk_domain
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cpu_id=0
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default_p_state=UNDEFINED
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do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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@@ -96,6 +107,9 @@ max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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profile=0
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progress_interval=0
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simpoint_start_insts=
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@@ -144,8 +158,12 @@ voltage_domain=system.voltage_domain
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type=MmDisk
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children=image
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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image=system.disk0.image
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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pio_addr=134217728000
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pio_latency=200
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system=system
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@@ -163,7 +181,7 @@ table_size=65536
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[system.disk0.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/dist/m5/system/disks/disk.s10hw2
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image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2
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read_only=true
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[system.dvfs_handler]
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@@ -179,11 +197,15 @@ type=SimpleMemory
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bandwidth=0.000000
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clk_domain=system.clk_domain
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conf_table_reported=true
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default_p_state=UNDEFINED
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eventq_index=0
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in_addr_map=true
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latency=60
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latency_var=0
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null=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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range=133446500352:133446508543
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port=system.membus.master[5]
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@@ -195,9 +217,13 @@ sys=system
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[system.iobus]
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type=NoncoherentXBar
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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forward_latency=1
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frontend_latency=2
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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response_latency=2
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use_default_range=false
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width=16
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@@ -208,9 +234,14 @@ slave=system.bridge.master
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type=CoherentXBar
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children=badaddr_responder
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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forward_latency=4
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frontend_latency=3
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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point_of_coherency=true
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response_latency=2
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snoop_filter=Null
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snoop_response_latency=4
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@@ -224,8 +255,12 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
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[system.membus.badaddr_responder]
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type=IsaFake
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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fake_mem=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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pio_addr=0
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pio_latency=200
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pio_size=8
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@@ -244,11 +279,15 @@ type=SimpleMemory
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bandwidth=0.000000
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clk_domain=system.clk_domain
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conf_table_reported=true
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default_p_state=UNDEFINED
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eventq_index=0
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in_addr_map=true
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latency=60
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latency_var=0
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null=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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range=133429198848:133429207039
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port=system.membus.master[4]
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@@ -257,11 +296,15 @@ type=SimpleMemory
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bandwidth=0.000000
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clk_domain=system.clk_domain
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conf_table_reported=true
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default_p_state=UNDEFINED
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eventq_index=0
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in_addr_map=true
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latency=60
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latency_var=0
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null=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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range=133445976064:133445984255
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port=system.membus.master[6]
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@@ -270,11 +313,15 @@ type=SimpleMemory
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bandwidth=0.000000
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clk_domain=system.clk_domain
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conf_table_reported=true
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default_p_state=UNDEFINED
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eventq_index=0
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in_addr_map=true
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latency=60
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latency_var=0
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null=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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range=1048576:68157439
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port=system.membus.master[7]
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@@ -283,11 +330,15 @@ type=SimpleMemory
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bandwidth=0.000000
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clk_domain=system.clk_domain
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conf_table_reported=true
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default_p_state=UNDEFINED
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eventq_index=0
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in_addr_map=true
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latency=60
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latency_var=0
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null=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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range=2147483648:2415919103
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port=system.membus.master[8]
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@@ -296,11 +347,15 @@ type=SimpleMemory
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bandwidth=0.000000
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clk_domain=system.clk_domain
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conf_table_reported=true
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default_p_state=UNDEFINED
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eventq_index=0
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in_addr_map=true
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latency=60
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latency_var=0
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null=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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range=1099243192320:1099251580927
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port=system.membus.master[3]
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@@ -314,8 +369,12 @@ system=system
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[system.t1000.fake_clk]
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type=IsaFake
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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fake_mem=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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pio_addr=644245094400
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pio_latency=200
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pio_size=4294967296
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@@ -332,8 +391,12 @@ pio=system.iobus.master[0]
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[system.t1000.fake_jbi]
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type=IsaFake
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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fake_mem=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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pio_addr=549755813888
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pio_latency=200
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pio_size=4294967296
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@@ -350,8 +413,12 @@ pio=system.iobus.master[11]
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[system.t1000.fake_l2_1]
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type=IsaFake
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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fake_mem=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
|
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p_state_clk_gate_min=2
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pio_addr=725849473024
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pio_latency=200
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pio_size=8
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@@ -368,8 +435,12 @@ pio=system.iobus.master[2]
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[system.t1000.fake_l2_2]
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type=IsaFake
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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fake_mem=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
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p_state_clk_gate_min=2
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pio_addr=725849473088
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pio_latency=200
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pio_size=8
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@@ -386,8 +457,12 @@ pio=system.iobus.master[3]
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[system.t1000.fake_l2_3]
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type=IsaFake
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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fake_mem=false
|
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=2000000000
|
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p_state_clk_gate_min=2
|
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pio_addr=725849473152
|
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pio_latency=200
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pio_size=8
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@@ -404,8 +479,12 @@ pio=system.iobus.master[4]
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[system.t1000.fake_l2_4]
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type=IsaFake
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
|
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eventq_index=0
|
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fake_mem=false
|
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p_state_clk_gate_bins=20
|
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p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=725849473216
|
||||
pio_latency=200
|
||||
pio_size=8
|
||||
@@ -422,8 +501,12 @@ pio=system.iobus.master[5]
|
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[system.t1000.fake_l2esr_1]
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type=IsaFake
|
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clk_domain=system.clk_domain
|
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default_p_state=UNDEFINED
|
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eventq_index=0
|
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fake_mem=false
|
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p_state_clk_gate_bins=20
|
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p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
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pio_addr=734439407616
|
||||
pio_latency=200
|
||||
pio_size=8
|
||||
@@ -440,8 +523,12 @@ pio=system.iobus.master[6]
|
||||
[system.t1000.fake_l2esr_2]
|
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type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=734439407680
|
||||
pio_latency=200
|
||||
pio_size=8
|
||||
@@ -458,8 +545,12 @@ pio=system.iobus.master[7]
|
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[system.t1000.fake_l2esr_3]
|
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type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=734439407744
|
||||
pio_latency=200
|
||||
pio_size=8
|
||||
@@ -476,8 +567,12 @@ pio=system.iobus.master[8]
|
||||
[system.t1000.fake_l2esr_4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=734439407808
|
||||
pio_latency=200
|
||||
pio_size=8
|
||||
@@ -494,8 +589,12 @@ pio=system.iobus.master[9]
|
||||
[system.t1000.fake_membnks]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=648540061696
|
||||
pio_latency=200
|
||||
pio_size=16384
|
||||
@@ -512,8 +611,12 @@ pio=system.iobus.master[1]
|
||||
[system.t1000.fake_ssi]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=1095216660480
|
||||
pio_latency=200
|
||||
pio_size=268435456
|
||||
@@ -538,7 +641,11 @@ port=3456
|
||||
[system.t1000.htod]
|
||||
type=DumbTOD
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=1099255906296
|
||||
pio_latency=200
|
||||
system=system
|
||||
@@ -548,7 +655,11 @@ pio=system.membus.master[1]
|
||||
[system.t1000.hvuart]
|
||||
type=Uart8250
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=1099255955456
|
||||
pio_latency=200
|
||||
platform=system.t1000
|
||||
@@ -559,7 +670,11 @@ pio=system.iobus.master[13]
|
||||
[system.t1000.iob]
|
||||
type=Iob
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
system=system
|
||||
@@ -576,7 +691,11 @@ port=3456
|
||||
[system.t1000.puart0]
|
||||
type=Uart8250
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=2000000000
|
||||
p_state_clk_gate_min=2
|
||||
pio_addr=133412421632
|
||||
pio_latency=200
|
||||
platform=system.t1000
|
||||
|
||||
@@ -9,12 +9,16 @@
|
||||
"range": "1099243192320:1099251580927",
|
||||
"latency": 60,
|
||||
"name": "rom",
|
||||
"p_state_clk_gate_min": 2,
|
||||
"eventq_index": 0,
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"clk_domain": "system.clk_domain",
|
||||
"latency_var": 0,
|
||||
"bandwidth": "0.000000",
|
||||
"conf_table_reported": true,
|
||||
"cxx_class": "SimpleMemory",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"path": "system.rom",
|
||||
"null": false,
|
||||
"type": "SimpleMemory",
|
||||
@@ -37,6 +41,9 @@
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"name": "bridge",
|
||||
"p_state_clk_gate_min": 2,
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"cxx_class": "Bridge",
|
||||
"req_size": 16,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"delay": 100,
|
||||
@@ -45,12 +52,14 @@
|
||||
"peer": "system.iobus.slave[0]",
|
||||
"role": "MASTER"
|
||||
},
|
||||
"cxx_class": "Bridge",
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"path": "system.bridge",
|
||||
"resp_size": 16,
|
||||
"type": "Bridge"
|
||||
},
|
||||
"iobus": {
|
||||
"forward_latency": 1,
|
||||
"slave": {
|
||||
"peer": [
|
||||
"system.bridge.master"
|
||||
@@ -58,7 +67,9 @@
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"name": "iobus",
|
||||
"forward_latency": 1,
|
||||
"p_state_clk_gate_min": 2,
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"cxx_class": "NoncoherentXBar",
|
||||
"clk_domain": "system.clk_domain",
|
||||
"width": 16,
|
||||
"eventq_index": 0,
|
||||
@@ -83,7 +94,8 @@
|
||||
"role": "MASTER"
|
||||
},
|
||||
"response_latency": 2,
|
||||
"cxx_class": "NoncoherentXBar",
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"path": "system.iobus",
|
||||
"type": "NoncoherentXBar",
|
||||
"use_default_range": false,
|
||||
@@ -92,110 +104,130 @@
|
||||
"t1000": {
|
||||
"htod": {
|
||||
"name": "htod",
|
||||
"p_state_clk_gate_min": 2,
|
||||
"pio": {
|
||||
"peer": "system.membus.master[1]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"time": "Thu Jan 1 00:00:00 2009",
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"cxx_class": "DumbTOD",
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"cxx_class": "DumbTOD",
|
||||
"time": "Thu Jan 1 00:00:00 2009",
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"path": "system.t1000.htod",
|
||||
"pio_addr": 1099255906296,
|
||||
"type": "DumbTOD"
|
||||
},
|
||||
"puart0": {
|
||||
"name": "puart0",
|
||||
"p_state_clk_gate_min": 2,
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[12]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"cxx_class": "Uart8250",
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"system": "system",
|
||||
"terminal": "system.t1000.pterm",
|
||||
"platform": "system.t1000",
|
||||
"eventq_index": 0,
|
||||
"cxx_class": "Uart8250",
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"path": "system.t1000.puart0",
|
||||
"pio_addr": 133412421632,
|
||||
"type": "Uart8250"
|
||||
},
|
||||
"fake_membnks": {
|
||||
"system": "system",
|
||||
"ret_data8": 255,
|
||||
"name": "fake_membnks",
|
||||
"warn_access": "",
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[1]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"ret_bad_addr": false,
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"fake_mem": false,
|
||||
"pio_size": 16384,
|
||||
"ret_data32": 4294967295,
|
||||
"eventq_index": 0,
|
||||
"update_data": false,
|
||||
"ret_data64": 0,
|
||||
"fake_mem": false,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"cxx_class": "IsaFake",
|
||||
"path": "system.t1000.fake_membnks",
|
||||
"pio_addr": 648540061696,
|
||||
"update_data": false,
|
||||
"warn_access": "",
|
||||
"pio_latency": 200,
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"type": "IsaFake",
|
||||
"ret_data16": 65535
|
||||
"p_state_clk_gate_min": 2,
|
||||
"ret_data32": 4294967295,
|
||||
"path": "system.t1000.fake_membnks",
|
||||
"ret_data16": 65535,
|
||||
"ret_data8": 255,
|
||||
"name": "fake_membnks",
|
||||
"ret_bad_addr": false,
|
||||
"pio_size": 16384,
|
||||
"p_state_clk_gate_bins": 20
|
||||
},
|
||||
"cxx_class": "T1000",
|
||||
"fake_jbi": {
|
||||
"system": "system",
|
||||
"ret_data8": 255,
|
||||
"name": "fake_jbi",
|
||||
"warn_access": "",
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[11]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"ret_bad_addr": false,
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"fake_mem": false,
|
||||
"pio_size": 4294967296,
|
||||
"ret_data32": 4294967295,
|
||||
"eventq_index": 0,
|
||||
"update_data": false,
|
||||
"ret_data64": 18446744073709551615,
|
||||
"fake_mem": false,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"cxx_class": "IsaFake",
|
||||
"path": "system.t1000.fake_jbi",
|
||||
"pio_addr": 549755813888,
|
||||
"update_data": false,
|
||||
"warn_access": "",
|
||||
"pio_latency": 200,
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"type": "IsaFake",
|
||||
"ret_data16": 65535
|
||||
"p_state_clk_gate_min": 2,
|
||||
"ret_data32": 4294967295,
|
||||
"path": "system.t1000.fake_jbi",
|
||||
"ret_data16": 65535,
|
||||
"ret_data8": 255,
|
||||
"name": "fake_jbi",
|
||||
"ret_bad_addr": false,
|
||||
"pio_size": 4294967296,
|
||||
"p_state_clk_gate_bins": 20
|
||||
},
|
||||
"intrctrl": "system.intrctrl",
|
||||
"fake_l2esr_2": {
|
||||
"system": "system",
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2esr_2",
|
||||
"warn_access": "",
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[7]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"ret_bad_addr": false,
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"fake_mem": false,
|
||||
"pio_size": 8,
|
||||
"ret_data32": 4294967295,
|
||||
"eventq_index": 0,
|
||||
"update_data": true,
|
||||
"ret_data64": 0,
|
||||
"fake_mem": false,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"cxx_class": "IsaFake",
|
||||
"path": "system.t1000.fake_l2esr_2",
|
||||
"pio_addr": 734439407680,
|
||||
"update_data": true,
|
||||
"warn_access": "",
|
||||
"pio_latency": 200,
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"type": "IsaFake",
|
||||
"ret_data16": 65535
|
||||
"p_state_clk_gate_min": 2,
|
||||
"ret_data32": 4294967295,
|
||||
"path": "system.t1000.fake_l2esr_2",
|
||||
"ret_data16": 65535,
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2esr_2",
|
||||
"ret_bad_addr": false,
|
||||
"pio_size": 8,
|
||||
"p_state_clk_gate_bins": 20
|
||||
},
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
@@ -212,100 +244,116 @@
|
||||
},
|
||||
"type": "T1000",
|
||||
"fake_l2_4": {
|
||||
"system": "system",
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2_4",
|
||||
"warn_access": "",
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[5]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"ret_bad_addr": false,
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"fake_mem": false,
|
||||
"pio_size": 8,
|
||||
"ret_data32": 4294967295,
|
||||
"eventq_index": 0,
|
||||
"update_data": true,
|
||||
"ret_data64": 1,
|
||||
"fake_mem": false,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"cxx_class": "IsaFake",
|
||||
"path": "system.t1000.fake_l2_4",
|
||||
"pio_addr": 725849473216,
|
||||
"update_data": true,
|
||||
"warn_access": "",
|
||||
"pio_latency": 200,
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"type": "IsaFake",
|
||||
"ret_data16": 65535
|
||||
"p_state_clk_gate_min": 2,
|
||||
"ret_data32": 4294967295,
|
||||
"path": "system.t1000.fake_l2_4",
|
||||
"ret_data16": 65535,
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2_4",
|
||||
"ret_bad_addr": false,
|
||||
"pio_size": 8,
|
||||
"p_state_clk_gate_bins": 20
|
||||
},
|
||||
"fake_l2_1": {
|
||||
"system": "system",
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2_1",
|
||||
"warn_access": "",
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[2]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"ret_bad_addr": false,
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"fake_mem": false,
|
||||
"pio_size": 8,
|
||||
"ret_data32": 4294967295,
|
||||
"eventq_index": 0,
|
||||
"update_data": true,
|
||||
"ret_data64": 1,
|
||||
"fake_mem": false,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"cxx_class": "IsaFake",
|
||||
"path": "system.t1000.fake_l2_1",
|
||||
"pio_addr": 725849473024,
|
||||
"update_data": true,
|
||||
"warn_access": "",
|
||||
"pio_latency": 200,
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"type": "IsaFake",
|
||||
"ret_data16": 65535
|
||||
"p_state_clk_gate_min": 2,
|
||||
"ret_data32": 4294967295,
|
||||
"path": "system.t1000.fake_l2_1",
|
||||
"ret_data16": 65535,
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2_1",
|
||||
"ret_bad_addr": false,
|
||||
"pio_size": 8,
|
||||
"p_state_clk_gate_bins": 20
|
||||
},
|
||||
"fake_l2_2": {
|
||||
"system": "system",
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2_2",
|
||||
"warn_access": "",
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[3]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"ret_bad_addr": false,
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"fake_mem": false,
|
||||
"pio_size": 8,
|
||||
"ret_data32": 4294967295,
|
||||
"eventq_index": 0,
|
||||
"update_data": true,
|
||||
"ret_data64": 1,
|
||||
"fake_mem": false,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"cxx_class": "IsaFake",
|
||||
"path": "system.t1000.fake_l2_2",
|
||||
"pio_addr": 725849473088,
|
||||
"update_data": true,
|
||||
"warn_access": "",
|
||||
"pio_latency": 200,
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"type": "IsaFake",
|
||||
"ret_data16": 65535
|
||||
"p_state_clk_gate_min": 2,
|
||||
"ret_data32": 4294967295,
|
||||
"path": "system.t1000.fake_l2_2",
|
||||
"ret_data16": 65535,
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2_2",
|
||||
"ret_bad_addr": false,
|
||||
"pio_size": 8,
|
||||
"p_state_clk_gate_bins": 20
|
||||
},
|
||||
"fake_l2_3": {
|
||||
"system": "system",
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2_3",
|
||||
"warn_access": "",
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[4]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"ret_bad_addr": false,
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"fake_mem": false,
|
||||
"pio_size": 8,
|
||||
"ret_data32": 4294967295,
|
||||
"eventq_index": 0,
|
||||
"update_data": true,
|
||||
"ret_data64": 1,
|
||||
"fake_mem": false,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"cxx_class": "IsaFake",
|
||||
"path": "system.t1000.fake_l2_3",
|
||||
"pio_addr": 725849473152,
|
||||
"update_data": true,
|
||||
"warn_access": "",
|
||||
"pio_latency": 200,
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"type": "IsaFake",
|
||||
"ret_data16": 65535
|
||||
"p_state_clk_gate_min": 2,
|
||||
"ret_data32": 4294967295,
|
||||
"path": "system.t1000.fake_l2_3",
|
||||
"ret_data16": 65535,
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2_3",
|
||||
"ret_bad_addr": false,
|
||||
"pio_size": 8,
|
||||
"p_state_clk_gate_bins": 20
|
||||
},
|
||||
"pterm": {
|
||||
"name": "pterm",
|
||||
@@ -321,171 +369,203 @@
|
||||
"path": "system.t1000",
|
||||
"iob": {
|
||||
"name": "iob",
|
||||
"p_state_clk_gate_min": 2,
|
||||
"pio": {
|
||||
"peer": "system.membus.master[0]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"cxx_class": "Iob",
|
||||
"pio_latency": 2,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"system": "system",
|
||||
"platform": "system.t1000",
|
||||
"eventq_index": 0,
|
||||
"cxx_class": "Iob",
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"path": "system.t1000.iob",
|
||||
"type": "Iob"
|
||||
},
|
||||
"hvuart": {
|
||||
"name": "hvuart",
|
||||
"p_state_clk_gate_min": 2,
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[13]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"cxx_class": "Uart8250",
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"system": "system",
|
||||
"terminal": "system.t1000.hterm",
|
||||
"platform": "system.t1000",
|
||||
"eventq_index": 0,
|
||||
"cxx_class": "Uart8250",
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"path": "system.t1000.hvuart",
|
||||
"pio_addr": 1099255955456,
|
||||
"type": "Uart8250"
|
||||
},
|
||||
"name": "t1000",
|
||||
"fake_l2esr_3": {
|
||||
"system": "system",
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2esr_3",
|
||||
"warn_access": "",
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[8]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"ret_bad_addr": false,
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"fake_mem": false,
|
||||
"pio_size": 8,
|
||||
"ret_data32": 4294967295,
|
||||
"eventq_index": 0,
|
||||
"update_data": true,
|
||||
"ret_data64": 0,
|
||||
"fake_mem": false,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"cxx_class": "IsaFake",
|
||||
"path": "system.t1000.fake_l2esr_3",
|
||||
"pio_addr": 734439407744,
|
||||
"update_data": true,
|
||||
"warn_access": "",
|
||||
"pio_latency": 200,
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"type": "IsaFake",
|
||||
"ret_data16": 65535
|
||||
"p_state_clk_gate_min": 2,
|
||||
"ret_data32": 4294967295,
|
||||
"path": "system.t1000.fake_l2esr_3",
|
||||
"ret_data16": 65535,
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2esr_3",
|
||||
"ret_bad_addr": false,
|
||||
"pio_size": 8,
|
||||
"p_state_clk_gate_bins": 20
|
||||
},
|
||||
"fake_ssi": {
|
||||
"system": "system",
|
||||
"ret_data8": 255,
|
||||
"name": "fake_ssi",
|
||||
"warn_access": "",
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[10]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"ret_bad_addr": false,
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"fake_mem": false,
|
||||
"pio_size": 268435456,
|
||||
"ret_data32": 4294967295,
|
||||
"eventq_index": 0,
|
||||
"update_data": false,
|
||||
"ret_data64": 18446744073709551615,
|
||||
"fake_mem": false,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"cxx_class": "IsaFake",
|
||||
"path": "system.t1000.fake_ssi",
|
||||
"pio_addr": 1095216660480,
|
||||
"update_data": false,
|
||||
"warn_access": "",
|
||||
"pio_latency": 200,
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"type": "IsaFake",
|
||||
"ret_data16": 65535
|
||||
"p_state_clk_gate_min": 2,
|
||||
"ret_data32": 4294967295,
|
||||
"path": "system.t1000.fake_ssi",
|
||||
"ret_data16": 65535,
|
||||
"ret_data8": 255,
|
||||
"name": "fake_ssi",
|
||||
"ret_bad_addr": false,
|
||||
"pio_size": 268435456,
|
||||
"p_state_clk_gate_bins": 20
|
||||
},
|
||||
"fake_l2esr_1": {
|
||||
"system": "system",
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2esr_1",
|
||||
"warn_access": "",
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[6]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"ret_bad_addr": false,
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"fake_mem": false,
|
||||
"pio_size": 8,
|
||||
"ret_data32": 4294967295,
|
||||
"eventq_index": 0,
|
||||
"update_data": true,
|
||||
"ret_data64": 0,
|
||||
"fake_mem": false,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"cxx_class": "IsaFake",
|
||||
"path": "system.t1000.fake_l2esr_1",
|
||||
"pio_addr": 734439407616,
|
||||
"update_data": true,
|
||||
"warn_access": "",
|
||||
"pio_latency": 200,
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"type": "IsaFake",
|
||||
"ret_data16": 65535
|
||||
"p_state_clk_gate_min": 2,
|
||||
"ret_data32": 4294967295,
|
||||
"path": "system.t1000.fake_l2esr_1",
|
||||
"ret_data16": 65535,
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2esr_1",
|
||||
"ret_bad_addr": false,
|
||||
"pio_size": 8,
|
||||
"p_state_clk_gate_bins": 20
|
||||
},
|
||||
"fake_l2esr_4": {
|
||||
"system": "system",
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2esr_4",
|
||||
"warn_access": "",
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[9]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"ret_bad_addr": false,
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"fake_mem": false,
|
||||
"pio_size": 8,
|
||||
"ret_data32": 4294967295,
|
||||
"eventq_index": 0,
|
||||
"update_data": true,
|
||||
"ret_data64": 0,
|
||||
"fake_mem": false,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"cxx_class": "IsaFake",
|
||||
"path": "system.t1000.fake_l2esr_4",
|
||||
"pio_addr": 734439407808,
|
||||
"update_data": true,
|
||||
"warn_access": "",
|
||||
"pio_latency": 200,
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"type": "IsaFake",
|
||||
"ret_data16": 65535
|
||||
"p_state_clk_gate_min": 2,
|
||||
"ret_data32": 4294967295,
|
||||
"path": "system.t1000.fake_l2esr_4",
|
||||
"ret_data16": 65535,
|
||||
"ret_data8": 255,
|
||||
"name": "fake_l2esr_4",
|
||||
"ret_bad_addr": false,
|
||||
"pio_size": 8,
|
||||
"p_state_clk_gate_bins": 20
|
||||
},
|
||||
"fake_clk": {
|
||||
"system": "system",
|
||||
"ret_data8": 255,
|
||||
"name": "fake_clk",
|
||||
"warn_access": "",
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[0]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"ret_bad_addr": false,
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"fake_mem": false,
|
||||
"pio_size": 4294967296,
|
||||
"ret_data32": 4294967295,
|
||||
"eventq_index": 0,
|
||||
"update_data": false,
|
||||
"ret_data64": 18446744073709551615,
|
||||
"fake_mem": false,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"cxx_class": "IsaFake",
|
||||
"path": "system.t1000.fake_clk",
|
||||
"pio_addr": 644245094400,
|
||||
"update_data": false,
|
||||
"warn_access": "",
|
||||
"pio_latency": 200,
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"type": "IsaFake",
|
||||
"ret_data16": 65535
|
||||
"p_state_clk_gate_min": 2,
|
||||
"ret_data32": 4294967295,
|
||||
"path": "system.t1000.fake_clk",
|
||||
"ret_data16": 65535,
|
||||
"ret_data8": 255,
|
||||
"name": "fake_clk",
|
||||
"ret_bad_addr": false,
|
||||
"pio_size": 4294967296,
|
||||
"p_state_clk_gate_bins": 20
|
||||
}
|
||||
},
|
||||
"partition_desc_addr": 133445976064,
|
||||
"symbolfile": "",
|
||||
"readfile": "/z/stever/hg/gem5/tests/halt.sh",
|
||||
"readfile": "/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh",
|
||||
"thermal_model": null,
|
||||
"hypervisor_addr": 1099243257856,
|
||||
"mem_ranges": [
|
||||
"1048576:68157439",
|
||||
"2147483648:2415919103"
|
||||
],
|
||||
"cxx_class": "SparcSystem",
|
||||
"work_begin_cpu_id_exit": -1,
|
||||
"load_offset": 0,
|
||||
"reset_bin": "/dist/m5/system/binaries/reset_new.bin",
|
||||
"openboot_addr": 1099243716608,
|
||||
"reset_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin",
|
||||
"work_end_ckpt_count": 0,
|
||||
"work_begin_exit_count": 0,
|
||||
"openboot_addr": 1099243716608,
|
||||
"p_state_clk_gate_min": 2,
|
||||
"nvram_addr": 133429198848,
|
||||
"memories": [
|
||||
"system.hypervisor_desc",
|
||||
@@ -500,12 +580,16 @@
|
||||
"range": "133445976064:133445984255",
|
||||
"latency": 60,
|
||||
"name": "partition_desc",
|
||||
"p_state_clk_gate_min": 2,
|
||||
"eventq_index": 0,
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"clk_domain": "system.clk_domain",
|
||||
"latency_var": 0,
|
||||
"bandwidth": "0.000000",
|
||||
"conf_table_reported": true,
|
||||
"cxx_class": "SimpleMemory",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"path": "system.partition_desc",
|
||||
"null": false,
|
||||
"type": "SimpleMemory",
|
||||
@@ -532,12 +616,16 @@
|
||||
"range": "133446500352:133446508543",
|
||||
"latency": 60,
|
||||
"name": "hypervisor_desc",
|
||||
"p_state_clk_gate_min": 2,
|
||||
"eventq_index": 0,
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"clk_domain": "system.clk_domain",
|
||||
"latency_var": 0,
|
||||
"bandwidth": "0.000000",
|
||||
"conf_table_reported": true,
|
||||
"cxx_class": "SimpleMemory",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"path": "system.hypervisor_desc",
|
||||
"null": false,
|
||||
"type": "SimpleMemory",
|
||||
@@ -548,49 +636,44 @@
|
||||
"in_addr_map": true
|
||||
},
|
||||
"membus": {
|
||||
"default": {
|
||||
"peer": "system.membus.badaddr_responder.pio",
|
||||
"role": "MASTER"
|
||||
},
|
||||
"slave": {
|
||||
"peer": [
|
||||
"system.system_port",
|
||||
"system.cpu.icache_port",
|
||||
"system.cpu.dcache_port"
|
||||
],
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"name": "membus",
|
||||
"point_of_coherency": true,
|
||||
"system": "system",
|
||||
"response_latency": 2,
|
||||
"cxx_class": "CoherentXBar",
|
||||
"badaddr_responder": {
|
||||
"system": "system",
|
||||
"ret_data8": 255,
|
||||
"name": "badaddr_responder",
|
||||
"warn_access": "",
|
||||
"pio": {
|
||||
"peer": "system.membus.default",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"ret_bad_addr": true,
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"fake_mem": false,
|
||||
"pio_size": 8,
|
||||
"ret_data32": 4294967295,
|
||||
"eventq_index": 0,
|
||||
"update_data": false,
|
||||
"ret_data64": 18446744073709551615,
|
||||
"fake_mem": false,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"cxx_class": "IsaFake",
|
||||
"path": "system.membus.badaddr_responder",
|
||||
"pio_addr": 0,
|
||||
"update_data": false,
|
||||
"warn_access": "",
|
||||
"pio_latency": 200,
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"type": "IsaFake",
|
||||
"ret_data16": 65535
|
||||
"p_state_clk_gate_min": 2,
|
||||
"ret_data32": 4294967295,
|
||||
"path": "system.membus.badaddr_responder",
|
||||
"ret_data16": 65535,
|
||||
"ret_data8": 255,
|
||||
"name": "badaddr_responder",
|
||||
"ret_bad_addr": true,
|
||||
"pio_size": 8,
|
||||
"p_state_clk_gate_bins": 20
|
||||
},
|
||||
"snoop_filter": null,
|
||||
"forward_latency": 4,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"system": "system",
|
||||
"width": 16,
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"master": {
|
||||
"peer": [
|
||||
"system.t1000.iob.pio",
|
||||
@@ -605,24 +688,42 @@
|
||||
],
|
||||
"role": "MASTER"
|
||||
},
|
||||
"response_latency": 2,
|
||||
"cxx_class": "CoherentXBar",
|
||||
"type": "CoherentXBar",
|
||||
"frontend_latency": 3,
|
||||
"slave": {
|
||||
"peer": [
|
||||
"system.system_port",
|
||||
"system.cpu.icache_port",
|
||||
"system.cpu.dcache_port"
|
||||
],
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"p_state_clk_gate_min": 2,
|
||||
"snoop_filter": null,
|
||||
"path": "system.membus",
|
||||
"snoop_response_latency": 4,
|
||||
"type": "CoherentXBar",
|
||||
"use_default_range": false,
|
||||
"frontend_latency": 3
|
||||
"name": "membus",
|
||||
"default": {
|
||||
"peer": "system.membus.badaddr_responder.pio",
|
||||
"role": "MASTER"
|
||||
},
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"use_default_range": false
|
||||
},
|
||||
"nvram": {
|
||||
"range": "133429198848:133429207039",
|
||||
"latency": 60,
|
||||
"name": "nvram",
|
||||
"p_state_clk_gate_min": 2,
|
||||
"eventq_index": 0,
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"clk_domain": "system.clk_domain",
|
||||
"latency_var": 0,
|
||||
"bandwidth": "0.000000",
|
||||
"conf_table_reported": true,
|
||||
"cxx_class": "SimpleMemory",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"path": "system.nvram",
|
||||
"null": false,
|
||||
"type": "SimpleMemory",
|
||||
@@ -633,7 +734,8 @@
|
||||
"in_addr_map": true
|
||||
},
|
||||
"eventq_index": 0,
|
||||
"work_begin_cpu_id_exit": -1,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"dvfs_handler": {
|
||||
"enable": false,
|
||||
"name": "dvfs_handler",
|
||||
@@ -646,8 +748,8 @@
|
||||
"type": "DVFSHandler"
|
||||
},
|
||||
"work_end_exit_count": 0,
|
||||
"hypervisor_desc_bin": "/dist/m5/system/binaries/1up-hv.bin",
|
||||
"openboot_bin": "/dist/m5/system/binaries/openboot_new.bin",
|
||||
"hypervisor_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin",
|
||||
"openboot_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin",
|
||||
"voltage_domain": {
|
||||
"name": "voltage_domain",
|
||||
"eventq_index": 0,
|
||||
@@ -669,12 +771,16 @@
|
||||
"range": "1048576:68157439",
|
||||
"latency": 60,
|
||||
"name": "physmem0",
|
||||
"p_state_clk_gate_min": 2,
|
||||
"eventq_index": 0,
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"clk_domain": "system.clk_domain",
|
||||
"latency_var": 0,
|
||||
"bandwidth": "0.000000",
|
||||
"conf_table_reported": true,
|
||||
"cxx_class": "SimpleMemory",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"path": "system.physmem0",
|
||||
"null": false,
|
||||
"type": "SimpleMemory",
|
||||
@@ -688,12 +794,16 @@
|
||||
"range": "2147483648:2415919103",
|
||||
"latency": 60,
|
||||
"name": "physmem1",
|
||||
"p_state_clk_gate_min": 2,
|
||||
"eventq_index": 0,
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"clk_domain": "system.clk_domain",
|
||||
"latency_var": 0,
|
||||
"bandwidth": "0.000000",
|
||||
"conf_table_reported": true,
|
||||
"cxx_class": "SimpleMemory",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"path": "system.physmem1",
|
||||
"null": false,
|
||||
"type": "SimpleMemory",
|
||||
@@ -705,9 +815,9 @@
|
||||
}
|
||||
],
|
||||
"work_cpus_ckpt_count": 0,
|
||||
"work_begin_exit_count": 0,
|
||||
"thermal_components": [],
|
||||
"path": "system",
|
||||
"hypervisor_bin": "/dist/m5/system/binaries/q_new.bin",
|
||||
"hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin",
|
||||
"cpu_clk_domain": {
|
||||
"name": "cpu_clk_domain",
|
||||
"clock": [
|
||||
@@ -721,12 +831,12 @@
|
||||
"type": "SrcClockDomain",
|
||||
"domain_id": -1
|
||||
},
|
||||
"nvram_bin": "/dist/m5/system/binaries/nvram1",
|
||||
"nvram_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1",
|
||||
"mem_mode": "atomic",
|
||||
"name": "system",
|
||||
"init_param": 0,
|
||||
"type": "SparcSystem",
|
||||
"partition_desc_bin": "/dist/m5/system/binaries/1up-md.bin",
|
||||
"partition_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin",
|
||||
"load_addr_mask": 1099511627775,
|
||||
"cpu": {
|
||||
"do_statistics_insts": true,
|
||||
@@ -751,6 +861,8 @@
|
||||
"width": 1,
|
||||
"checker": null,
|
||||
"eventq_index": 0,
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"do_quiesce": true,
|
||||
"type": "AtomicSimpleCPU",
|
||||
"fastmem": false,
|
||||
@@ -759,6 +871,8 @@
|
||||
"peer": "system.membus.slave[1]",
|
||||
"role": "MASTER"
|
||||
},
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"p_state_clk_gate_min": 2,
|
||||
"interrupts": [
|
||||
{
|
||||
"eventq_index": 0,
|
||||
@@ -819,10 +933,12 @@
|
||||
},
|
||||
"disk0": {
|
||||
"name": "disk0",
|
||||
"p_state_clk_gate_min": 2,
|
||||
"pio": {
|
||||
"peer": "system.iobus.master[14]",
|
||||
"role": "SLAVE"
|
||||
},
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"image": {
|
||||
"read_only": false,
|
||||
"name": "image",
|
||||
@@ -834,7 +950,7 @@
|
||||
"eventq_index": 0,
|
||||
"cxx_class": "RawDiskImage",
|
||||
"path": "system.disk0.image.child",
|
||||
"image_file": "/dist/m5/system/disks/disk.s10hw2",
|
||||
"image_file": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2",
|
||||
"type": "RawDiskImage"
|
||||
},
|
||||
"path": "system.disk0.image",
|
||||
@@ -842,17 +958,20 @@
|
||||
"type": "CowDiskImage",
|
||||
"table_size": 65536
|
||||
},
|
||||
"cxx_class": "MmDisk",
|
||||
"pio_latency": 200,
|
||||
"clk_domain": "system.clk_domain",
|
||||
"system": "system",
|
||||
"eventq_index": 0,
|
||||
"cxx_class": "MmDisk",
|
||||
"default_p_state": "UNDEFINED",
|
||||
"p_state_clk_gate_max": 2000000000,
|
||||
"path": "system.disk0",
|
||||
"pio_addr": 134217728000,
|
||||
"type": "MmDisk"
|
||||
},
|
||||
"multi_thread": false,
|
||||
"reset_addr": 1099243192320,
|
||||
"p_state_clk_gate_bins": 20,
|
||||
"hypervisor_desc_addr": 133446500352,
|
||||
"num_work_ids": 16,
|
||||
"work_item_id": -1,
|
||||
|
||||
@@ -1,10 +1,12 @@
|
||||
Redirecting stdout to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simout
|
||||
Redirecting stderr to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 17 2016 20:30:24
|
||||
gem5 started Jan 17 2016 20:30:38
|
||||
gem5 executing on zizzer, pid 47389
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re /z/stever/hg/gem5/tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
|
||||
gem5 compiled Apr 4 2017 00:40:32
|
||||
gem5 started Apr 4 2017 00:40:43
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 88259
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
|
||||
|
||||
Global frequency set at 2000000000 ticks per second
|
||||
info: No kernel set for full system simulation. Assuming you know what you're doing
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user