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stats: Update ARM FS stats.

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The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.

    commit 746e2f3c27
    Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
    Date:   Mon Feb 27 10:29:56 2017 +0000

        arm, kmi: Clear interrupts in KMI devices

Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Gabe Black
2017-03-29 18:50:49 -07:00
parent 33c48b50cd
commit 1297ee31f6
25 changed files with 15657 additions and 15490 deletions
Download Patch File Download Diff File Expand all files Collapse all files

212
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
View File

@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -30,7 +30,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -49,7 +49,7 @@ panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
@@ -99,7 +99,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -175,6 +175,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu0.tracer
@@ -212,10 +213,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -229,6 +230,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu0.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -241,15 +243,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu0.dstage2_mmu]
type=ArmStage2MMU
@@ -461,9 +464,9 @@ timings=system.cpu0.executeFuncUnits.funcUnits4.timings
[system.cpu0.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
eventq_index=0
opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25
opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses27
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
@@ -483,116 +486,126 @@ opClass=FloatCvt
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
opClass=FloatMisc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
opClass=FloatMult
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
opClass=FloatMultAcc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
opClass=FloatDiv
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
opClass=FloatSqrt
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
opClass=SimdAdd
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
opClass=SimdAddAcc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
opClass=SimdAlu
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
opClass=SimdCmp
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
opClass=SimdCvt
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
opClass=SimdMisc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
opClass=SimdMult
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
opClass=SimdMultAcc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
opClass=SimdShift
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
opClass=SimdShiftAcc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
opClass=SimdSqrt
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
opClass=SimdFloatAdd
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
opClass=SimdFloatAlu
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
opClass=SimdFloatCmp
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
opClass=SimdFloatCvt
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
opClass=SimdFloatDiv
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
opClass=SimdFloatMisc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses26]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses27]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu0.executeFuncUnits.funcUnits4.timings]
@@ -626,9 +639,9 @@ timings=system.cpu0.executeFuncUnits.funcUnits5.timings
[system.cpu0.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
children=opClasses0 opClasses1 opClasses2 opClasses3
eventq_index=0
opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1
opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses3
[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
@@ -640,6 +653,16 @@ type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses2]
type=MinorOpClass
eventq_index=0
opClass=FloatMemRead
[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses3]
type=MinorOpClass
eventq_index=0
opClass=FloatMemWrite
[system.cpu0.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
@@ -692,10 +715,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -709,6 +732,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
tag_latency=1
tags=system.cpu0.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -721,15 +745,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=1
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=1
[system.cpu0.interrupts]
type=ArmInterrupts
@@ -748,8 +773,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -760,8 +783,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -824,10 +845,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -841,6 +862,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
tag_latency=12
tags=system.cpu0.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -883,15 +905,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=12
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
tag_latency=12
[system.cpu0.toL2Bus]
type=CoherentXBar
@@ -991,6 +1014,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu1.tracer
@@ -1028,10 +1052,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -1045,6 +1069,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu1.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -1057,15 +1082,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
@@ -1277,9 +1303,9 @@ timings=system.cpu1.executeFuncUnits.funcUnits4.timings
[system.cpu1.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
eventq_index=0
opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25
opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses27
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
@@ -1299,116 +1325,126 @@ opClass=FloatCvt
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
opClass=FloatMisc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
opClass=FloatMult
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
opClass=FloatMultAcc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
opClass=FloatDiv
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
opClass=FloatSqrt
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
opClass=SimdAdd
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
opClass=SimdAddAcc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
opClass=SimdAlu
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
opClass=SimdCmp
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
opClass=SimdCvt
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
opClass=SimdMisc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
opClass=SimdMult
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
opClass=SimdMultAcc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
opClass=SimdShift
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
opClass=SimdShiftAcc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
opClass=SimdSqrt
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
opClass=SimdFloatAdd
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
opClass=SimdFloatAlu
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
opClass=SimdFloatCmp
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
opClass=SimdFloatCvt
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
opClass=SimdFloatDiv
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
opClass=SimdFloatMisc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses26]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses27]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu1.executeFuncUnits.funcUnits4.timings]
@@ -1442,9 +1478,9 @@ timings=system.cpu1.executeFuncUnits.funcUnits5.timings
[system.cpu1.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
children=opClasses0 opClasses1 opClasses2 opClasses3
eventq_index=0
opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1
opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses3
[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
@@ -1456,6 +1492,16 @@ type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses2]
type=MinorOpClass
eventq_index=0
opClass=FloatMemRead
[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses3]
type=MinorOpClass
eventq_index=0
opClass=FloatMemWrite
[system.cpu1.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
@@ -1508,10 +1554,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -1525,6 +1571,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
tag_latency=1
tags=system.cpu1.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -1537,15 +1584,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=1
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=1
[system.cpu1.interrupts]
type=ArmInterrupts
@@ -1564,8 +1612,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -1576,8 +1622,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -1640,10 +1684,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -1657,6 +1701,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
tag_latency=12
tags=system.cpu1.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -1699,15 +1744,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=12
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
tag_latency=12
[system.cpu1.toL2Bus]
type=CoherentXBar
@@ -1787,10 +1833,10 @@ addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=50
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=50
is_read_only=false
max_miss_count=0
mshrs=20
@@ -1804,6 +1850,7 @@ response_latency=50
sequential_access=false
size=1024
system=system
tag_latency=50
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
@@ -1816,15 +1863,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
data_latency=50
default_p_state=UNDEFINED
eventq_index=0
hit_latency=50
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1024
tag_latency=50
[system.l2c]
type=Cache
@@ -1833,10 +1881,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -1850,6 +1898,7 @@ response_latency=20
sequential_access=false
size=4194304
system=system
tag_latency=20
tags=system.l2c.tags
tgts_per_mshr=12
write_buffers=8
@@ -1862,15 +1911,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=4194304
tag_latency=20
[system.membus]
type=CoherentXBar

20
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr
View File

@@ -1,10 +1,15 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0. Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
@@ -27,10 +32,25 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: instruction 'mcr bpiall' unimplemented
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]

30
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
View File

@@ -3,30 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:42:59
gem5 executing on e108600-lin, pid 17317
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor-dual
gem5 compiled Mar 29 2017 19:38:26
gem5 started Mar 29 2017 19:38:42
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83600
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2848926718000 because m5_exit instruction encountered
Exiting @ tick 2848623849000 because m5_exit instruction encountered

6286
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
View File

File diff suppressed because it is too large Load Diff

111
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
View File

@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -30,7 +30,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -49,7 +49,7 @@ panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
@@ -99,7 +99,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -175,6 +175,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
@@ -212,10 +213,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -229,6 +230,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -241,15 +243,16 @@ type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -461,9 +464,9 @@ timings=system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
@@ -483,116 +486,126 @@ opClass=FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
opClass=FloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
opClass=FloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
@@ -626,9 +639,9 @@ timings=system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
children=opClasses0 opClasses1 opClasses2 opClasses3
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
@@ -640,6 +653,16 @@ type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2]
type=MinorOpClass
eventq_index=0
opClass=FloatMemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3]
type=MinorOpClass
eventq_index=0
opClass=FloatMemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
@@ -692,10 +715,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -709,6 +732,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -721,15 +745,16 @@ type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
@@ -748,8 +773,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -760,8 +783,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -824,10 +845,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -841,6 +862,7 @@ response_latency=20
sequential_access=false
size=4194304
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -853,15 +875,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=4194304
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -941,10 +964,10 @@ addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=50
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=50
is_read_only=false
max_miss_count=0
mshrs=20
@@ -958,6 +981,7 @@ response_latency=50
sequential_access=false
size=1024
system=system
tag_latency=50
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
@@ -970,15 +994,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
data_latency=50
default_p_state=UNDEFINED
eventq_index=0
hit_latency=50
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1024
tag_latency=50
[system.membus]
type=CoherentXBar

20
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr
View File

@@ -1,9 +1,14 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0. Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
@@ -26,7 +31,22 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]

30
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout
View File

@@ -3,30 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:53:08
gem5 executing on e108600-lin, pid 17485
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor
gem5 compiled Mar 29 2017 19:38:26
gem5 started Mar 29 2017 19:38:42
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83599
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2854925996500 because m5_exit instruction encountered
Exiting @ tick 2854927627500 because m5_exit instruction encountered

3130
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
View File

File diff suppressed because it is too large Load Diff

164
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
View File

@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -30,7 +30,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -49,7 +49,7 @@ panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
@@ -99,7 +99,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -122,7 +122,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu0.branchPred
cachePorts=200
cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -198,6 +198,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu0.tracer
trapLatency=13
@@ -233,10 +234,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -250,6 +251,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu0.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -262,15 +264,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu0.dstage2_mmu]
type=ArmStage2MMU
@@ -373,38 +376,52 @@ pipelined=true
[system.cpu0.fuPool.FUList2]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu0.fuPool.FUList2.opList
opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1
[system.cpu0.fuPool.FUList2.opList]
[system.cpu0.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
[system.cpu0.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=2
pipelined=true
[system.cpu0.fuPool.FUList3]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu0.fuPool.FUList3.opList
opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1
[system.cpu0.fuPool.FUList3.opList]
[system.cpu0.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
[system.cpu0.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=2
pipelined=true
[system.cpu0.fuPool.FUList4]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25
opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25 system.cpu0.fuPool.FUList4.opList26 system.cpu0.fuPool.FUList4.opList27
[system.cpu0.fuPool.FUList4.opList00]
type=OpDesc
@@ -536,7 +553,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
opLat=5
pipelined=true
[system.cpu0.fuPool.FUList4.opList19]
@@ -588,6 +605,20 @@ opClass=FloatMult
opLat=4
pipelined=true
[system.cpu0.fuPool.FUList4.opList26]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu0.fuPool.FUList4.opList27]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu0.icache]
type=Cache
children=tags
@@ -595,10 +626,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -612,6 +643,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
tag_latency=1
tags=system.cpu0.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -624,15 +656,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=1
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=1
[system.cpu0.interrupts]
type=ArmInterrupts
@@ -651,8 +684,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -663,8 +694,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -727,10 +756,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -744,6 +773,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
tag_latency=12
tags=system.cpu0.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -786,15 +816,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=12
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
tag_latency=12
[system.cpu0.toL2Bus]
type=CoherentXBar
@@ -841,7 +872,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu1.branchPred
cachePorts=200
cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -917,6 +948,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu1.tracer
trapLatency=13
@@ -952,10 +984,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -969,6 +1001,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu1.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -981,15 +1014,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
@@ -1092,38 +1126,52 @@ pipelined=true
[system.cpu1.fuPool.FUList2]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu1.fuPool.FUList2.opList
opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1
[system.cpu1.fuPool.FUList2.opList]
[system.cpu1.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
[system.cpu1.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=2
pipelined=true
[system.cpu1.fuPool.FUList3]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu1.fuPool.FUList3.opList
opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1
[system.cpu1.fuPool.FUList3.opList]
[system.cpu1.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
[system.cpu1.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=2
pipelined=true
[system.cpu1.fuPool.FUList4]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25
opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25 system.cpu1.fuPool.FUList4.opList26 system.cpu1.fuPool.FUList4.opList27
[system.cpu1.fuPool.FUList4.opList00]
type=OpDesc
@@ -1255,7 +1303,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
opLat=5
pipelined=true
[system.cpu1.fuPool.FUList4.opList19]
@@ -1307,6 +1355,20 @@ opClass=FloatMult
opLat=4
pipelined=true
[system.cpu1.fuPool.FUList4.opList26]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu1.fuPool.FUList4.opList27]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu1.icache]
type=Cache
children=tags
@@ -1314,10 +1376,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -1331,6 +1393,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
tag_latency=1
tags=system.cpu1.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -1343,15 +1406,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=1
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=1
[system.cpu1.interrupts]
type=ArmInterrupts
@@ -1370,8 +1434,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -1382,8 +1444,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -1446,10 +1506,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -1463,6 +1523,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
tag_latency=12
tags=system.cpu1.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -1505,15 +1566,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=12
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
tag_latency=12
[system.cpu1.toL2Bus]
type=CoherentXBar
@@ -1593,10 +1655,10 @@ addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=50
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=50
is_read_only=false
max_miss_count=0
mshrs=20
@@ -1610,6 +1672,7 @@ response_latency=50
sequential_access=false
size=1024
system=system
tag_latency=50
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
@@ -1622,15 +1685,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
data_latency=50
default_p_state=UNDEFINED
eventq_index=0
hit_latency=50
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1024
tag_latency=50
[system.l2c]
type=Cache
@@ -1639,10 +1703,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -1656,6 +1720,7 @@ response_latency=20
sequential_access=false
size=4194304
system=system
tag_latency=20
tags=system.l2c.tags
tgts_per_mshr=12
write_buffers=8
@@ -1668,15 +1733,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=4194304
tag_latency=20
[system.membus]
type=CoherentXBar

22
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
View File

@@ -1,10 +1,15 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0. Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
@@ -25,16 +30,32 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[4], opc1[4], crm[0], opc2[0]
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: instruction 'mcr bpiall' unimplemented
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
warn: allocating bonus target for snoop
warn: allocating bonus target for snoop
warn: Returning zero for read from miscreg pmcr
warn: Ignoring write to miscreg pmcntenclr
warn: Ignoring write to miscreg pmintenclr
@@ -45,4 +66,3 @@ warn: Ignoring write to miscreg pmintenclr
warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmcr
warn: instruction 'mcr dcisw' unimplemented
warn: CP14 unimplemented crn[3], opc1[5], crm[8], opc2[0]

30
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
View File

@@ -3,30 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 21:00:48
gem5 executing on e108600-lin, pid 17551
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-dual
gem5 compiled Mar 29 2017 19:38:26
gem5 started Mar 29 2017 19:38:42
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83601
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2826594924500 because m5_exit instruction encountered
Exiting @ tick 2826661822500 because m5_exit instruction encountered

7650
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
View File

File diff suppressed because it is too large Load Diff

2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
View File

@@ -158,8 +158,8 @@ ata1.00: 1048320 sectors, multi 0: LBA
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
Serial: AMBA PL011 UART driver
Serial: AMBA PL011 UART driver
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
console [ttyAMA0] enabled

87
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View File

@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -30,7 +30,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -49,7 +49,7 @@ panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
@@ -99,7 +99,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -122,7 +122,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -198,6 +198,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -233,10 +234,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -250,6 +251,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -262,15 +264,16 @@ type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -373,38 +376,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
[system.cpu.fuPool.FUList2.opList]
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
[system.cpu.fuPool.FUList3.opList]
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@@ -536,7 +553,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@@ -588,6 +605,20 @@ opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList4.opList26]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList27]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.icache]
type=Cache
children=tags
@@ -595,10 +626,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -612,6 +643,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -624,15 +656,16 @@ type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
@@ -651,8 +684,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -663,8 +694,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -727,10 +756,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -744,6 +773,7 @@ response_latency=20
sequential_access=false
size=4194304
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -756,15 +786,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=4194304
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -844,10 +875,10 @@ addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=50
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=50
is_read_only=false
max_miss_count=0
mshrs=20
@@ -861,6 +892,7 @@ response_latency=50
sequential_access=false
size=1024
system=system
tag_latency=50
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
@@ -873,15 +905,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
data_latency=50
default_p_state=UNDEFINED
eventq_index=0
hit_latency=50
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1024
tag_latency=50
[system.membus]
type=CoherentXBar

21
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
View File

@@ -1,9 +1,14 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0. Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
@@ -24,7 +29,22 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
@@ -35,5 +55,6 @@ warn: Ignoring write to miscreg pmcntenclr
warn: Ignoring write to miscreg pmintenclr
warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmcr
warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5]
warn: instruction 'mcr dcisw' unimplemented
warn: instruction 'mcr bpiall' unimplemented

30
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
View File

@@ -3,30 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:43:01
gem5 executing on e108600-lin, pid 17340
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3
gem5 compiled Mar 29 2017 19:38:26
gem5 started Mar 29 2017 19:38:42
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 83598
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2829112944500 because m5_exit instruction encountered
Exiting @ tick 2829109393000 because m5_exit instruction encountered

3761
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
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File diff suppressed because it is too large Load Diff

20
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
View File

@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -30,7 +30,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -49,7 +49,7 @@ panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
readfile=/z/powerjg/gem5-upstream/tests/testing/../halt.sh
readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
@@ -99,7 +99,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/dist/m5/system/disks/linux-aarch32-ael.img
image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -144,6 +144,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu0.tracer
workload=
@@ -314,8 +315,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -326,8 +325,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -528,6 +525,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu1.tracer
workload=
@@ -698,8 +696,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -710,8 +706,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system

20
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
View File

@@ -1,10 +1,15 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0. Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
@@ -25,9 +30,24 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: instruction 'mcr bpiall' unimplemented
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]

30
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
View File

@@ -3,30 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 29 2016 19:03:48
gem5 started Nov 29 2016 19:04:20
gem5 executing on zizzer, pid 5756
command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
gem5 compiled Mar 29 2017 18:44:23
gem5 started Mar 29 2017 18:44:38
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 53279
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2870988926500 because m5_exit instruction encountered
Exiting @ tick 2871012355500 because m5_exit instruction encountered

6302
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
View File

File diff suppressed because it is too large Load Diff

15
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
View File

@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -30,7 +30,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -49,7 +49,7 @@ panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
readfile=/z/powerjg/gem5-upstream/tests/testing/../halt.sh
readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
@@ -99,7 +99,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/dist/m5/system/disks/linux-aarch32-ael.img
image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -144,6 +144,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=
@@ -314,8 +315,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -326,8 +325,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system

20
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
View File

@@ -1,9 +1,14 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0. Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
@@ -24,6 +29,21 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]

30
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
View File

@@ -3,30 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 29 2016 19:03:48
gem5 started Nov 29 2016 19:06:57
gem5 executing on zizzer, pid 5768
command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing
gem5 compiled Mar 29 2017 18:44:23
gem5 started Mar 29 2017 18:44:38
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 53278
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2905317504500 because m5_exit instruction encountered
Exiting @ tick 2905305537500 because m5_exit instruction encountered

3104
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff