1297ee31f6
The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.
commit 746e2f3c27
Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
Date: Mon Feb 27 10:29:56 2017 +0000
arm, kmi: Clear interrupts in KMI devices
Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
55 lines
3.3 KiB
Plaintext
Executable File
55 lines
3.3 KiB
Plaintext
Executable File
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
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info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
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warn: Sockets disabled, not accepting vnc client connections
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warn: Sockets disabled, not accepting terminal connections
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warn: Sockets disabled, not accepting gdb connections
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warn: ClockedObject: More than one power state change request encountered within the same simulation tick
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info: Using bootloader at address 0x10
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info: Using kernel entry physical address at 0x80008000
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info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
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warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
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info: Entering event queue @ 0. Starting simulation...
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warn: Not doing anything for miscreg ACTLR
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warn: Not doing anything for write of miscreg ACTLR
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warn: The clidr register always reports 0 caches.
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warn: clidr LoUIS field of 0b001 to match current ARM implementations.
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warn: The csselr register isn't implemented.
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warn: instruction 'mcr dccmvau' unimplemented
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warn: instruction 'mcr icimvau' unimplemented
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warn: instruction 'mcr bpiallis' unimplemented
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warn: instruction 'mcr icialluis' unimplemented
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warn: instruction 'mcr dccimvac' unimplemented
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warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
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warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
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warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
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warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
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warn: Returning zero for read from miscreg pmcr
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warn: Ignoring write to miscreg pmcntenclr
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warn: Ignoring write to miscreg pmintenclr
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warn: Ignoring write to miscreg pmovsr
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warn: Ignoring write to miscreg pmcr
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