config: Move core timing models to config/common/cores

Change-Id: I189b6462cc64f7cc6c1b7a6c2af1abb60e1854de
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3943
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Andreas Sandberg
2017-06-26 14:35:17 +01:00
parent 90c7e56bf4
commit 3212bdf3a8
11 changed files with 83 additions and 12 deletions

View File

@@ -55,9 +55,9 @@ def config_cache(options, system):
if options.cpu_type == "O3_ARM_v7a_3":
try:
from O3_ARM_v7a import *
from cores.arm.O3_ARM_v7a import *
except:
print "arm_detailed is unavailable. Did you compile the O3 model?"
print "O3_ARM_v7a_3 is unavailable. Did you compile the O3 model?"
sys.exit(1)
dcache_class, icache_class, l2_cache_class, walk_cache_class = \

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@@ -113,23 +113,23 @@ def config_etrace(cpu_cls, cpu_list, options):
# The ARM detailed CPU is special in the sense that it doesn't exist
# in the normal object hierarchy, so we have to add it manually.
try:
from O3_ARM_v7a import O3_ARM_v7a_3
from cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
_cpu_classes["O3_ARM_v7a_3"] = O3_ARM_v7a_3
except:
pass
# The calibrated ex5-model cores
try:
from ex5_LITTLE import ex5_LITTLE
from cores.arm.ex5_LITTLE import ex5_LITTLE
_cpu_classes["ex5_LITTLE"] = ex5_LITTLE
except:
pass
pass
try:
from ex5_big import ex5_big
from cores.arm.ex5_big import ex5_big
_cpu_classes["ex5_big"] = ex5_big
except:
pass
pass
# Add all CPUs in the object hierarchy.

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@@ -0,0 +1,36 @@
# Copyright (c) 2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Sandberg

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@@ -0,0 +1,36 @@
# Copyright (c) 2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Sandberg

View File

@@ -51,8 +51,7 @@ m5.util.addToPath("../../")
from common import SysPaths
from common import CpuConfig
from common import ex5_big
from common import ex5_LITTLE
from common.cores.arm import ex5_big, ex5_LITTLE
import devices
from devices import AtomicCluster, KvmCluster

View File

@@ -43,7 +43,7 @@ m5.util.addToPath('../configs/')
from common import FSConfig
from common.Caches import *
from base_config import *
from common.O3_ARM_v7a import *
from common.cores.arm.O3_ARM_v7a import *
from common.Benchmarks import SysConfig
class ArmSESystemUniprocessor(BaseSESystemUniprocessor):

View File

@@ -42,7 +42,7 @@ from m5.objects import *
from m5.defines import buildEnv
from base_config import *
from arm_generic import *
from common.O3_ARM_v7a import O3_ARM_v7a_3
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
# If we are running ARM regressions, use a more sensible CPU
# configuration. This makes the results more meaningful, and also

View File

@@ -42,7 +42,7 @@ from m5.objects import *
from m5.defines import buildEnv
from base_config import *
from arm_generic import *
from common.O3_ARM_v7a import O3_ARM_v7a_3
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
# If we are running ARM regressions, use a more sensible CPU
# configuration. This makes the results more meaningful, and also