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mem: Update DRAM configuration names

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Names of DRAM configurations were updated to reflect both
the channel and device data width.

Previous naming format was:
	<DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>

The following nomenclature is now used:
	<DEVICE_TYPE>_<DATA_RATE>_<n>x<w>
where n = The number of devices per rank on the channel
      x = Device width

Total channel width can be calculated by n*w

Example:
A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
	n = 16
	w = 4
The resulting configuration name is:
	DDR4_2400_16x4

Updated scripts to match new naming convention.

Added unique configurations for DDR4 for:
1) 16x4
2) 8x8
3) 4x16

Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
This commit is contained in:
Wendy Elsasser
2017-02-14 15:09:18 -06:00
parent 94e6126650
commit ca0fd665dc
47 changed files with 171 additions and 96 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
tests/configs/minor-timing-mp.py
View File

@@ -42,5 +42,5 @@ from m5.objects import *
from base_config import *
nb_cores = 4
root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_x64,
root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU, num_cpus=nb_cores).create_root()

2
tests/configs/minor-timing.py
View File

@@ -41,5 +41,5 @@
from m5.objects import *
from base_config import *
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU).create_root()

2
tests/configs/o3-timing-checker.py
View File

@@ -38,6 +38,6 @@
from m5.objects import *
from base_config import *
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU,
checker=True).create_root()

2
tests/configs/o3-timing-mp.py
View File

@@ -42,5 +42,5 @@ from m5.objects import *
from base_config import *
nb_cores = 4
root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_x64,
root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU, num_cpus=nb_cores).create_root()

4
tests/configs/o3-timing-mt.py
View File

@@ -48,10 +48,10 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
# configuration. This makes the results more meaningful, and also
# increases the coverage of the regressions.
if buildEnv['TARGET_ISA'] == "arm":
root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
num_threads=2).create_root()
else:
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU,
num_threads=2).create_root()

4
tests/configs/o3-timing.py
View File

@@ -48,8 +48,8 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
# configuration. This makes the results more meaningful, and also
# increases the coverage of the regressions.
if buildEnv['TARGET_ISA'] == "arm":
root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3).create_root()
else:
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU).create_root()

2
tests/configs/pc-o3-timing.py
View File

@@ -39,5 +39,5 @@ from m5.objects import *
from x86_generic import *
root = LinuxX86FSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU).create_root()

2
tests/configs/pc-simple-timing.py
View File

@@ -39,6 +39,6 @@ from m5.objects import *
from x86_generic import *
root = LinuxX86FSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU).create_root()

2
tests/configs/pc-switcheroo-full.py
View File

@@ -42,7 +42,7 @@ from x86_generic import *
import switcheroo
root = LinuxX86FSSwitcheroo(
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
).create_root()

2
tests/configs/realview-minor-dual.py
View File

@@ -39,6 +39,6 @@ from m5.objects import *
from arm_generic import *
root = LinuxArmFSSystem(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU,
num_cpus=2).create_root()

2
tests/configs/realview-minor.py
View File

@@ -39,5 +39,5 @@ from m5.objects import *
from arm_generic import *
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU).create_root()

2
tests/configs/realview-o3-checker.py
View File

@@ -40,6 +40,6 @@ from arm_generic import *
from common.O3_ARM_v7a import O3_ARM_v7a_3
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
checker=True).create_root()

2
tests/configs/realview-o3-dual.py
View File

@@ -40,6 +40,6 @@ from arm_generic import *
from common.O3_ARM_v7a import O3_ARM_v7a_3
root = LinuxArmFSSystem(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
num_cpus=2).create_root()

2
tests/configs/realview-o3.py
View File

@@ -40,5 +40,5 @@ from arm_generic import *
from common.O3_ARM_v7a import O3_ARM_v7a_3
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3).create_root()

2
tests/configs/realview-simple-timing-dual.py
View File

@@ -39,6 +39,6 @@ from m5.objects import *
from arm_generic import *
root = LinuxArmFSSystem(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU,
num_cpus=2).create_root()

2
tests/configs/realview-simple-timing.py
View File

@@ -39,5 +39,5 @@ from m5.objects import *
from arm_generic import *
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU).create_root()

2
tests/configs/realview-switcheroo-full.py
View File

@@ -40,7 +40,7 @@ from arm_generic import *
import switcheroo
root = LinuxArmFSSwitcheroo(
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, MinorCPU, DerivO3CPU)
).create_root()

2
tests/configs/realview-switcheroo-o3.py
View File

@@ -40,7 +40,7 @@ from arm_generic import *
import switcheroo
root = LinuxArmFSSwitcheroo(
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(DerivO3CPU, DerivO3CPU)
).create_root()

2
tests/configs/realview-switcheroo-timing.py
View File

@@ -40,7 +40,7 @@ from arm_generic import *
import switcheroo
root = LinuxArmFSSwitcheroo(
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(TimingSimpleCPU, TimingSimpleCPU)
).create_root()

2
tests/configs/realview64-minor-dual.py
View File

@@ -40,6 +40,6 @@ from arm_generic import *
root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU,
num_cpus=2).create_root()

2
tests/configs/realview64-minor.py
View File

@@ -40,5 +40,5 @@ from arm_generic import *
root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU).create_root()

2
tests/configs/realview64-o3-checker.py
View File

@@ -41,6 +41,6 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
checker=True).create_root()

2
tests/configs/realview64-o3-dual.py
View File

@@ -41,6 +41,6 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
num_cpus=2).create_root()

2
tests/configs/realview64-o3.py
View File

@@ -41,5 +41,5 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3).create_root()

2
tests/configs/realview64-simple-timing-dual.py
View File

@@ -40,6 +40,6 @@ from arm_generic import *
root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU,
num_cpus=2).create_root()

2
tests/configs/realview64-simple-timing.py
View File

@@ -40,5 +40,5 @@ from arm_generic import *
root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU).create_root()

2
tests/configs/realview64-switcheroo-full.py
View File

@@ -41,7 +41,7 @@ import switcheroo
root = LinuxArmFSSwitcheroo(
machine_type='VExpress_EMM64',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, MinorCPU, DerivO3CPU)
).create_root()

2
tests/configs/realview64-switcheroo-o3.py
View File

@@ -41,7 +41,7 @@ import switcheroo
root = LinuxArmFSSwitcheroo(
machine_type='VExpress_EMM64',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(DerivO3CPU, DerivO3CPU)
).create_root()

2
tests/configs/realview64-switcheroo-timing.py
View File

@@ -41,7 +41,7 @@ import switcheroo
root = LinuxArmFSSwitcheroo(
machine_type='VExpress_EMM64',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(TimingSimpleCPU, TimingSimpleCPU)
).create_root()

2
tests/configs/tgen-dram-ctrl.py
View File

@@ -49,7 +49,7 @@ cpu = TrafficGen(
config_file=srcpath("tests/quick/se/70.tgen/tgen-dram-ctrl.cfg"))
# system simulated
system = System(cpu = cpu, physmem = DDR3_1600_x64(),
system = System(cpu = cpu, physmem = DDR3_1600_8x8(),
membus = IOXBar(width = 16),
clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain =

2
tests/configs/tsunami-minor-dual.py
View File

@@ -39,6 +39,6 @@ from m5.objects import *
from alpha_generic import *
root = LinuxAlphaFSSystem(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU,
num_cpus=2).create_root()

2
tests/configs/tsunami-minor.py
View File

@@ -39,5 +39,5 @@ from m5.objects import *
from alpha_generic import *
root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU).create_root()

2
tests/configs/tsunami-o3-dual.py
View File

@@ -39,6 +39,6 @@ from m5.objects import *
from alpha_generic import *
root = LinuxAlphaFSSystem(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU,
num_cpus=2).create_root()

2
tests/configs/tsunami-o3.py
View File

@@ -39,5 +39,5 @@ from m5.objects import *
from alpha_generic import *
root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU).create_root()

2
tests/configs/tsunami-simple-timing-dual.py
View File

@@ -39,6 +39,6 @@ from m5.objects import *
from alpha_generic import *
root = LinuxAlphaFSSystem(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU,
num_cpus=2).create_root()

2
tests/configs/tsunami-simple-timing.py
View File

@@ -39,5 +39,5 @@ from m5.objects import *
from alpha_generic import *
root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_class=TimingSimpleCPU).create_root()

2
tests/configs/tsunami-switcheroo-full.py
View File

@@ -40,7 +40,7 @@ from alpha_generic import *
import switcheroo
root = LinuxAlphaFSSwitcheroo(
mem_class=DDR3_1600_x64,
mem_class=DDR3_1600_8x8,
cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
).create_root()