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stats: Update some stats after simulated program exit behavior was changed.

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The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

    commit 2c1286865f
    Author: Brandon Potter <Brandon.Potter@amd.com>
    Date:   Wed Mar 1 14:52:23 2017 -0600

        syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Gabe Black
2017-03-29 16:14:05 -07:00
parent 8ebc383465
commit f7ddc4672a
261 changed files with 41062 additions and 40155 deletions
Download Patch File Download Diff File Expand all files Collapse all files

82
tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
View File

@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -141,6 +141,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -193,6 +194,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -205,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -316,38 +319,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
[system.cpu.fuPool.FUList2.opList]
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
[system.cpu.fuPool.FUList3.opList]
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@@ -479,7 +496,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@@ -531,6 +548,20 @@ opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList4.opList26]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList27]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.icache]
type=Cache
children=tags
@@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -555,6 +586,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
tag_latency=1
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -567,15 +599,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=1
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=1
[system.cpu.interrupts]
type=ArmInterrupts
@@ -594,8 +627,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -606,8 +637,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -687,6 +716,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
tag_latency=12
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -729,15 +759,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=12
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
tag_latency=12
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -773,7 +804,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=mcf mcf.in
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
drivers=
@@ -782,14 +813,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=55300000000
system=system
uid=100

1
tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
View File

@@ -1,4 +1,5 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]

11
tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
View File

@@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:52:57
gem5 executing on e108600-lin, pid 17480
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 18:10:17
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 56685
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -26,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 58675371500 because target called exit()
Exiting @ tick 58521086000 because exiting with last active thread context

2516
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

49
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
View File

@@ -85,6 +85,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -115,6 +116,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -127,15 +129,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=SparcTLB
@@ -145,14 +148,14 @@ size=64
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -166,6 +169,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -178,15 +182,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=SparcInterrupts
@@ -204,14 +209,14 @@ size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -225,6 +230,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -237,15 +243,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -281,7 +288,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=mcf mcf.in
cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
drivers=
@@ -290,14 +297,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/mcf
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100
input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=55300000000
system=system
uid=100
@@ -321,6 +329,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -332,7 +341,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -340,6 +349,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -348,6 +364,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
@@ -355,7 +372,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:268435455
range=0:268435455:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]

1
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
View File

@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...

11
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
View File

@@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-ti
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:30:06
gem5 started Jul 21 2016 14:30:36
gem5 executing on e108600-lin, pid 38669
command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/sparc/linux/simple-timing
gem5 compiled Apr 3 2017 18:41:19
gem5 started Apr 3 2017 18:43:33
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 66471
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -26,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 361597758500 because target called exit()
Exiting @ tick 361613361500 because exiting with last active thread context

1074
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

97
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
View File

@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -65,7 +66,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -139,6 +140,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -183,10 +185,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -200,6 +202,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -212,15 +215,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=X86TLB
@@ -313,10 +317,10 @@ pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
@@ -328,11 +332,25 @@ pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.fuPool.FUList3.opList3]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
@@ -341,18 +359,25 @@ pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
[system.cpu.fuPool.FUList4.opList]
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList4.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@@ -502,24 +527,31 @@ pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList]
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
@@ -535,6 +567,20 @@ opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList3]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
@@ -556,10 +602,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -573,6 +619,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -585,15 +632,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=X86LocalApic
@@ -643,10 +691,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -660,6 +708,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -672,15 +721,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -716,7 +766,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=mcf mcf.in
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
drivers=
@@ -725,14 +775,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/mcf
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=55300000000
system=system
uid=100

3
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
View File

@@ -1,3 +1,6 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.

13
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
View File

@@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 21:08:11
gem5 executing on e108600-lin, pid 17630
command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/x86/linux/o3-timing
gem5 compiled Apr 3 2017 19:05:53
gem5 started Apr 3 2017 19:06:21
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87177
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -19,13 +18,11 @@ All Rights Reserved.
nodes : 500
active arcs : 1905
simplex iterations : 1502
info: Increasing stack size by one page.
flow value : 4990014995
info: Increasing stack size by one page.
new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 66079350000 because target called exit()
Exiting @ tick 65721494500 because exiting with last active thread context

2102
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

50
tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
View File

@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -85,6 +86,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -100,14 +102,14 @@ eventq_index=0
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -121,6 +123,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -133,15 +136,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=X86TLB
@@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -187,6 +191,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -199,15 +204,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=X86LocalApic
@@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -274,6 +280,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -286,15 +293,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -330,7 +338,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=mcf mcf.in
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
drivers=
@@ -339,14 +347,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/mcf
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=55300000000
system=system
uid=100
@@ -370,6 +379,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -381,7 +391,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -389,6 +399,13 @@ width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -397,6 +414,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
@@ -404,7 +422,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:268435455
range=0:268435455:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]

1
tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
View File

@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...

11
tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
View File

@@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:35:23
gem5 started Jul 21 2016 14:36:18
gem5 executing on e108600-lin, pid 18549
command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/x86/linux/simple-timing
gem5 compiled Apr 3 2017 19:05:53
gem5 started Apr 3 2017 19:08:56
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 90898
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -26,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 366199170500 because target called exit()
Exiting @ tick 366229314500 because exiting with last active thread context

1074
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

82
tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
View File

@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -141,6 +141,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -193,6 +194,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -205,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -316,38 +319,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
[system.cpu.fuPool.FUList2.opList]
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
[system.cpu.fuPool.FUList3.opList]
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@@ -479,7 +496,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@@ -531,6 +548,20 @@ opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList4.opList26]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList27]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.icache]
type=Cache
children=tags
@@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -555,6 +586,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
tag_latency=1
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -567,15 +599,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=1
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=1
[system.cpu.interrupts]
type=ArmInterrupts
@@ -594,8 +627,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -606,8 +637,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -687,6 +716,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
tag_latency=12
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -729,15 +759,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=12
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
tag_latency=12
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -773,7 +804,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=parser 2.1.dict -batch
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
drivers=
@@ -782,14 +813,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/parser
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=114600000000
system=system
uid=100

3
tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
View File

@@ -1,4 +1,7 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
info: Increasing stack size by one page.
info: Increasing stack size by one page.

13
tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
View File

@@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:43:00
gem5 executing on e108600-lin, pid 17328
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/o3-timing
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 18:14:44
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 57363
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
@@ -20,12 +19,10 @@ Welcome to the Link Parser -- Version 2.1
Processing sentences in batch mode
info: Increasing stack size by one page.
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@@ -70,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 236034256000 because target called exit()
Exiting @ tick 235850129000 because exiting with last active thread context

2544
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

29
tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
View File

@@ -90,6 +90,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -165,8 +166,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -177,8 +176,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -239,7 +236,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=parser 2.1.dict -batch
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
drivers=
@@ -248,14 +245,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/parser
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=114600000000
system=system
uid=100
@@ -279,6 +277,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -290,7 +289,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -298,6 +297,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -306,6 +312,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
@@ -313,7 +320,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]

3
tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
View File

@@ -1,2 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.

13
tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
View File

@@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-ato
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41
gem5 started Jul 21 2016 14:38:22
gem5 executing on e108600-lin, pid 23082
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/simple-atomic
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 17:56:13
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54223
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
@@ -20,12 +19,10 @@ Welcome to the Link Parser -- Version 2.1
Processing sentences in batch mode
info: Increasing stack size by one page.
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@@ -70,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 279360903000 because target called exit()
Exiting @ tick 279360903000 because exiting with last active thread context

516
tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
View File

@@ -1,262 +1,262 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.279361 # Number of seconds simulated
sim_ticks 279360903000 # Number of ticks simulated
final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2213544 # Simulator instruction rate (inst/s)
host_op_rate 2397561 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1220693561 # Simulator tick rate (ticks/s)
host_mem_usage 263256 # Number of bytes of host memory used
host_seconds 228.85 # Real time elapsed on the host
sim_insts 506578818 # Number of instructions simulated
sim_ops 548692039 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory
system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2066434344 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2066434344 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 216066596 # Number of bytes written to this memory
system.physmem.bytes_written::total 216066596 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 516608586 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 115590054 # Number of read requests responded to by this memory
system.physmem.num_reads::total 632198640 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 55727590 # Number of write requests responded to by this memory
system.physmem.num_writes::total 55727590 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7397006245 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1513627506 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8910633751 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7397006245 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7397006245 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 773431764 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 773431764 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.numSyscalls 548 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 279360903000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 558721807 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 506578818 # Number of instructions committed
system.cpu.committedOps 548692039 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls
system.cpu.num_int_insts 448447005 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 749023721 # number of times the integer registers were read
system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1634221880 # number of times the CC registers were read
system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written
system.cpu.num_mem_refs 172743505 # number of memory refs
system.cpu.num_load_insts 115883283 # Number of load instructions
system.cpu.num_store_insts 56860222 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 558721806.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 121552863 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction
system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction
system.cpu.op_class::MemWrite 56860206 10.36% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 548692589 # Class of executed instruction
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 630707528 # Transaction distribution
system.membus.trans_dist::ReadResp 632196069 # Transaction distribution
system.membus.trans_dist::WriteReq 54239049 # Transaction distribution
system.membus.trans_dist::WriteResp 54239049 # Transaction distribution
system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution
system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution
system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution
system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1375852460 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 2705349287 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 687926230 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 687926230 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 687926230 # Request fanout histogram
sim_seconds 0.279361
sim_ticks 279360903000
final_tick 279360903000
sim_freq 1000000000000
host_inst_rate 937755
host_op_rate 1015713
host_tick_rate 517139598
host_mem_usage 274756
host_seconds 540.20
sim_insts 506578818
sim_ops 548692039
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000
system.physmem.bytes_read::cpu.inst 2066434344
system.physmem.bytes_read::cpu.data 422848347
system.physmem.bytes_read::total 2489282691
system.physmem.bytes_inst_read::cpu.inst 2066434344
system.physmem.bytes_inst_read::total 2066434344
system.physmem.bytes_written::cpu.data 216066596
system.physmem.bytes_written::total 216066596
system.physmem.num_reads::cpu.inst 516608586
system.physmem.num_reads::cpu.data 115590054
system.physmem.num_reads::total 632198640
system.physmem.num_writes::cpu.data 55727590
system.physmem.num_writes::total 55727590
system.physmem.bw_read::cpu.inst 7397006245
system.physmem.bw_read::cpu.data 1513627506
system.physmem.bw_read::total 8910633751
system.physmem.bw_inst_read::cpu.inst 7397006245
system.physmem.bw_inst_read::total 7397006245
system.physmem.bw_write::cpu.data 773431764
system.physmem.bw_write::total 773431764
system.physmem.bw_total::cpu.inst 7397006245
system.physmem.bw_total::cpu.data 2287059270
system.physmem.bw_total::total 9684065515
system.pwrStateResidencyTicks::UNDEFINED 279360903000
system.cpu_clk_domain.clock 500
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0
system.cpu.dstage2_mmu.stage2_tlb.misses 0
system.cpu.dstage2_mmu.stage2_tlb.accesses 0
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000
system.cpu.dtb.walker.walks 0
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
system.cpu.dtb.walker.walkRequestOrigin::total 0
system.cpu.dtb.inst_hits 0
system.cpu.dtb.inst_misses 0
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
system.cpu.dtb.write_hits 0
system.cpu.dtb.write_misses 0
system.cpu.dtb.flush_tlb 0
system.cpu.dtb.flush_tlb_mva 0
system.cpu.dtb.flush_tlb_mva_asid 0
system.cpu.dtb.flush_tlb_asid 0
system.cpu.dtb.flush_entries 0
system.cpu.dtb.align_faults 0
system.cpu.dtb.prefetch_faults 0
system.cpu.dtb.domain_faults 0
system.cpu.dtb.perms_faults 0
system.cpu.dtb.read_accesses 0
system.cpu.dtb.write_accesses 0
system.cpu.dtb.inst_accesses 0
system.cpu.dtb.hits 0
system.cpu.dtb.misses 0
system.cpu.dtb.accesses 0
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
system.cpu.istage2_mmu.stage2_tlb.read_hits 0
system.cpu.istage2_mmu.stage2_tlb.read_misses 0
system.cpu.istage2_mmu.stage2_tlb.write_hits 0
system.cpu.istage2_mmu.stage2_tlb.write_misses 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
system.cpu.istage2_mmu.stage2_tlb.align_faults 0
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0
system.cpu.istage2_mmu.stage2_tlb.misses 0
system.cpu.istage2_mmu.stage2_tlb.accesses 0
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000
system.cpu.itb.walker.walks 0
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
system.cpu.itb.walker.walkRequestOrigin::total 0
system.cpu.itb.inst_hits 0
system.cpu.itb.inst_misses 0
system.cpu.itb.read_hits 0
system.cpu.itb.read_misses 0
system.cpu.itb.write_hits 0
system.cpu.itb.write_misses 0
system.cpu.itb.flush_tlb 0
system.cpu.itb.flush_tlb_mva 0
system.cpu.itb.flush_tlb_mva_asid 0
system.cpu.itb.flush_tlb_asid 0
system.cpu.itb.flush_entries 0
system.cpu.itb.align_faults 0
system.cpu.itb.prefetch_faults 0
system.cpu.itb.domain_faults 0
system.cpu.itb.perms_faults 0
system.cpu.itb.read_accesses 0
system.cpu.itb.write_accesses 0
system.cpu.itb.inst_accesses 0
system.cpu.itb.hits 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 548
system.cpu.pwrStateResidencyTicks::ON 279360903000
system.cpu.numCycles 558721807
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
system.cpu.committedInsts 506578818
system.cpu.committedOps 548692039
system.cpu.num_int_alu_accesses 448447005
system.cpu.num_fp_alu_accesses 16
system.cpu.num_func_calls 19311615
system.cpu.num_conditional_control_insts 90670594
system.cpu.num_int_insts 448447005
system.cpu.num_fp_insts 16
system.cpu.num_int_register_reads 749023721
system.cpu.num_int_register_writes 289993515
system.cpu.num_fp_register_reads 16
system.cpu.num_fp_register_writes 0
system.cpu.num_cc_register_reads 1634221880
system.cpu.num_cc_register_writes 344062197
system.cpu.num_mem_refs 172743505
system.cpu.num_load_insts 115883283
system.cpu.num_store_insts 56860222
system.cpu.num_idle_cycles 0
system.cpu.num_busy_cycles 558721807
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction 0
system.cpu.Branches 121552863
system.cpu.op_class::No_OpClass 0 0.00% 0.00%
system.cpu.op_class::IntAlu 375609862 68.46% 68.46%
system.cpu.op_class::IntMult 339219 0.06% 68.52%
system.cpu.op_class::IntDiv 0 0.00% 68.52%
system.cpu.op_class::FloatAdd 0 0.00% 68.52%
system.cpu.op_class::FloatCmp 0 0.00% 68.52%
system.cpu.op_class::FloatCvt 0 0.00% 68.52%
system.cpu.op_class::FloatMult 0 0.00% 68.52%
system.cpu.op_class::FloatMultAcc 0 0.00% 68.52%
system.cpu.op_class::FloatDiv 0 0.00% 68.52%
system.cpu.op_class::FloatMisc 0 0.00% 68.52%
system.cpu.op_class::FloatSqrt 0 0.00% 68.52%
system.cpu.op_class::SimdAdd 0 0.00% 68.52%
system.cpu.op_class::SimdAddAcc 0 0.00% 68.52%
system.cpu.op_class::SimdAlu 0 0.00% 68.52%
system.cpu.op_class::SimdCmp 0 0.00% 68.52%
system.cpu.op_class::SimdCvt 0 0.00% 68.52%
system.cpu.op_class::SimdMisc 0 0.00% 68.52%
system.cpu.op_class::SimdMult 0 0.00% 68.52%
system.cpu.op_class::SimdMultAcc 0 0.00% 68.52%
system.cpu.op_class::SimdShift 0 0.00% 68.52%
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52%
system.cpu.op_class::SimdSqrt 0 0.00% 68.52%
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52%
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52%
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52%
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52%
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52%
system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52%
system.cpu.op_class::SimdFloatMult 0 0.00% 68.52%
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52%
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52%
system.cpu.op_class::MemRead 115883283 21.12% 89.64%
system.cpu.op_class::MemWrite 56860206 10.36% 100.00%
system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
system.cpu.op_class::FloatMemWrite 16 0.00% 100.00%
system.cpu.op_class::IprAccess 0 0.00% 100.00%
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
system.cpu.op_class::total 548692589
system.membus.snoop_filter.tot_requests 0
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000
system.membus.trans_dist::ReadReq 630707528
system.membus.trans_dist::ReadResp 632196069
system.membus.trans_dist::WriteReq 54239049
system.membus.trans_dist::WriteResp 54239049
system.membus.trans_dist::SoftPFReq 2571
system.membus.trans_dist::SoftPFResp 2571
system.membus.trans_dist::LoadLockedReq 1488541
system.membus.trans_dist::StoreCondReq 1488541
system.membus.trans_dist::StoreCondResp 1488541
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288
system.membus.pkt_count::total 1375852460
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943
system.membus.pkt_size::total 2705349287
system.membus.snoops 0
system.membus.snoopTraffic 0
system.membus.snoop_fanout::samples 687926230
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev 0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
system.membus.snoop_fanout::0 687926230 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
system.membus.snoop_fanout::total 687926230
---------- End Simulation Statistics ----------

53
tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
View File

@@ -87,6 +87,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -117,6 +118,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -129,15 +131,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -214,6 +217,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -226,15 +230,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
@@ -253,8 +258,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -265,8 +268,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -346,6 +347,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -358,15 +360,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -402,7 +405,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=parser 2.1.dict -batch
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
drivers=
@@ -411,14 +414,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/parser
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=114600000000
system=system
uid=100
@@ -442,6 +446,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -453,7 +458,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -461,6 +466,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -469,6 +481,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
@@ -476,7 +489,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]

3
tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
View File

@@ -1,2 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.

13
tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
View File

@@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41
gem5 started Jul 21 2016 14:38:21
gem5 executing on e108600-lin, pid 23071
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/simple-timing
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 18:35:18
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 61430
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
@@ -20,12 +19,10 @@ Welcome to the Link Parser -- Version 2.1
Processing sentences in batch mode
info: Increasing stack size by one page.
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@@ -70,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 708539449500 because target called exit()
Exiting @ tick 708700329500 because exiting with last active thread context

1362
tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

97
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
View File

@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -65,7 +66,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -139,6 +140,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -183,10 +185,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -200,6 +202,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -212,15 +215,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=X86TLB
@@ -313,10 +317,10 @@ pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
@@ -328,11 +332,25 @@ pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.fuPool.FUList3.opList3]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
@@ -341,18 +359,25 @@ pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
[system.cpu.fuPool.FUList4.opList]
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList4.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@@ -502,24 +527,31 @@ pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList]
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
@@ -535,6 +567,20 @@ opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList3]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
@@ -556,10 +602,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -573,6 +619,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -585,15 +632,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=X86LocalApic
@@ -643,10 +691,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -660,6 +708,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -672,15 +721,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -716,7 +766,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=parser 2.1.dict -batch
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
drivers=
@@ -725,14 +775,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/parser
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=114600000000
system=system
uid=100

15
tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
View File

@@ -1,3 +1,18 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.

14
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
View File

@@ -3,17 +3,13 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 21:09:23
gem5 executing on e108600-lin, pid 17649
command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing
gem5 compiled Apr 3 2017 19:05:53
gem5 started Apr 3 2017 19:06:22
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87198
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Reading the dictionary files: *************************************************
58924 words stored in 3784810 bytes
@@ -72,4 +68,4 @@ Echoing of input sentence turned on.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 487015166000 because target called exit()
Exiting @ tick 487050729500 because exiting with last active thread context

2176
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

26
tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
View File

@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
@@ -88,6 +89,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -167,7 +169,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=parser 2.1.dict -batch
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
drivers=
@@ -176,14 +178,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/parser
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=114600000000
system=system
uid=100
@@ -207,6 +210,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -218,7 +222,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -226,6 +230,13 @@ width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -234,6 +245,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
@@ -241,7 +253,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]

4
tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
View File

@@ -1,2 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.

16
tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
View File

@@ -3,16 +3,14 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-ato
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:35:23
gem5 started Jul 21 2016 14:36:19
gem5 executing on e108600-lin, pid 18563
command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/simple-atomic
gem5 compiled Apr 3 2017 19:05:53
gem5 started Apr 3 2017 19:06:22
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87200
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *****************************info: Increasing stack size by one page.
********************
Reading the dictionary files: *************************************************
58924 words stored in 3784810 bytes
@@ -26,8 +24,6 @@ Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
info: Increasing stack size by one page.
info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@@ -72,4 +68,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 885772926000 because target called exit()
Exiting @ tick 885772926000 because exiting with last active thread context

282
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
View File

@@ -1,145 +1,145 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.885773 # Number of seconds simulated
sim_ticks 885772926000 # Number of ticks simulated
final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1551014 # Simulator instruction rate (inst/s)
host_op_rate 2870153 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1661547121 # Simulator tick rate (ticks/s)
host_mem_usage 272636 # Number of bytes of host memory used
host_seconds 533.10 # Real time elapsed on the host
sim_insts 826847304 # Number of instructions simulated
sim_ops 1530082521 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory
system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 8546485088 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 8546485088 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 991837474 # Number of bytes written to this memory
system.physmem.bytes_written::total 991837474 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1068310636 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 384083342 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1452393978 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 149158211 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149158211 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9648618554 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2580263190 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12228881744 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9648618554 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9648618554 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1119742368 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1119742368 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
system.cpu.workload.numSyscalls 551 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 885772926000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1771545853 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826847304 # Number of instructions committed
system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls
system.cpu.num_int_insts 1527470226 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read
system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written
system.cpu.num_mem_refs 533241508 # number of memory refs
system.cpu.num_load_insts 384083313 # Number of load instructions
system.cpu.num_store_insts 149158195 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1771545852.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 149981740 # Number of branches fetched
system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction
system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction
system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction
system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction
system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1530082521 # Class of executed instruction
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution
system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution
system.membus.trans_dist::WriteReq 149158211 # Transaction distribution
system.membus.trans_dist::WriteResp 149158211 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::total 2136621272 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::total 1066483106 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 3203104378 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::total 8546485088 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::total 3277364750 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 11823849838 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 1601552189 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 1601552189 # Request fanout histogram
sim_seconds 0.885773
sim_ticks 885772926000
final_tick 885772926000
sim_freq 1000000000000
host_inst_rate 728826
host_op_rate 1348694
host_tick_rate 780766307
host_mem_usage 284536
host_seconds 1134.49
sim_insts 826847304
sim_ops 1530082521
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
system.physmem.pwrStateResidencyTicks::UNDEFINED 885772926000
system.physmem.bytes_read::cpu.inst 8546485088
system.physmem.bytes_read::cpu.data 2285527276
system.physmem.bytes_read::total 10832012364
system.physmem.bytes_inst_read::cpu.inst 8546485088
system.physmem.bytes_inst_read::total 8546485088
system.physmem.bytes_written::cpu.data 991837474
system.physmem.bytes_written::total 991837474
system.physmem.num_reads::cpu.inst 1068310636
system.physmem.num_reads::cpu.data 384083342
system.physmem.num_reads::total 1452393978
system.physmem.num_writes::cpu.data 149158211
system.physmem.num_writes::total 149158211
system.physmem.bw_read::cpu.inst 9648618554
system.physmem.bw_read::cpu.data 2580263190
system.physmem.bw_read::total 12228881744
system.physmem.bw_inst_read::cpu.inst 9648618554
system.physmem.bw_inst_read::total 9648618554
system.physmem.bw_write::cpu.data 1119742368
system.physmem.bw_write::total 1119742368
system.physmem.bw_total::cpu.inst 9648618554
system.physmem.bw_total::cpu.data 3700005559
system.physmem.bw_total::total 13348624112
system.pwrStateResidencyTicks::UNDEFINED 885772926000
system.cpu_clk_domain.clock 500
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000
system.cpu.apic_clk_domain.clock 8000
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 885772926000
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000
system.cpu.workload.numSyscalls 551
system.cpu.pwrStateResidencyTicks::ON 885772926000
system.cpu.numCycles 1771545853
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
system.cpu.committedInsts 826847304
system.cpu.committedOps 1530082521
system.cpu.num_int_alu_accesses 1527470226
system.cpu.num_fp_alu_accesses 0
system.cpu.num_func_calls 35346287
system.cpu.num_conditional_control_insts 92881952
system.cpu.num_int_insts 1527470226
system.cpu.num_fp_insts 0
system.cpu.num_int_register_reads 3298246119
system.cpu.num_int_register_writes 1240060586
system.cpu.num_fp_register_reads 0
system.cpu.num_fp_register_writes 0
system.cpu.num_cc_register_reads 562449682
system.cpu.num_cc_register_writes 376900986
system.cpu.num_mem_refs 533241508
system.cpu.num_load_insts 384083313
system.cpu.num_store_insts 149158195
system.cpu.num_idle_cycles 0
system.cpu.num_busy_cycles 1771545853
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction 0
system.cpu.Branches 149981740
system.cpu.op_class::No_OpClass 2048202 0.13% 0.13%
system.cpu.op_class::IntAlu 989691029 64.68% 64.82%
system.cpu.op_class::IntMult 306834 0.02% 64.84%
system.cpu.op_class::IntDiv 4794948 0.31% 65.15%
system.cpu.op_class::FloatAdd 0 0.00% 65.15%
system.cpu.op_class::FloatCmp 0 0.00% 65.15%
system.cpu.op_class::FloatCvt 0 0.00% 65.15%
system.cpu.op_class::FloatMult 0 0.00% 65.15%
system.cpu.op_class::FloatMultAcc 0 0.00% 65.15%
system.cpu.op_class::FloatDiv 0 0.00% 65.15%
system.cpu.op_class::FloatMisc 0 0.00% 65.15%
system.cpu.op_class::FloatSqrt 0 0.00% 65.15%
system.cpu.op_class::SimdAdd 0 0.00% 65.15%
system.cpu.op_class::SimdAddAcc 0 0.00% 65.15%
system.cpu.op_class::SimdAlu 0 0.00% 65.15%
system.cpu.op_class::SimdCmp 0 0.00% 65.15%
system.cpu.op_class::SimdCvt 0 0.00% 65.15%
system.cpu.op_class::SimdMisc 0 0.00% 65.15%
system.cpu.op_class::SimdMult 0 0.00% 65.15%
system.cpu.op_class::SimdMultAcc 0 0.00% 65.15%
system.cpu.op_class::SimdShift 0 0.00% 65.15%
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15%
system.cpu.op_class::SimdSqrt 0 0.00% 65.15%
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15%
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15%
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15%
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15%
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15%
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15%
system.cpu.op_class::SimdFloatMult 0 0.00% 65.15%
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15%
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15%
system.cpu.op_class::MemRead 384083313 25.10% 90.25%
system.cpu.op_class::MemWrite 149158195 9.75% 100.00%
system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00%
system.cpu.op_class::IprAccess 0 0.00% 100.00%
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
system.cpu.op_class::total 1530082521
system.membus.snoop_filter.tot_requests 0
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000
system.membus.trans_dist::ReadReq 1452393978
system.membus.trans_dist::ReadResp 1452393978
system.membus.trans_dist::WriteReq 149158211
system.membus.trans_dist::WriteResp 149158211
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272
system.membus.pkt_count_system.cpu.icache_port::total 2136621272
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106
system.membus.pkt_count_system.cpu.dcache_port::total 1066483106
system.membus.pkt_count::total 3203104378
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088
system.membus.pkt_size_system.cpu.icache_port::total 8546485088
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750
system.membus.pkt_size_system.cpu.dcache_port::total 3277364750
system.membus.pkt_size::total 11823849838
system.membus.snoops 0
system.membus.snoopTraffic 0
system.membus.snoop_fanout::samples 1601552189
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev 0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
system.membus.snoop_fanout::0 1601552189 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
system.membus.snoop_fanout::total 1601552189
---------- End Simulation Statistics ----------

50
tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
View File

@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -85,6 +86,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -100,14 +102,14 @@ eventq_index=0
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -121,6 +123,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -133,15 +136,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=X86TLB
@@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -187,6 +191,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -199,15 +204,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=X86LocalApic
@@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -274,6 +280,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -286,15 +293,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -330,7 +338,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=parser 2.1.dict -batch
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
drivers=
@@ -339,14 +347,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/parser
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=114600000000
system=system
uid=100
@@ -370,6 +379,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -381,7 +391,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -389,6 +399,13 @@ width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -397,6 +414,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
@@ -404,7 +422,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]

4
tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
View File

@@ -1,2 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.

16
tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
View File

@@ -3,16 +3,14 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:35:23
gem5 started Jul 21 2016 14:36:17
gem5 executing on e108600-lin, pid 18541
command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/simple-timing
gem5 compiled Apr 3 2017 19:05:53
gem5 started Apr 3 2017 19:06:22
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87196
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *****************************info: Increasing stack size by one page.
********************
Reading the dictionary files: *************************************************
58924 words stored in 3784810 bytes
@@ -26,8 +24,6 @@ Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
info: Increasing stack size by one page.
info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@@ -72,4 +68,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 1650501252500 because target called exit()
Exiting @ tick 1650923912500 because exiting with last active thread context

1084
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

80
tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
View File

@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -141,6 +141,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -193,6 +194,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -205,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -316,38 +319,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
[system.cpu.fuPool.FUList2.opList]
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
[system.cpu.fuPool.FUList3.opList]
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@@ -479,7 +496,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@@ -531,6 +548,20 @@ opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList4.opList26]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList27]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.icache]
type=Cache
children=tags
@@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -555,6 +586,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
tag_latency=1
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -567,15 +599,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=1
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=1
[system.cpu.interrupts]
type=ArmInterrupts
@@ -594,8 +627,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -606,8 +637,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -687,6 +716,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
tag_latency=12
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -729,15 +759,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=12
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
tag_latency=12
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -773,7 +804,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
drivers=
@@ -782,14 +813,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100

5
tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
View File

@@ -1,11 +1,14 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
info: Increasing stack size by one page.
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
@@ -32,6 +35,8 @@ col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
info: Increasing stack size by one page.
info: Increasing stack size by one page.
0 8 14
1 8 14
2 8 14

15
tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
View File

@@ -3,17 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:51:10
gem5 executing on e108600-lin, pid 17461
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/o3-timing
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 18:05:52
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55337
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.120000
Exiting @ tick 122177531500 because target called exit()
Exiting @ tick 124340889500 because exiting with last active thread context

2474
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

27
tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
View File

@@ -90,6 +90,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -165,8 +166,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -177,8 +176,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -239,7 +236,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
drivers=
@@ -248,14 +245,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100
@@ -279,6 +277,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -290,7 +289,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -298,6 +297,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -306,6 +312,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
@@ -313,7 +320,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]

5
tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
View File

@@ -1,10 +1,13 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
info: Increasing stack size by one page.
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
@@ -31,6 +34,8 @@ col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
info: Increasing stack size by one page.
info: Increasing stack size by one page.
0 8 14
1 8 14
2 8 14

15
tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
View File

@@ -3,17 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41
gem5 started Jul 21 2016 14:54:12
gem5 executing on e108600-lin, pid 23918
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/simple-atomic
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 17:56:13
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54231
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/30.eon/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.200000
Exiting @ tick 201717314000 because target called exit()
Exiting @ tick 201717314000 because exiting with last active thread context

516
tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
View File

@@ -1,262 +1,262 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.201717 # Number of seconds simulated
sim_ticks 201717314000 # Number of ticks simulated
final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1476968 # Simulator instruction rate (inst/s)
host_op_rate 1773264 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1091168515 # Simulator tick rate (ticks/s)
host_mem_usage 268416 # Number of bytes of host memory used
host_seconds 184.86 # Real time elapsed on the host
sim_insts 273037595 # Number of instructions simulated
sim_ops 327811950 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 1394641096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory
system.physmem.bytes_read::total 1875350312 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1394641096 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1394641096 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory
system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 348660274 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory
system.physmem.num_reads::total 434960785 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory
system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6913839315 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2383083566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9296922881 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6913839315 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6913839315 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1983209845 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1983209845 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6913839315 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4366293411 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11280132726 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.numSyscalls 191 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 201717314000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 403434629 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 273037595 # Number of instructions committed
system.cpu.committedOps 327811950 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
system.cpu.num_func_calls 12448615 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15799338 # number of instructions that are conditional controls
system.cpu.num_int_insts 258331481 # number of integer instructions
system.cpu.num_fp_insts 114216705 # number of float instructions
system.cpu.num_int_register_reads 938030601 # number of times the integer registers were read
system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
system.cpu.num_cc_register_reads 985884626 # number of times the CC registers were read
system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written
system.cpu.num_mem_refs 168107829 # number of memory refs
system.cpu.num_load_insts 85732235 # Number of load instructions
system.cpu.num_store_insts 82375594 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 403434628.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 30563491 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 104312493 31.82% 31.82% # Class of executed instruction
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
system.cpu.op_class::MemRead 44185161 13.48% 62.20% # Class of executed instruction
system.cpu.op_class::MemWrite 55008376 16.78% 78.98% # Class of executed instruction
system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 327812145 # Class of executed instruction
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 434895828 # Transaction distribution
system.membus.trans_dist::ReadResp 434906723 # Transaction distribution
system.membus.trans_dist::WriteReq 82052672 # Transaction distribution
system.membus.trans_dist::WriteResp 82052672 # Transaction distribution
system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution
system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution
system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution
system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320548 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1034048704 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641096 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 2275398075 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 517024352 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 517024352 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 517024352 # Request fanout histogram
sim_seconds 0.201717
sim_ticks 201717314000
final_tick 201717314000
sim_freq 1000000000000
host_inst_rate 634159
host_op_rate 761378
host_tick_rate 468510100
host_mem_usage 279924
host_seconds 430.55
sim_insts 273037595
sim_ops 327811950
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
system.physmem.pwrStateResidencyTicks::UNDEFINED 201717314000
system.physmem.bytes_read::cpu.inst 1394641096
system.physmem.bytes_read::cpu.data 480709216
system.physmem.bytes_read::total 1875350312
system.physmem.bytes_inst_read::cpu.inst 1394641096
system.physmem.bytes_inst_read::total 1394641096
system.physmem.bytes_written::cpu.data 400047763
system.physmem.bytes_written::total 400047763
system.physmem.num_reads::cpu.inst 348660274
system.physmem.num_reads::cpu.data 86300511
system.physmem.num_reads::total 434960785
system.physmem.num_writes::cpu.data 82063567
system.physmem.num_writes::total 82063567
system.physmem.bw_read::cpu.inst 6913839315
system.physmem.bw_read::cpu.data 2383083566
system.physmem.bw_read::total 9296922881
system.physmem.bw_inst_read::cpu.inst 6913839315
system.physmem.bw_inst_read::total 6913839315
system.physmem.bw_write::cpu.data 1983209845
system.physmem.bw_write::total 1983209845
system.physmem.bw_total::cpu.inst 6913839315
system.physmem.bw_total::cpu.data 4366293411
system.physmem.bw_total::total 11280132726
system.pwrStateResidencyTicks::UNDEFINED 201717314000
system.cpu_clk_domain.clock 500
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0
system.cpu.dstage2_mmu.stage2_tlb.misses 0
system.cpu.dstage2_mmu.stage2_tlb.accesses 0
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000
system.cpu.dtb.walker.walks 0
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
system.cpu.dtb.walker.walkRequestOrigin::total 0
system.cpu.dtb.inst_hits 0
system.cpu.dtb.inst_misses 0
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
system.cpu.dtb.write_hits 0
system.cpu.dtb.write_misses 0
system.cpu.dtb.flush_tlb 0
system.cpu.dtb.flush_tlb_mva 0
system.cpu.dtb.flush_tlb_mva_asid 0
system.cpu.dtb.flush_tlb_asid 0
system.cpu.dtb.flush_entries 0
system.cpu.dtb.align_faults 0
system.cpu.dtb.prefetch_faults 0
system.cpu.dtb.domain_faults 0
system.cpu.dtb.perms_faults 0
system.cpu.dtb.read_accesses 0
system.cpu.dtb.write_accesses 0
system.cpu.dtb.inst_accesses 0
system.cpu.dtb.hits 0
system.cpu.dtb.misses 0
system.cpu.dtb.accesses 0
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
system.cpu.istage2_mmu.stage2_tlb.read_hits 0
system.cpu.istage2_mmu.stage2_tlb.read_misses 0
system.cpu.istage2_mmu.stage2_tlb.write_hits 0
system.cpu.istage2_mmu.stage2_tlb.write_misses 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
system.cpu.istage2_mmu.stage2_tlb.align_faults 0
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0
system.cpu.istage2_mmu.stage2_tlb.misses 0
system.cpu.istage2_mmu.stage2_tlb.accesses 0
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000
system.cpu.itb.walker.walks 0
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
system.cpu.itb.walker.walkRequestOrigin::total 0
system.cpu.itb.inst_hits 0
system.cpu.itb.inst_misses 0
system.cpu.itb.read_hits 0
system.cpu.itb.read_misses 0
system.cpu.itb.write_hits 0
system.cpu.itb.write_misses 0
system.cpu.itb.flush_tlb 0
system.cpu.itb.flush_tlb_mva 0
system.cpu.itb.flush_tlb_mva_asid 0
system.cpu.itb.flush_tlb_asid 0
system.cpu.itb.flush_entries 0
system.cpu.itb.align_faults 0
system.cpu.itb.prefetch_faults 0
system.cpu.itb.domain_faults 0
system.cpu.itb.perms_faults 0
system.cpu.itb.read_accesses 0
system.cpu.itb.write_accesses 0
system.cpu.itb.inst_accesses 0
system.cpu.itb.hits 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 191
system.cpu.pwrStateResidencyTicks::ON 201717314000
system.cpu.numCycles 403434629
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
system.cpu.committedInsts 273037595
system.cpu.committedOps 327811950
system.cpu.num_int_alu_accesses 258331481
system.cpu.num_fp_alu_accesses 114216705
system.cpu.num_func_calls 12448615
system.cpu.num_conditional_control_insts 15799338
system.cpu.num_int_insts 258331481
system.cpu.num_fp_insts 114216705
system.cpu.num_int_register_reads 938030601
system.cpu.num_int_register_writes 162499657
system.cpu.num_fp_register_reads 180262959
system.cpu.num_fp_register_writes 126152315
system.cpu.num_cc_register_reads 985884626
system.cpu.num_cc_register_writes 76361749
system.cpu.num_mem_refs 168107829
system.cpu.num_load_insts 85732235
system.cpu.num_store_insts 82375594
system.cpu.num_idle_cycles 0
system.cpu.num_busy_cycles 403434629
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction 0
system.cpu.Branches 30563491
system.cpu.op_class::No_OpClass 0 0.00% 0.00%
system.cpu.op_class::IntAlu 104312493 31.82% 31.82%
system.cpu.op_class::IntMult 2145905 0.65% 32.48%
system.cpu.op_class::IntDiv 0 0.00% 32.48%
system.cpu.op_class::FloatAdd 0 0.00% 32.48%
system.cpu.op_class::FloatCmp 0 0.00% 32.48%
system.cpu.op_class::FloatCvt 0 0.00% 32.48%
system.cpu.op_class::FloatMult 0 0.00% 32.48%
system.cpu.op_class::FloatMultAcc 0 0.00% 32.48%
system.cpu.op_class::FloatDiv 0 0.00% 32.48%
system.cpu.op_class::FloatMisc 0 0.00% 32.48%
system.cpu.op_class::FloatSqrt 0 0.00% 32.48%
system.cpu.op_class::SimdAdd 0 0.00% 32.48%
system.cpu.op_class::SimdAddAcc 0 0.00% 32.48%
system.cpu.op_class::SimdAlu 0 0.00% 32.48%
system.cpu.op_class::SimdCmp 0 0.00% 32.48%
system.cpu.op_class::SimdCvt 0 0.00% 32.48%
system.cpu.op_class::SimdMisc 0 0.00% 32.48%
system.cpu.op_class::SimdMult 0 0.00% 32.48%
system.cpu.op_class::SimdMultAcc 0 0.00% 32.48%
system.cpu.op_class::SimdShift 0 0.00% 32.48%
system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48%
system.cpu.op_class::SimdSqrt 0 0.00% 32.48%
system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49%
system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49%
system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91%
system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86%
system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34%
system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33%
system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51%
system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66%
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72%
system.cpu.op_class::MemRead 44185161 13.48% 62.20%
system.cpu.op_class::MemWrite 55008376 16.78% 78.98%
system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65%
system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00%
system.cpu.op_class::IprAccess 0 0.00% 100.00%
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
system.cpu.op_class::total 327812145
system.membus.snoop_filter.tot_requests 0
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000
system.membus.trans_dist::ReadReq 434895828
system.membus.trans_dist::ReadResp 434906723
system.membus.trans_dist::WriteReq 82052672
system.membus.trans_dist::WriteResp 82052672
system.membus.trans_dist::SoftPFReq 54062
system.membus.trans_dist::SoftPFResp 54062
system.membus.trans_dist::LoadLockedReq 10895
system.membus.trans_dist::StoreCondReq 10895
system.membus.trans_dist::StoreCondResp 10895
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320548
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156
system.membus.pkt_count::total 1034048704
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641096
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979
system.membus.pkt_size::total 2275398075
system.membus.snoops 0
system.membus.snoopTraffic 0
system.membus.snoop_fanout::samples 517024352
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev 0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
system.membus.snoop_fanout::0 517024352 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
system.membus.snoop_fanout::total 517024352
---------- End Simulation Statistics ----------

51
tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
View File

@@ -87,6 +87,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -117,6 +118,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -129,15 +131,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -214,6 +217,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -226,15 +230,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
@@ -253,8 +258,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -265,8 +268,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -346,6 +347,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -358,15 +360,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -402,7 +405,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
drivers=
@@ -411,14 +414,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100
@@ -442,6 +446,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -453,7 +458,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -461,6 +466,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -469,6 +481,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
@@ -476,7 +489,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]

5
tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
View File

@@ -1,10 +1,13 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
info: Increasing stack size by one page.
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
@@ -31,6 +34,8 @@ col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
info: Increasing stack size by one page.
info: Increasing stack size by one page.
0 8 14
1 8 14
2 8 14

15
tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
View File

@@ -3,17 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41
gem5 started Jul 21 2016 15:00:59
gem5 executing on e108600-lin, pid 24143
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/simple-timing
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 17:56:13
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54216
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.510000
Exiting @ tick 517291025500 because target called exit()
Exiting @ tick 517297855500 because exiting with last active thread context

1342
tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

2
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
View File

@@ -817,7 +817,7 @@ executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/li
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100

8
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
View File

@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Apr 2 2017 11:48:43
gem5 started Apr 2 2017 11:49:00
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87253
gem5 compiled Apr 3 2017 04:18:56
gem5 started Apr 3 2017 04:19:11
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 3566
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@@ -647,4 +647,4 @@ Global frequency set at 1000000000000 ticks per second
2000: 2845746745
1000: 2068042552
0: 290958364
Exiting @ tick 339069355000 because target called exit()
Exiting @ tick 339069355000 because exiting with last active thread context

18
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.339069
sim_ticks 339069355000
final_tick 339069355000
sim_freq 1000000000000
host_inst_rate 200289
host_op_rate 246583
host_tick_rate 106004783
host_mem_usage 288044
host_seconds 3198.62
host_inst_rate 210410
host_op_rate 259043
host_tick_rate 111361442
host_mem_usage 288088
host_seconds 3044.76
sim_insts 640649299
sim_ops 788724958
system.voltage_domain.voltage 1
@@ -458,7 +458,7 @@ system.cpu.fetch.Insts 824295259
system.cpu.fetch.Branches 175312537
system.cpu.fetch.predictedBranches 103250498
system.cpu.fetch.Cycles 638595633
system.cpu.fetch.SquashCycles 8083491
system.cpu.fetch.SquashCycles 8083490
system.cpu.fetch.MiscStallCycles 2728
system.cpu.fetch.PendingTrapStallCycles 17
system.cpu.fetch.IcacheWaitRetryStallCycles 3109
@@ -516,7 +516,7 @@ system.cpu.iq.iqInstsAdded 899826395
system.cpu.iq.iqNonSpecInstsAdded 12582
system.cpu.iq.iqInstsIssued 860048195
system.cpu.iq.iqSquashedInstsIssued 9222152
system.cpu.iq.iqSquashedInstsExamined 111114019
system.cpu.iq.iqSquashedInstsExamined 111114018
system.cpu.iq.iqSquashedOperandsExamined 244270336
system.cpu.iq.iqSquashedNonSpecRemoved 428
system.cpu.iq.issued_per_cycle::samples 677669366
@@ -617,7 +617,7 @@ system.cpu.iq.rate 1.268248
system.cpu.iq.fu_busy_cnt 277608649
system.cpu.iq.fu_busy_rate 0.322783
system.cpu.iq.int_inst_queue_reads 2621941266
system.cpu.iq.int_inst_queue_writes 980329396
system.cpu.iq.int_inst_queue_writes 980329395
system.cpu.iq.int_inst_queue_wakeup_accesses 820105906
system.cpu.iq.fp_inst_queue_reads 62655291
system.cpu.iq.fp_inst_queue_writes 30642249
@@ -735,7 +735,7 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
system.cpu.commit.op_class_0::total 788730070
system.cpu.commit.bw_lim_events 29951867
system.cpu.rob.rob_reads 1525019812
system.cpu.rob.rob_writes 1798395927
system.cpu.rob.rob_writes 1798395926
system.cpu.timesIdled 10540
system.cpu.idleCycles 469345
system.cpu.committedInsts 640649299

27
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
View File

@@ -90,6 +90,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -165,8 +166,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -177,8 +176,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -239,7 +236,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
drivers=
@@ -248,14 +245,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100
@@ -279,6 +277,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -290,7 +289,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -298,6 +297,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -306,6 +312,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
@@ -313,7 +320,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]

3
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
View File

@@ -1,3 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: fcntl64(3, 2) passed through to host
info: Increasing stack size by one page.
info: Increasing stack size by one page.

13
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
View File

@@ -3,15 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-at
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41
gem5 started Jul 21 2016 14:51:02
gem5 executing on e108600-lin, pid 23320
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-atomic
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 17:56:15
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54237
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
637000: 2581848540
636000: 4117852332
635000: 329081094
@@ -650,4 +647,4 @@ info: Increasing stack size by one page.
2000: 2845746745
1000: 2068042552
0: 290958364
Exiting @ tick 395726778500 because target called exit()
Exiting @ tick 395726778500 because exiting with last active thread context

516
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
View File

@@ -1,262 +1,262 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.395727 # Number of seconds simulated
sim_ticks 395726778500 # Number of ticks simulated
final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1825974 # Simulator instruction rate (inst/s)
host_op_rate 2248015 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1127888505 # Simulator tick rate (ticks/s)
host_mem_usage 268260 # Number of bytes of host memory used
host_seconds 350.86 # Real time elapsed on the host
sim_insts 640654411 # Number of instructions simulated
sim_ops 788730070 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory
system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2573511596 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2573511596 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory
system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 643377899 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory
system.physmem.num_reads::total 893713137 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory
system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6503253598 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2892699151 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9395952748 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6503253598 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6503253598 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1322421027 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1322421027 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.numSyscalls 673 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 791453558 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 640654411 # Number of instructions committed
system.cpu.committedOps 788730070 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
system.cpu.num_func_calls 37261296 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
system.cpu.num_int_insts 682251400 # number of integer instructions
system.cpu.num_fp_insts 24239771 # number of float instructions
system.cpu.num_int_register_reads 1268495038 # number of times the integer registers were read
system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
system.cpu.num_cc_register_reads 2369173294 # number of times the CC registers were read
system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
system.cpu.num_mem_refs 381221435 # number of memory refs
system.cpu.num_load_insts 252240938 # Number of load instructions
system.cpu.num_store_insts 128980497 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 791453557.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 137364860 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction
system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction
system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction
system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 788730744 # Class of executed instruction
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 893703778 # Transaction distribution
system.membus.trans_dist::ReadResp 893709517 # Transaction distribution
system.membus.trans_dist::WriteReq 128951477 # Transaction distribution
system.membus.trans_dist::WriteResp 128951477 # Transaction distribution
system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution
system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution
system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution
system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 1022670353 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 1022670353 # Request fanout histogram
sim_seconds 0.395727
sim_ticks 395726778500
final_tick 395726778500
sim_freq 1000000000000
host_inst_rate 761557
host_op_rate 937577
host_tick_rate 470407263
host_mem_usage 279508
host_seconds 841.24
sim_insts 640654411
sim_ops 788730070
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500
system.physmem.bytes_read::cpu.inst 2573511596
system.physmem.bytes_read::cpu.data 1144718516
system.physmem.bytes_read::total 3718230112
system.physmem.bytes_inst_read::cpu.inst 2573511596
system.physmem.bytes_inst_read::total 2573511596
system.physmem.bytes_written::cpu.data 523317413
system.physmem.bytes_written::total 523317413
system.physmem.num_reads::cpu.inst 643377899
system.physmem.num_reads::cpu.data 250335238
system.physmem.num_reads::total 893713137
system.physmem.num_writes::cpu.data 128957216
system.physmem.num_writes::total 128957216
system.physmem.bw_read::cpu.inst 6503253598
system.physmem.bw_read::cpu.data 2892699151
system.physmem.bw_read::total 9395952748
system.physmem.bw_inst_read::cpu.inst 6503253598
system.physmem.bw_inst_read::total 6503253598
system.physmem.bw_write::cpu.data 1322421027
system.physmem.bw_write::total 1322421027
system.physmem.bw_total::cpu.inst 6503253598
system.physmem.bw_total::cpu.data 4215120178
system.physmem.bw_total::total 10718373776
system.pwrStateResidencyTicks::UNDEFINED 395726778500
system.cpu_clk_domain.clock 500
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0
system.cpu.dstage2_mmu.stage2_tlb.misses 0
system.cpu.dstage2_mmu.stage2_tlb.accesses 0
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500
system.cpu.dtb.walker.walks 0
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
system.cpu.dtb.walker.walkRequestOrigin::total 0
system.cpu.dtb.inst_hits 0
system.cpu.dtb.inst_misses 0
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
system.cpu.dtb.write_hits 0
system.cpu.dtb.write_misses 0
system.cpu.dtb.flush_tlb 0
system.cpu.dtb.flush_tlb_mva 0
system.cpu.dtb.flush_tlb_mva_asid 0
system.cpu.dtb.flush_tlb_asid 0
system.cpu.dtb.flush_entries 0
system.cpu.dtb.align_faults 0
system.cpu.dtb.prefetch_faults 0
system.cpu.dtb.domain_faults 0
system.cpu.dtb.perms_faults 0
system.cpu.dtb.read_accesses 0
system.cpu.dtb.write_accesses 0
system.cpu.dtb.inst_accesses 0
system.cpu.dtb.hits 0
system.cpu.dtb.misses 0
system.cpu.dtb.accesses 0
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
system.cpu.istage2_mmu.stage2_tlb.read_hits 0
system.cpu.istage2_mmu.stage2_tlb.read_misses 0
system.cpu.istage2_mmu.stage2_tlb.write_hits 0
system.cpu.istage2_mmu.stage2_tlb.write_misses 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
system.cpu.istage2_mmu.stage2_tlb.align_faults 0
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0
system.cpu.istage2_mmu.stage2_tlb.misses 0
system.cpu.istage2_mmu.stage2_tlb.accesses 0
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500
system.cpu.itb.walker.walks 0
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
system.cpu.itb.walker.walkRequestOrigin::total 0
system.cpu.itb.inst_hits 0
system.cpu.itb.inst_misses 0
system.cpu.itb.read_hits 0
system.cpu.itb.read_misses 0
system.cpu.itb.write_hits 0
system.cpu.itb.write_misses 0
system.cpu.itb.flush_tlb 0
system.cpu.itb.flush_tlb_mva 0
system.cpu.itb.flush_tlb_mva_asid 0
system.cpu.itb.flush_tlb_asid 0
system.cpu.itb.flush_entries 0
system.cpu.itb.align_faults 0
system.cpu.itb.prefetch_faults 0
system.cpu.itb.domain_faults 0
system.cpu.itb.perms_faults 0
system.cpu.itb.read_accesses 0
system.cpu.itb.write_accesses 0
system.cpu.itb.inst_accesses 0
system.cpu.itb.hits 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 673
system.cpu.pwrStateResidencyTicks::ON 395726778500
system.cpu.numCycles 791453558
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
system.cpu.committedInsts 640654411
system.cpu.committedOps 788730070
system.cpu.num_int_alu_accesses 682251400
system.cpu.num_fp_alu_accesses 24239771
system.cpu.num_func_calls 37261296
system.cpu.num_conditional_control_insts 91575866
system.cpu.num_int_insts 682251400
system.cpu.num_fp_insts 24239771
system.cpu.num_int_register_reads 1268495038
system.cpu.num_int_register_writes 468423268
system.cpu.num_fp_register_reads 28064643
system.cpu.num_fp_register_writes 21684311
system.cpu.num_cc_register_reads 2369173294
system.cpu.num_cc_register_writes 351919006
system.cpu.num_mem_refs 381221435
system.cpu.num_load_insts 252240938
system.cpu.num_store_insts 128980497
system.cpu.num_idle_cycles 0
system.cpu.num_busy_cycles 791453558
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction 0
system.cpu.Branches 137364860
system.cpu.op_class::No_OpClass 0 0.00% 0.00%
system.cpu.op_class::IntAlu 385757467 48.91% 48.91%
system.cpu.op_class::IntMult 5173441 0.66% 49.56%
system.cpu.op_class::IntDiv 0 0.00% 49.56%
system.cpu.op_class::FloatAdd 0 0.00% 49.56%
system.cpu.op_class::FloatCmp 0 0.00% 49.56%
system.cpu.op_class::FloatCvt 0 0.00% 49.56%
system.cpu.op_class::FloatMult 0 0.00% 49.56%
system.cpu.op_class::FloatMultAcc 0 0.00% 49.56%
system.cpu.op_class::FloatDiv 0 0.00% 49.56%
system.cpu.op_class::FloatMisc 0 0.00% 49.56%
system.cpu.op_class::FloatSqrt 0 0.00% 49.56%
system.cpu.op_class::SimdAdd 0 0.00% 49.56%
system.cpu.op_class::SimdAddAcc 0 0.00% 49.56%
system.cpu.op_class::SimdAlu 0 0.00% 49.56%
system.cpu.op_class::SimdCmp 0 0.00% 49.56%
system.cpu.op_class::SimdCvt 0 0.00% 49.56%
system.cpu.op_class::SimdMisc 0 0.00% 49.56%
system.cpu.op_class::SimdMult 0 0.00% 49.56%
system.cpu.op_class::SimdMultAcc 0 0.00% 49.56%
system.cpu.op_class::SimdShift 0 0.00% 49.56%
system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56%
system.cpu.op_class::SimdSqrt 0 0.00% 49.56%
system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65%
system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65%
system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05%
system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37%
system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37%
system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67%
system.cpu.op_class::SimdFloatMult 0 0.00% 51.67%
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67%
system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67%
system.cpu.op_class::MemRead 245222568 31.09% 82.76%
system.cpu.op_class::MemWrite 125149823 15.87% 98.62%
system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51%
system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00%
system.cpu.op_class::IprAccess 0 0.00% 100.00%
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
system.cpu.op_class::total 788730744
system.membus.snoop_filter.tot_requests 0
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500
system.membus.trans_dist::ReadReq 893703778
system.membus.trans_dist::ReadResp 893709517
system.membus.trans_dist::WriteReq 128951477
system.membus.trans_dist::WriteResp 128951477
system.membus.trans_dist::SoftPFReq 3620
system.membus.trans_dist::SoftPFResp 3620
system.membus.trans_dist::LoadLockedReq 5739
system.membus.trans_dist::StoreCondReq 5739
system.membus.trans_dist::StoreCondResp 5739
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908
system.membus.pkt_count::total 2045340706
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929
system.membus.pkt_size::total 4241547525
system.membus.snoops 0
system.membus.snoopTraffic 0
system.membus.snoop_fanout::samples 1022670353
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev 0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
system.membus.snoop_fanout::0 1022670353 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
system.membus.snoop_fanout::total 1022670353
---------- End Simulation Statistics ----------

51
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
View File

@@ -87,6 +87,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -117,6 +118,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -129,15 +131,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -214,6 +217,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -226,15 +230,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
@@ -253,8 +258,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -265,8 +268,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -346,6 +347,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -358,15 +360,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -402,7 +405,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
drivers=
@@ -411,14 +414,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100
@@ -442,6 +446,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -453,7 +458,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -461,6 +466,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -469,6 +481,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
@@ -476,7 +489,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]

3
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
View File

@@ -1,3 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: fcntl64(3, 2) passed through to host
info: Increasing stack size by one page.
info: Increasing stack size by one page.

13
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
View File

@@ -3,15 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-ti
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41
gem5 started Jul 21 2016 14:46:39
gem5 executing on e108600-lin, pid 23194
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-timing
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 18:24:09
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 59398
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
637000: 2581848540
636000: 4117852332
635000: 329081094
@@ -650,4 +647,4 @@ info: Increasing stack size by one page.
2000: 2845746745
1000: 2068042552
0: 290958364
Exiting @ tick 1045756396500 because target called exit()
Exiting @ tick 1046047111500 because exiting with last active thread context

1364
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

80
tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
View File

@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -141,6 +141,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -193,6 +194,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -205,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -316,38 +319,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
[system.cpu.fuPool.FUList2.opList]
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
[system.cpu.fuPool.FUList3.opList]
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@@ -479,7 +496,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@@ -531,6 +548,20 @@ opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList4.opList26]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList27]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.icache]
type=Cache
children=tags
@@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -555,6 +586,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
tag_latency=1
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -567,15 +599,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=1
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=1
[system.cpu.interrupts]
type=ArmInterrupts
@@ -594,8 +627,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -606,8 +637,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -687,6 +716,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
tag_latency=12
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -729,15 +759,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=12
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
tag_latency=12
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -773,7 +804,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=vortex lendian.raw
cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
drivers=
@@ -782,14 +813,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100

2
tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
View File

@@ -1,3 +1,5 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

12
tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
View File

@@ -3,12 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:59:48
gem5 executing on e108600-lin, pid 17544
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/arm/linux/o3-timing
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 17:56:13
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54227
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 37982056000 because target called exit()
Exiting @ tick 37944194500 because exiting with last active thread context

2524
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

80
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
View File

@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -141,6 +141,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -193,6 +194,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -205,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -316,38 +319,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
[system.cpu.fuPool.FUList2.opList]
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
[system.cpu.fuPool.FUList3.opList]
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@@ -479,7 +496,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@@ -531,6 +548,20 @@ opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList4.opList26]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList27]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.icache]
type=Cache
children=tags
@@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -555,6 +586,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
tag_latency=1
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -567,15 +599,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=1
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=1
[system.cpu.interrupts]
type=ArmInterrupts
@@ -594,8 +627,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -606,8 +637,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -687,6 +716,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
tag_latency=12
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -729,15 +759,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=12
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
tag_latency=12
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -773,7 +804,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=bzip2 input.source 1
cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
drivers=
@@ -782,14 +813,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100

4
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
View File

@@ -1,4 +1,8 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.

14
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
View File

@@ -3,20 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/s
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:48:52
gem5 executing on e108600-lin, pid 17438
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/o3-timing
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 17:56:14
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54235
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
@@ -27,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 787742202500 because target called exit()
Exiting @ tick 787835965500 because exiting with last active thread context

2556
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

27
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
View File

@@ -90,6 +90,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -165,8 +166,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -177,8 +176,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -239,7 +236,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=bzip2 input.source 1
cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
drivers=
@@ -248,14 +245,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100
@@ -279,6 +277,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -290,7 +289,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -298,6 +297,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -306,6 +312,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
@@ -313,7 +320,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]

4
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
View File

@@ -1,2 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.

14
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
View File

@@ -3,20 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atom
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41
gem5 started Jul 21 2016 14:38:22
gem5 executing on e108600-lin, pid 23077
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-atomic
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 18:15:54
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 57397
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
@@ -27,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 832017490500 because target called exit()
Exiting @ tick 832017490500 because exiting with last active thread context

516
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
View File

@@ -1,262 +1,262 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.832017 # Number of seconds simulated
sim_ticks 832017490500 # Number of ticks simulated
final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2178592 # Simulator instruction rate (inst/s)
host_op_rate 2347103 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1173553065 # Simulator tick rate (ticks/s)
host_mem_usage 260024 # Number of bytes of host memory used
host_seconds 708.97 # Real time elapsed on the host
sim_insts 1544563042 # Number of instructions simulated
sim_ops 1664032434 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory
system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 6178262360 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6178262360 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory
system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1544565590 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1999474787 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory
system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1900666379 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9326306381 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.numSyscalls 46 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 832017490500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1664034982 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1544563042 # Number of instructions committed
system.cpu.committedOps 1664032434 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330256 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
system.cpu.num_int_insts 1477900422 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
system.cpu.num_int_register_reads 2605402867 # number of times the integer registers were read
system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_cc_register_reads 4992096239 # number of times the CC registers were read
system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
system.cpu.num_mem_refs 633153380 # number of memory refs
system.cpu.num_load_insts 458306334 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1664034981.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 213462427 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction
system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::MemRead 458306322 27.54% 89.49% # Class of executed instruction
system.cpu.op_class::MemWrite 174847022 10.51% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead 12 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 24 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1664032481 # Class of executed instruction
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution
system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution
system.membus.trans_dist::WriteReq 172586047 # Transaction distribution
system.membus.trans_dist::WriteResp 172586047 # Transaction distribution
system.membus.trans_dist::SoftPFReq 1 # Transaction distribution
system.membus.trans_dist::SoftPFResp 1 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution
system.membus.trans_dist::StoreCondReq 61 # Transaction distribution
system.membus.trans_dist::StoreCondResp 61 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131180 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4344121790 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262360 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2172060895 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 2172060895 # Request fanout histogram
sim_seconds 0.832017
sim_ticks 832017490500
final_tick 832017490500
sim_freq 1000000000000
host_inst_rate 917891
host_op_rate 988888
host_tick_rate 494444669
host_mem_usage 271524
host_seconds 1682.73
sim_insts 1544563042
sim_ops 1664032434
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500
system.physmem.bytes_read::cpu.inst 6178262360
system.physmem.bytes_read::cpu.data 1581387671
system.physmem.bytes_read::total 7759650031
system.physmem.bytes_inst_read::cpu.inst 6178262360
system.physmem.bytes_inst_read::total 6178262360
system.physmem.bytes_written::cpu.data 624158392
system.physmem.bytes_written::total 624158392
system.physmem.num_reads::cpu.inst 1544565590
system.physmem.num_reads::cpu.data 454909197
system.physmem.num_reads::total 1999474787
system.physmem.num_writes::cpu.data 172586108
system.physmem.num_writes::total 172586108
system.physmem.bw_read::cpu.inst 7425640002
system.physmem.bw_read::cpu.data 1900666379
system.physmem.bw_read::total 9326306381
system.physmem.bw_inst_read::cpu.inst 7425640002
system.physmem.bw_inst_read::total 7425640002
system.physmem.bw_write::cpu.data 750174605
system.physmem.bw_write::total 750174605
system.physmem.bw_total::cpu.inst 7425640002
system.physmem.bw_total::cpu.data 2650840984
system.physmem.bw_total::total 10076480986
system.pwrStateResidencyTicks::UNDEFINED 832017490500
system.cpu_clk_domain.clock 500
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0
system.cpu.dstage2_mmu.stage2_tlb.misses 0
system.cpu.dstage2_mmu.stage2_tlb.accesses 0
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500
system.cpu.dtb.walker.walks 0
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
system.cpu.dtb.walker.walkRequestOrigin::total 0
system.cpu.dtb.inst_hits 0
system.cpu.dtb.inst_misses 0
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
system.cpu.dtb.write_hits 0
system.cpu.dtb.write_misses 0
system.cpu.dtb.flush_tlb 0
system.cpu.dtb.flush_tlb_mva 0
system.cpu.dtb.flush_tlb_mva_asid 0
system.cpu.dtb.flush_tlb_asid 0
system.cpu.dtb.flush_entries 0
system.cpu.dtb.align_faults 0
system.cpu.dtb.prefetch_faults 0
system.cpu.dtb.domain_faults 0
system.cpu.dtb.perms_faults 0
system.cpu.dtb.read_accesses 0
system.cpu.dtb.write_accesses 0
system.cpu.dtb.inst_accesses 0
system.cpu.dtb.hits 0
system.cpu.dtb.misses 0
system.cpu.dtb.accesses 0
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
system.cpu.istage2_mmu.stage2_tlb.read_hits 0
system.cpu.istage2_mmu.stage2_tlb.read_misses 0
system.cpu.istage2_mmu.stage2_tlb.write_hits 0
system.cpu.istage2_mmu.stage2_tlb.write_misses 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
system.cpu.istage2_mmu.stage2_tlb.align_faults 0
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0
system.cpu.istage2_mmu.stage2_tlb.misses 0
system.cpu.istage2_mmu.stage2_tlb.accesses 0
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500
system.cpu.itb.walker.walks 0
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
system.cpu.itb.walker.walkRequestOrigin::total 0
system.cpu.itb.inst_hits 0
system.cpu.itb.inst_misses 0
system.cpu.itb.read_hits 0
system.cpu.itb.read_misses 0
system.cpu.itb.write_hits 0
system.cpu.itb.write_misses 0
system.cpu.itb.flush_tlb 0
system.cpu.itb.flush_tlb_mva 0
system.cpu.itb.flush_tlb_mva_asid 0
system.cpu.itb.flush_tlb_asid 0
system.cpu.itb.flush_entries 0
system.cpu.itb.align_faults 0
system.cpu.itb.prefetch_faults 0
system.cpu.itb.domain_faults 0
system.cpu.itb.perms_faults 0
system.cpu.itb.read_accesses 0
system.cpu.itb.write_accesses 0
system.cpu.itb.inst_accesses 0
system.cpu.itb.hits 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 46
system.cpu.pwrStateResidencyTicks::ON 832017490500
system.cpu.numCycles 1664034982
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
system.cpu.committedInsts 1544563042
system.cpu.committedOps 1664032434
system.cpu.num_int_alu_accesses 1477900422
system.cpu.num_fp_alu_accesses 36
system.cpu.num_func_calls 27330256
system.cpu.num_conditional_control_insts 167612489
system.cpu.num_int_insts 1477900422
system.cpu.num_fp_insts 36
system.cpu.num_int_register_reads 2605402867
system.cpu.num_int_register_writes 1125475224
system.cpu.num_fp_register_reads 24
system.cpu.num_fp_register_writes 16
system.cpu.num_cc_register_reads 4992096239
system.cpu.num_cc_register_writes 518236214
system.cpu.num_mem_refs 633153380
system.cpu.num_load_insts 458306334
system.cpu.num_store_insts 174847046
system.cpu.num_idle_cycles 0
system.cpu.num_busy_cycles 1664034982
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction 0
system.cpu.Branches 213462427
system.cpu.op_class::No_OpClass 0 0.00% 0.00%
system.cpu.op_class::IntAlu 1030178776 61.91% 61.91%
system.cpu.op_class::IntMult 700322 0.04% 61.95%
system.cpu.op_class::IntDiv 0 0.00% 61.95%
system.cpu.op_class::FloatAdd 0 0.00% 61.95%
system.cpu.op_class::FloatCmp 0 0.00% 61.95%
system.cpu.op_class::FloatCvt 0 0.00% 61.95%
system.cpu.op_class::FloatMult 0 0.00% 61.95%
system.cpu.op_class::FloatMultAcc 0 0.00% 61.95%
system.cpu.op_class::FloatDiv 0 0.00% 61.95%
system.cpu.op_class::FloatMisc 0 0.00% 61.95%
system.cpu.op_class::FloatSqrt 0 0.00% 61.95%
system.cpu.op_class::SimdAdd 0 0.00% 61.95%
system.cpu.op_class::SimdAddAcc 0 0.00% 61.95%
system.cpu.op_class::SimdAlu 0 0.00% 61.95%
system.cpu.op_class::SimdCmp 0 0.00% 61.95%
system.cpu.op_class::SimdCvt 0 0.00% 61.95%
system.cpu.op_class::SimdMisc 0 0.00% 61.95%
system.cpu.op_class::SimdMult 0 0.00% 61.95%
system.cpu.op_class::SimdMultAcc 0 0.00% 61.95%
system.cpu.op_class::SimdShift 0 0.00% 61.95%
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95%
system.cpu.op_class::SimdSqrt 0 0.00% 61.95%
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95%
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95%
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95%
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95%
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95%
system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95%
system.cpu.op_class::SimdFloatMult 0 0.00% 61.95%
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95%
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95%
system.cpu.op_class::MemRead 458306322 27.54% 89.49%
system.cpu.op_class::MemWrite 174847022 10.51% 100.00%
system.cpu.op_class::FloatMemRead 12 0.00% 100.00%
system.cpu.op_class::FloatMemWrite 24 0.00% 100.00%
system.cpu.op_class::IprAccess 0 0.00% 100.00%
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
system.cpu.op_class::total 1664032481
system.membus.snoop_filter.tot_requests 0
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500
system.membus.trans_dist::ReadReq 1999474725
system.membus.trans_dist::ReadResp 1999474786
system.membus.trans_dist::WriteReq 172586047
system.membus.trans_dist::WriteResp 172586047
system.membus.trans_dist::SoftPFReq 1
system.membus.trans_dist::SoftPFResp 1
system.membus.trans_dist::LoadLockedReq 61
system.membus.trans_dist::StoreCondReq 61
system.membus.trans_dist::StoreCondResp 61
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131180
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610
system.membus.pkt_count::total 4344121790
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262360
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063
system.membus.pkt_size::total 8383808423
system.membus.snoops 0
system.membus.snoopTraffic 0
system.membus.snoop_fanout::samples 2172060895
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev 0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
system.membus.snoop_fanout::0 2172060895 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
system.membus.snoop_fanout::total 2172060895
---------- End Simulation Statistics ----------

51
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
View File

@@ -87,6 +87,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -117,6 +118,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -129,15 +131,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -214,6 +217,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -226,15 +230,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
@@ -253,8 +258,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -265,8 +268,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -346,6 +347,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -358,15 +360,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -402,7 +405,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=bzip2 input.source 1
cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
drivers=
@@ -411,14 +414,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100
@@ -442,6 +446,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -453,7 +458,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -461,6 +466,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -469,6 +481,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
@@ -476,7 +489,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]

4
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
View File

@@ -1,2 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.

14
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
View File

@@ -3,20 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:37:41
gem5 started Jul 21 2016 14:49:25
gem5 executing on e108600-lin, pid 23292
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-timing
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 17:57:50
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54313
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
@@ -27,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2377029670500 because target called exit()
Exiting @ tick 2379921906500 because exiting with last active thread context

1356
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

24
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
View File

@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
@@ -88,6 +89,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -167,7 +169,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=bzip2 input.source 1
cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
drivers=
@@ -176,14 +178,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/bzip2
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/bzip2
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100
@@ -207,6 +210,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -218,7 +222,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -226,6 +230,13 @@ width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -234,6 +245,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
@@ -241,7 +253,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]

4
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
View File

@@ -1,2 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.

14
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
View File

@@ -3,20 +3,16 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atom
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:35:23
gem5 started Jul 21 2016 14:36:17
gem5 executing on e108600-lin, pid 18539
command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-atomic
gem5 compiled Apr 3 2017 19:05:53
gem5 started Apr 3 2017 19:06:24
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87211
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
@@ -27,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2846007227500 because target called exit()
Exiting @ tick 2846007227500 because exiting with last active thread context

282
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
View File

@@ -1,145 +1,145 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.846007 # Number of seconds simulated
sim_ticks 2846007227500 # Number of ticks simulated
final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1654731 # Simulator instruction rate (inst/s)
host_op_rate 2578221 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1565575242 # Simulator tick rate (ticks/s)
host_mem_usage 262288 # Number of bytes of host memory used
host_seconds 1817.87 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory
system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 1544656792 # Number of bytes written to this memory
system.physmem.bytes_written::total 1544656792 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1239184746 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5252417628 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 438528338 # Number of write requests responded to by this memory
system.physmem.num_writes::total 438528338 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 11281019509 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13046253376 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 11281019509 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 11281019509 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 542745211 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 542745211 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
system.cpu.workload.numSyscalls 46 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 2846007227500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5692014456 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081022 # Number of instructions committed
system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 33534539 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
system.cpu.num_int_insts 4684368009 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read
system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read
system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written
system.cpu.num_mem_refs 1677713084 # number of memory refs
system.cpu.num_load_insts 1239184746 # Number of load instructions
system.cpu.num_store_insts 438528338 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 5692014455.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 248500691 # Number of branches fetched
system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction
system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction
system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction
system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 4686862596 # Class of executed instruction
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution
system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution
system.membus.trans_dist::WriteReq 438528338 # Transaction distribution
system.membus.trans_dist::WriteResp 438528338 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 5690945966 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 5690945966 # Request fanout histogram
sim_seconds 2.846007
sim_ticks 2846007227500
final_tick 2846007227500
sim_freq 1000000000000
host_inst_rate 877028
host_op_rate 1366490
host_tick_rate 829774485
host_mem_usage 274188
host_seconds 3429.86
sim_insts 3008081022
sim_ops 4686862596
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500
system.physmem.bytes_read::cpu.inst 32105863056
system.physmem.bytes_read::cpu.data 5023868345
system.physmem.bytes_read::total 37129731401
system.physmem.bytes_inst_read::cpu.inst 32105863056
system.physmem.bytes_inst_read::total 32105863056
system.physmem.bytes_written::cpu.data 1544656792
system.physmem.bytes_written::total 1544656792
system.physmem.num_reads::cpu.inst 4013232882
system.physmem.num_reads::cpu.data 1239184746
system.physmem.num_reads::total 5252417628
system.physmem.num_writes::cpu.data 438528338
system.physmem.num_writes::total 438528338
system.physmem.bw_read::cpu.inst 11281019509
system.physmem.bw_read::cpu.data 1765233867
system.physmem.bw_read::total 13046253376
system.physmem.bw_inst_read::cpu.inst 11281019509
system.physmem.bw_inst_read::total 11281019509
system.physmem.bw_write::cpu.data 542745211
system.physmem.bw_write::total 542745211
system.physmem.bw_total::cpu.inst 11281019509
system.physmem.bw_total::cpu.data 2307979078
system.physmem.bw_total::total 13588998587
system.pwrStateResidencyTicks::UNDEFINED 2846007227500
system.cpu_clk_domain.clock 500
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500
system.cpu.apic_clk_domain.clock 8000
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500
system.cpu.workload.numSyscalls 46
system.cpu.pwrStateResidencyTicks::ON 2846007227500
system.cpu.numCycles 5692014456
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
system.cpu.committedInsts 3008081022
system.cpu.committedOps 4686862596
system.cpu.num_int_alu_accesses 4684368009
system.cpu.num_fp_alu_accesses 0
system.cpu.num_func_calls 33534539
system.cpu.num_conditional_control_insts 182173300
system.cpu.num_int_insts 4684368009
system.cpu.num_fp_insts 0
system.cpu.num_int_register_reads 10688755601
system.cpu.num_int_register_writes 3999841477
system.cpu.num_fp_register_reads 0
system.cpu.num_fp_register_writes 0
system.cpu.num_cc_register_reads 1226718827
system.cpu.num_cc_register_writes 1355930461
system.cpu.num_mem_refs 1677713084
system.cpu.num_load_insts 1239184746
system.cpu.num_store_insts 438528338
system.cpu.num_idle_cycles 0
system.cpu.num_busy_cycles 5692014456
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction 0
system.cpu.Branches 248500691
system.cpu.op_class::No_OpClass 2494522 0.05% 0.05%
system.cpu.op_class::IntAlu 3006647871 64.15% 64.20%
system.cpu.op_class::IntMult 6215 0.00% 64.20%
system.cpu.op_class::IntDiv 904 0.00% 64.20%
system.cpu.op_class::FloatAdd 0 0.00% 64.20%
system.cpu.op_class::FloatCmp 0 0.00% 64.20%
system.cpu.op_class::FloatCvt 0 0.00% 64.20%
system.cpu.op_class::FloatMult 0 0.00% 64.20%
system.cpu.op_class::FloatMultAcc 0 0.00% 64.20%
system.cpu.op_class::FloatDiv 0 0.00% 64.20%
system.cpu.op_class::FloatMisc 0 0.00% 64.20%
system.cpu.op_class::FloatSqrt 0 0.00% 64.20%
system.cpu.op_class::SimdAdd 0 0.00% 64.20%
system.cpu.op_class::SimdAddAcc 0 0.00% 64.20%
system.cpu.op_class::SimdAlu 0 0.00% 64.20%
system.cpu.op_class::SimdCmp 0 0.00% 64.20%
system.cpu.op_class::SimdCvt 0 0.00% 64.20%
system.cpu.op_class::SimdMisc 0 0.00% 64.20%
system.cpu.op_class::SimdMult 0 0.00% 64.20%
system.cpu.op_class::SimdMultAcc 0 0.00% 64.20%
system.cpu.op_class::SimdShift 0 0.00% 64.20%
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20%
system.cpu.op_class::SimdSqrt 0 0.00% 64.20%
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20%
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20%
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20%
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20%
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20%
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20%
system.cpu.op_class::SimdFloatMult 0 0.00% 64.20%
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20%
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20%
system.cpu.op_class::MemRead 1239184746 26.44% 90.64%
system.cpu.op_class::MemWrite 438528338 9.36% 100.00%
system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00%
system.cpu.op_class::IprAccess 0 0.00% 100.00%
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
system.cpu.op_class::total 4686862596
system.membus.snoop_filter.tot_requests 0
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500
system.membus.trans_dist::ReadReq 5252417628
system.membus.trans_dist::ReadResp 5252417628
system.membus.trans_dist::WriteReq 438528338
system.membus.trans_dist::WriteResp 438528338
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764
system.membus.pkt_count_system.cpu.icache_port::total 8026465764
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168
system.membus.pkt_count_system.cpu.dcache_port::total 3355426168
system.membus.pkt_count::total 11381891932
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056
system.membus.pkt_size_system.cpu.icache_port::total 32105863056
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137
system.membus.pkt_size_system.cpu.dcache_port::total 6568525137
system.membus.pkt_size::total 38674388193
system.membus.snoops 0
system.membus.snoopTraffic 0
system.membus.snoop_fanout::samples 5690945966
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev 0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
system.membus.snoop_fanout::0 5690945966 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
system.membus.snoop_fanout::total 5690945966
---------- End Simulation Statistics ----------

48
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
View File

@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -85,6 +86,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -100,14 +102,14 @@ eventq_index=0
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -121,6 +123,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -133,15 +136,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=X86TLB
@@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -187,6 +191,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -199,15 +204,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=X86LocalApic
@@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -274,6 +280,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -286,15 +293,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -330,7 +338,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=bzip2 input.source 1
cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
drivers=
@@ -339,14 +347,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/bzip2
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/bzip2
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100
@@ -370,6 +379,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -381,7 +391,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=Null
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -389,6 +399,13 @@ width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -397,6 +414,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
@@ -404,7 +422,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]

4
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
View File

@@ -1,2 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.

14
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
View File

@@ -3,20 +3,16 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 21 2016 14:35:23
gem5 started Jul 21 2016 14:36:20
gem5 executing on e108600-lin, pid 18569
command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-timing
gem5 compiled Apr 3 2017 19:05:53
gem5 started Apr 3 2017 19:06:21
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87163
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
@@ -27,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 5895947852500 because target called exit()
Exiting @ tick 5898831348500 because exiting with last active thread context

1074
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

80
tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
View File

@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -141,6 +141,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -193,6 +194,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -205,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -316,38 +319,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
[system.cpu.fuPool.FUList2.opList]
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
[system.cpu.fuPool.FUList3.opList]
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@@ -479,7 +496,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@@ -531,6 +548,20 @@ opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList4.opList26]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList27]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.icache]
type=Cache
children=tags
@@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -555,6 +586,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
tag_latency=1
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -567,15 +599,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=1
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=1
[system.cpu.interrupts]
type=ArmInterrupts
@@ -594,8 +627,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -606,8 +637,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -687,6 +716,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
tag_latency=12
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -729,15 +759,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=12
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
tag_latency=12
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -773,7 +804,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=twolf smred
cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
drivers=
@@ -782,14 +813,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/twolf
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100

2
tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
View File

@@ -1,3 +1,5 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

12
tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
View File

@@ -3,21 +3,19 @@ Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/s
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:43:01
gem5 executing on e108600-lin, pid 17342
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/arm/linux/o3-timing
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 18:24:01
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 59389
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/70.twolf/arm/linux/o3-timing
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
info: Increasing stack size by one page.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
@@ -26,4 +24,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 86053034000 because target called exit()
122 123 124 Exiting @ tick 85986203000 because exiting with last active thread context

2458
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

8
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
View File

@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 30 2017 17:14:30
gem5 started Mar 30 2017 17:14:43
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 80103
gem5 compiled Mar 31 2017 16:17:52
gem5 started Mar 31 2017 16:18:04
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 50433
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
@@ -24,4 +24,4 @@ Authors: Carl Sechen, Bill Swartz
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 102720088500 because target called exit()
122 123 124 Exiting @ tick 102720088500 because exiting with last active thread context

26
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.102720
sim_ticks 102720088500
final_tick 102720088500
sim_freq 1000000000000
host_inst_rate 110078
host_op_rate 184500
host_tick_rate 85614304
host_mem_usage 318036
host_seconds 1199.80
host_inst_rate 108111
host_op_rate 181205
host_tick_rate 84085065
host_mem_usage 318048
host_seconds 1221.62
sim_insts 132071192
sim_ops 221363384
system.voltage_domain.voltage 1
@@ -290,7 +290,7 @@ system.cpu.fetch.Insts 415890076
system.cpu.fetch.Branches 40475084
system.cpu.fetch.predictedBranches 13128503
system.cpu.fetch.Cycles 151898082
system.cpu.fetch.SquashCycles 14677483
system.cpu.fetch.SquashCycles 14677482
system.cpu.fetch.TlbCycles 200
system.cpu.fetch.MiscStallCycles 5835
system.cpu.fetch.PendingTrapStallCycles 64355
@@ -352,7 +352,7 @@ system.cpu.iq.iqInstsAdded 486700641
system.cpu.iq.iqNonSpecInstsAdded 63617
system.cpu.iq.iqInstsIssued 336591190
system.cpu.iq.iqSquashedInstsIssued 1075815
system.cpu.iq.iqSquashedInstsExamined 265400874
system.cpu.iq.iqSquashedInstsExamined 265400873
system.cpu.iq.iqSquashedOperandsExamined 520101528
system.cpu.iq.iqSquashedNonSpecRemoved 62372
system.cpu.iq.issued_per_cycle::samples 205201489
@@ -453,7 +453,7 @@ system.cpu.iq.rate 1.638390
system.cpu.iq.fu_busy_cnt 3927876
system.cpu.iq.fu_busy_rate 0.011670
system.cpu.iq.int_inst_queue_reads 875282503
system.cpu.iq.int_inst_queue_writes 737961959
system.cpu.iq.int_inst_queue_writes 737961958
system.cpu.iq.int_inst_queue_wakeup_accesses 314539840
system.cpu.iq.fp_inst_queue_reads 8105057
system.cpu.iq.fp_inst_queue_writes 15024545
@@ -503,11 +503,11 @@ system.cpu.iew.wb_fanout 0.588199
system.cpu.commit.commitSquashedInsts 265431246
system.cpu.commit.commitNonSpecStalls 1245
system.cpu.commit.branchMispredicts 6620627
system.cpu.commit.committed_per_cycle::samples 163282867
system.cpu.commit.committed_per_cycle::samples 163282868
system.cpu.commit.committed_per_cycle::mean 1.355705
system.cpu.commit.committed_per_cycle::stdev 1.936594
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00%
system.cpu.commit.committed_per_cycle::0 66681317 40.84% 40.84%
system.cpu.commit.committed_per_cycle::0 66681318 40.84% 40.84%
system.cpu.commit.committed_per_cycle::1 54877393 33.61% 74.45%
system.cpu.commit.committed_per_cycle::2 13218924 8.10% 82.54%
system.cpu.commit.committed_per_cycle::3 10716776 6.56% 89.11%
@@ -519,7 +519,7 @@ system.cpu.commit.committed_per_cycle::8 6989165 4.28% 100.00%
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00%
system.cpu.commit.committed_per_cycle::min_value 0
system.cpu.commit.committed_per_cycle::max_value 8
system.cpu.commit.committed_per_cycle::total 163282867
system.cpu.commit.committed_per_cycle::total 163282868
system.cpu.commit.committedInsts 132071192
system.cpu.commit.committedOps 221363384
system.cpu.commit.swp_count 0
@@ -570,8 +570,8 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00%
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
system.cpu.commit.op_class_0::total 221363384
system.cpu.commit.bw_lim_events 6989165
system.cpu.rob.rob_reads 643088332
system.cpu.rob.rob_writes 1015902506
system.cpu.rob.rob_reads 643088333
system.cpu.rob.rob_writes 1015902505
system.cpu.timesIdled 2802
system.cpu.idleCycles 238689
system.cpu.committedInsts 132071192

104
tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
View File

@@ -118,6 +118,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
@@ -155,10 +156,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -172,6 +173,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -184,15 +186,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -404,9 +407,9 @@ timings=system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
@@ -426,116 +429,126 @@ opClass=FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
opClass=FloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
opClass=FloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
@@ -569,9 +582,9 @@ timings=system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
children=opClasses0 opClasses1 opClasses2 opClasses3
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
@@ -583,6 +596,16 @@ type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2]
type=MinorOpClass
eventq_index=0
opClass=FloatMemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3]
type=MinorOpClass
eventq_index=0
opClass=FloatMemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
@@ -635,10 +658,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -652,6 +675,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -664,15 +688,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
@@ -691,8 +716,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -703,8 +726,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -767,10 +788,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -784,6 +805,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -796,15 +818,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -840,7 +863,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=hello
cwd=
drivers=
@@ -849,14 +872,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100

1
tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr
View File

@@ -1,3 +1,4 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...

11
tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout
View File

@@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:42:59
gem5 executing on e108600-lin, pid 17319
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/minor-timing
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 17:56:13
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54225
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 32719500 because target called exit()
Exiting @ tick 32617500 because exiting with last active thread context

1748
tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

103
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
View File

@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
cacheStorePorts=200
checker=system.cpu.checker
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -141,6 +141,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -206,6 +207,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.checker.tracer
updateOnError=true
@@ -276,8 +278,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -288,8 +288,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -356,10 +354,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -373,6 +371,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -385,15 +384,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -517,10 +517,10 @@ pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
@@ -532,11 +532,25 @@ pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.fuPool.FUList3.opList3]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
@@ -545,18 +559,25 @@ pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
[system.cpu.fuPool.FUList4.opList]
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList4.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@@ -706,24 +727,31 @@ pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList]
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
@@ -739,6 +767,20 @@ opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList3]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
@@ -760,10 +802,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -777,6 +819,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -789,15 +832,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
@@ -816,8 +860,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -828,8 +870,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -892,10 +932,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -909,6 +949,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -921,15 +962,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -965,7 +1007,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=hello
cwd=
drivers=
@@ -974,14 +1016,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100

1
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr
View File

@@ -2,3 +2,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...

11
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
View File

@@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:42:58
gem5 executing on e108600-lin, pid 17311
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing-checker
gem5 compiled Apr 3 2017 17:55:48
gem5 started Apr 3 2017 18:05:15
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55322
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing-checker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 18422500 because target called exit()
Exiting @ tick 18517500 because exiting with last active thread context

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