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tests: Upate RISC-V binaries and results

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This patch updates the binaries and results for hello and insttest
regressions using the compressed extension.

Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e
Reviewed-on: https://gem5-review.googlesource.com/4042
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Alec Roelke
2017-07-13 18:00:50 -04:00
parent 68b6f9c8a1
commit cc076757e1
186 changed files with 45664 additions and 12793 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini
View File

@@ -120,6 +120,7 @@ syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side

1
tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json
View File

@@ -1086,6 +1086,7 @@
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,

1
tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr
View File

@@ -1,6 +1,5 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/hello/bin/riscv/linux/hello'

14
tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout
View File

@@ -1,13 +1,13 @@
Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/minor-timing/simout
Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/minor-timing/simerr
Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 31 2017 18:33:59
gem5 started May 31 2017 18:34:12
gem5 executing on boldrock, pid 15707
command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/minor-timing
gem5 compiled Jul 13 2017 17:37:52
gem5 started Jul 13 2017 18:03:36
gem5 executing on boldrock, pid 21568
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
Hello world!
Exiting @ tick 41515000 because exiting with last active thread context
Exiting @ tick 37069000 because exiting with last active thread context

990
tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

2
tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini
View File

@@ -111,6 +111,7 @@ numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numPhysVecRegs=256
numROBEntries=192
numRobs=1
numThreads=1
@@ -143,6 +144,7 @@ syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
wait_for_remote_gdb=false
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side

2
tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json
View File

@@ -970,6 +970,7 @@
"switched_out": false,
"smtLSQPolicy": "Partitioned",
"fetchBufferSize": 64,
"wait_for_remote_gdb": false,
"cacheStorePorts": 200,
"simpoint_start_insts": [],
"max_insts_any_thread": 0,
@@ -1087,6 +1088,7 @@
"default_p_state": "UNDEFINED",
"type": "DerivO3CPU",
"wbWidth": 8,
"numPhysVecRegs": 256,
"interrupts": [
{
"eventq_index": 0,

1
tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr
View File

@@ -1,6 +1,5 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/hello/bin/riscv/linux/hello'

14
tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout
View File

@@ -1,13 +1,13 @@
Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing/simout
Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing/simerr
Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 31 2017 18:33:59
gem5 started May 31 2017 18:34:13
gem5 executing on boldrock, pid 15720
command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/o3-timing
gem5 compiled Jul 13 2017 17:37:52
gem5 started Jul 13 2017 18:03:36
gem5 executing on boldrock, pid 21571
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Hello world!
Exiting @ tick 21876000 because exiting with last active thread context
Exiting @ tick 22347000 because exiting with last active thread context

1503
tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

1
tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini
View File

@@ -91,6 +91,7 @@ switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]

1
tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json
View File

@@ -244,6 +244,7 @@
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,

1
tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr
View File

@@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/hello/bin/riscv/linux/hello'

14
tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout
View File

@@ -1,13 +1,13 @@
Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-atomic/simout
Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-atomic/simerr
Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 31 2017 18:33:59
gem5 started May 31 2017 18:34:14
gem5 executing on boldrock, pid 15724
command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-atomic
gem5 compiled Jul 13 2017 17:37:52
gem5 started Jul 13 2017 18:03:36
gem5 executing on boldrock, pid 21572
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
Hello world!
Exiting @ tick 2783000 because exiting with last active thread context
Exiting @ tick 3301500 because exiting with last active thread context

194
tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt
View File

@@ -1,42 +1,42 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003
sim_ticks 2783000
final_tick 2783000
sim_ticks 3301500
final_tick 3301500
sim_freq 1000000000000
host_inst_rate 86590
host_op_rate 86699
host_tick_rate 43405073
host_mem_usage 264628
host_seconds 0.06
sim_insts 5550
sim_ops 5558
host_inst_rate 10162
host_op_rate 10178
host_tick_rate 6042080
host_mem_usage 248192
host_seconds 0.55
sim_insts 5552
sim_ops 5561
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
system.physmem.pwrStateResidencyTicks::UNDEFINED 2783000
system.physmem.bytes_read::cpu.inst 22236
system.physmem.bytes_read::cpu.data 7346
system.physmem.bytes_read::total 29582
system.physmem.bytes_inst_read::cpu.inst 22236
system.physmem.bytes_inst_read::total 22236
system.physmem.bytes_written::cpu.data 8138
system.physmem.bytes_written::total 8138
system.physmem.num_reads::cpu.inst 5559
system.physmem.num_reads::cpu.data 1101
system.physmem.num_reads::total 6660
system.physmem.num_writes::cpu.data 1097
system.physmem.num_writes::total 1097
system.physmem.bw_read::cpu.inst 7989938915
system.physmem.bw_read::cpu.data 2639597557
system.physmem.bw_read::total 10629536471
system.physmem.bw_inst_read::cpu.inst 7989938915
system.physmem.bw_inst_read::total 7989938915
system.physmem.bw_write::cpu.data 2924182537
system.physmem.bw_write::total 2924182537
system.physmem.bw_total::cpu.inst 7989938915
system.physmem.bw_total::cpu.data 5563780093
system.physmem.bw_total::total 13553719008
system.pwrStateResidencyTicks::UNDEFINED 2783000
system.physmem.pwrStateResidencyTicks::UNDEFINED 3301500
system.physmem.bytes_read::cpu.inst 26380
system.physmem.bytes_read::cpu.data 7234
system.physmem.bytes_read::total 33614
system.physmem.bytes_inst_read::cpu.inst 26380
system.physmem.bytes_inst_read::total 26380
system.physmem.bytes_written::cpu.data 8248
system.physmem.bytes_written::total 8248
system.physmem.num_reads::cpu.inst 6595
system.physmem.num_reads::cpu.data 1082
system.physmem.num_reads::total 7677
system.physmem.num_writes::cpu.data 1080
system.physmem.num_writes::total 1080
system.physmem.bw_read::cpu.inst 7990307436
system.physmem.bw_read::cpu.data 2191125246
system.physmem.bw_read::total 10181432682
system.physmem.bw_inst_read::cpu.inst 7990307436
system.physmem.bw_inst_read::total 7990307436
system.physmem.bw_write::cpu.data 2498258367
system.physmem.bw_write::total 2498258367
system.physmem.bw_total::cpu.inst 7990307436
system.physmem.bw_total::cpu.data 4689383614
system.physmem.bw_total::total 12679691050
system.pwrStateResidencyTicks::UNDEFINED 3301500
system.cpu_clk_domain.clock 500
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
@@ -57,100 +57,104 @@ system.cpu.itb.hits 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 9
system.cpu.pwrStateResidencyTicks::ON 2783000
system.cpu.numCycles 5567
system.cpu.pwrStateResidencyTicks::ON 3301500
system.cpu.numCycles 6604
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
system.cpu.committedInsts 5550
system.cpu.committedOps 5558
system.cpu.num_int_alu_accesses 5557
system.cpu.committedInsts 5552
system.cpu.committedOps 5561
system.cpu.num_int_alu_accesses 5498
system.cpu.num_fp_alu_accesses 12
system.cpu.num_func_calls 291
system.cpu.num_vec_alu_accesses 0
system.cpu.num_func_calls 282
system.cpu.num_conditional_control_insts 914
system.cpu.num_int_insts 5557
system.cpu.num_int_insts 5498
system.cpu.num_fp_insts 12
system.cpu.num_int_register_reads 7540
system.cpu.num_int_register_writes 3562
system.cpu.num_vec_insts 0
system.cpu.num_int_register_reads 7038
system.cpu.num_int_register_writes 3414
system.cpu.num_fp_register_reads 12
system.cpu.num_fp_register_writes 0
system.cpu.num_mem_refs 2198
system.cpu.num_load_insts 1101
system.cpu.num_store_insts 1097
system.cpu.num_vec_register_reads 0
system.cpu.num_vec_register_writes 0
system.cpu.num_mem_refs 2162
system.cpu.num_load_insts 1082
system.cpu.num_store_insts 1080
system.cpu.num_idle_cycles 0
system.cpu.num_busy_cycles 5567
system.cpu.num_busy_cycles 6604
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction 0
system.cpu.Branches 1205
system.cpu.Branches 1196
system.cpu.op_class::No_OpClass 10 0.18% 0.18%
system.cpu.op_class::IntAlu 3353 60.23% 60.41%
system.cpu.op_class::IntMult 2 0.04% 60.45%
system.cpu.op_class::IntDiv 4 0.07% 60.52%
system.cpu.op_class::FloatAdd 0 0.00% 60.52%
system.cpu.op_class::FloatCmp 0 0.00% 60.52%
system.cpu.op_class::FloatCvt 0 0.00% 60.52%
system.cpu.op_class::FloatMult 0 0.00% 60.52%
system.cpu.op_class::FloatMultAcc 0 0.00% 60.52%
system.cpu.op_class::FloatDiv 0 0.00% 60.52%
system.cpu.op_class::FloatMisc 0 0.00% 60.52%
system.cpu.op_class::FloatSqrt 0 0.00% 60.52%
system.cpu.op_class::SimdAdd 0 0.00% 60.52%
system.cpu.op_class::SimdAddAcc 0 0.00% 60.52%
system.cpu.op_class::SimdAlu 0 0.00% 60.52%
system.cpu.op_class::SimdCmp 0 0.00% 60.52%
system.cpu.op_class::SimdCvt 0 0.00% 60.52%
system.cpu.op_class::SimdMisc 0 0.00% 60.52%
system.cpu.op_class::SimdMult 0 0.00% 60.52%
system.cpu.op_class::SimdMultAcc 0 0.00% 60.52%
system.cpu.op_class::SimdShift 0 0.00% 60.52%
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.52%
system.cpu.op_class::SimdSqrt 0 0.00% 60.52%
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.52%
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.52%
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.52%
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.52%
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.52%
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.52%
system.cpu.op_class::SimdFloatMult 0 0.00% 60.52%
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.52%
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.52%
system.cpu.op_class::MemRead 1101 19.78% 80.29%
system.cpu.op_class::MemWrite 1085 19.49% 99.78%
system.cpu.op_class::IntAlu 3392 60.90% 61.08%
system.cpu.op_class::IntMult 2 0.04% 61.11%
system.cpu.op_class::IntDiv 4 0.07% 61.18%
system.cpu.op_class::FloatAdd 0 0.00% 61.18%
system.cpu.op_class::FloatCmp 0 0.00% 61.18%
system.cpu.op_class::FloatCvt 0 0.00% 61.18%
system.cpu.op_class::FloatMult 0 0.00% 61.18%
system.cpu.op_class::FloatMultAcc 0 0.00% 61.18%
system.cpu.op_class::FloatDiv 0 0.00% 61.18%
system.cpu.op_class::FloatMisc 0 0.00% 61.18%
system.cpu.op_class::FloatSqrt 0 0.00% 61.18%
system.cpu.op_class::SimdAdd 0 0.00% 61.18%
system.cpu.op_class::SimdAddAcc 0 0.00% 61.18%
system.cpu.op_class::SimdAlu 0 0.00% 61.18%
system.cpu.op_class::SimdCmp 0 0.00% 61.18%
system.cpu.op_class::SimdCvt 0 0.00% 61.18%
system.cpu.op_class::SimdMisc 0 0.00% 61.18%
system.cpu.op_class::SimdMult 0 0.00% 61.18%
system.cpu.op_class::SimdMultAcc 0 0.00% 61.18%
system.cpu.op_class::SimdShift 0 0.00% 61.18%
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.18%
system.cpu.op_class::SimdSqrt 0 0.00% 61.18%
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.18%
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.18%
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.18%
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.18%
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.18%
system.cpu.op_class::SimdFloatMisc 0 0.00% 61.18%
system.cpu.op_class::SimdFloatMult 0 0.00% 61.18%
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.18%
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.18%
system.cpu.op_class::MemRead 1082 19.43% 80.61%
system.cpu.op_class::MemWrite 1068 19.17% 99.78%
system.cpu.op_class::FloatMemRead 0 0.00% 99.78%
system.cpu.op_class::FloatMemWrite 12 0.22% 100.00%
system.cpu.op_class::IprAccess 0 0.00% 100.00%
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
system.cpu.op_class::total 5567
system.cpu.op_class::total 5570
system.membus.snoop_filter.tot_requests 0
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
system.membus.pwrStateResidencyTicks::UNDEFINED 2783000
system.membus.trans_dist::ReadReq 6652
system.membus.trans_dist::ReadResp 6660
system.membus.trans_dist::WriteReq 1089
system.membus.trans_dist::WriteResp 1089
system.membus.pwrStateResidencyTicks::UNDEFINED 3301500
system.membus.trans_dist::ReadReq 7669
system.membus.trans_dist::ReadResp 7677
system.membus.trans_dist::WriteReq 1072
system.membus.trans_dist::WriteResp 1072
system.membus.trans_dist::LoadLockedReq 8
system.membus.trans_dist::StoreCondReq 8
system.membus.trans_dist::StoreCondResp 8
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11118
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4396
system.membus.pkt_count::total 15514
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 22236
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15484
system.membus.pkt_size::total 37720
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13190
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4324
system.membus.pkt_count::total 17514
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 26380
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15482
system.membus.pkt_size::total 41862
system.membus.snoops 0
system.membus.snoopTraffic 0
system.membus.snoop_fanout::samples 7757
system.membus.snoop_fanout::samples 8757
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev 0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
system.membus.snoop_fanout::0 7757 100.00% 100.00%
system.membus.snoop_fanout::0 8757 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
system.membus.snoop_fanout::total 7757
system.membus.snoop_fanout::total 8757
---------- End Simulation Statistics ----------

10
tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini
View File

@@ -88,6 +88,7 @@ switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
@@ -268,6 +269,7 @@ voltage_domain=system.voltage_domain
[system.ruby.dir_cntrl0]
type=Directory_Controller
children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory
addr_ranges=0:268435455:5:0:0:0
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
@@ -290,17 +292,14 @@ responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
ruby_system=system.ruby
system=system
to_memory_controller_latency=1
transitions_per_cycle=4
transitions_per_cycle=32
version=0
memory=system.mem_ctrls.port
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
addr_ranges=0:268435455:5:0:0:0
eventq_index=0
numa_high_bit=5
size=268435456
system=system
version=0
[system.ruby.dir_cntrl0.dmaRequestToDir]
type=MessageBuffer
@@ -352,6 +351,7 @@ randomization=false
[system.ruby.l1_cntrl0]
type=L1Cache_Controller
children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer
addr_ranges=0:18446744073709551615:0:0:0:0
buffer_size=0
cacheMemory=system.ruby.l1_cntrl0.cacheMemory
cache_response_latency=12

22
tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json
View File

@@ -115,7 +115,6 @@
"path": "system.ruby.l1_cntrl0.requestFromCache",
"type": "MessageBuffer"
},
"cxx_class": "L1Cache_Controller",
"forwardToCache": {
"ordered": true,
"name": "forwardToCache",
@@ -168,8 +167,9 @@
"support_data_reqs": true,
"is_cpu_sequencer": true
},
"type": "L1Cache_Controller",
"cxx_class": "L1Cache_Controller",
"issue_latency": 2,
"type": "L1Cache_Controller",
"recycle_latency": 10,
"clk_domain": "system.cpu.clk_domain",
"version": 0,
@@ -241,6 +241,9 @@
},
"ruby_system": "system.ruby",
"name": "l1_cntrl0",
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"p_state_clk_gate_bins": 20,
"mandatoryQueue": {
"ordered": false,
@@ -1447,12 +1450,15 @@
"path": "system.ruby.dir_cntrl0.responseFromDir",
"type": "MessageBuffer"
},
"transitions_per_cycle": 4,
"transitions_per_cycle": 32,
"memory": {
"peer": "system.mem_ctrls.port",
"role": "MASTER"
},
"power_model": null,
"addr_ranges": [
"0:268435455:5:0:0:0"
],
"buffer_size": 0,
"ruby_system": "system.ruby",
"requestToDir": {
@@ -1487,14 +1493,13 @@
"p_state_clk_gate_bins": 20,
"directory": {
"name": "directory",
"system": "system",
"version": 0,
"addr_ranges": [
"0:268435455:5:0:0:0"
],
"eventq_index": 0,
"cxx_class": "DirectoryMemory",
"path": "system.ruby.dir_cntrl0.directory",
"type": "RubyDirectoryMemory",
"numa_high_bit": 5,
"size": 268435456
"type": "RubyDirectoryMemory"
},
"path": "system.ruby.dir_cntrl0"
}
@@ -1601,6 +1606,7 @@
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,

1
tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr
View File

@@ -8,7 +8,6 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.

14
tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout
View File

@@ -1,13 +1,13 @@
Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing-ruby/simout
Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing-ruby/simerr
Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 31 2017 18:33:59
gem5 started May 31 2017 18:34:14
gem5 executing on boldrock, pid 15732
command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing-ruby
gem5 compiled Jul 13 2017 17:37:52
gem5 started Jul 13 2017 18:03:36
gem5 executing on boldrock, pid 21569
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
Hello world!
Exiting @ tick 99780 because exiting with last active thread context
Exiting @ tick 96790 because exiting with last active thread context

990
tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt
View File

File diff suppressed because it is too large Load Diff

1
tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini
View File

@@ -88,6 +88,7 @@ switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side

1
tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json
View File

@@ -404,6 +404,7 @@
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,

1
tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr
View File

@@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/hello/bin/riscv/linux/hello'

14
tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout
View File

@@ -1,13 +1,13 @@
Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing/simout
Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing/simerr
Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 31 2017 18:33:59
gem5 started May 31 2017 18:34:14
gem5 executing on boldrock, pid 15728
command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing
gem5 compiled Jul 13 2017 17:37:52
gem5 started Jul 13 2017 18:03:36
gem5 executing on boldrock, pid 21570
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Hello world!
Exiting @ tick 34045500 because exiting with last active thread context
Exiting @ tick 31821500 because exiting with last active thread context

648
tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt
View File

@@ -1,36 +1,36 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000034
sim_ticks 34045500
final_tick 34045500
sim_seconds 0.000032
sim_ticks 31821500
final_tick 31821500
sim_freq 1000000000000
host_inst_rate 83295
host_op_rate 83403
host_tick_rate 510821707
host_mem_usage 275396
host_seconds 0.07
sim_insts 5550
sim_ops 5558
host_inst_rate 11620
host_op_rate 11638
host_tick_rate 66593131
host_mem_usage 258956
host_seconds 0.48
sim_insts 5552
sim_ops 5561
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
system.physmem.pwrStateResidencyTicks::UNDEFINED 34045500
system.physmem.bytes_read::cpu.inst 17856
system.physmem.bytes_read::cpu.data 9280
system.physmem.bytes_read::total 27136
system.physmem.bytes_inst_read::cpu.inst 17856
system.physmem.bytes_inst_read::total 17856
system.physmem.num_reads::cpu.inst 279
system.physmem.num_reads::cpu.data 145
system.physmem.num_reads::total 424
system.physmem.bw_read::cpu.inst 524474600
system.physmem.bw_read::cpu.data 272576405
system.physmem.bw_read::total 797051005
system.physmem.bw_inst_read::cpu.inst 524474600
system.physmem.bw_inst_read::total 524474600
system.physmem.bw_total::cpu.inst 524474600
system.physmem.bw_total::cpu.data 272576405
system.physmem.bw_total::total 797051005
system.pwrStateResidencyTicks::UNDEFINED 34045500
system.physmem.pwrStateResidencyTicks::UNDEFINED 31821500
system.physmem.bytes_read::cpu.inst 14592
system.physmem.bytes_read::cpu.data 9216
system.physmem.bytes_read::total 23808
system.physmem.bytes_inst_read::cpu.inst 14592
system.physmem.bytes_inst_read::total 14592
system.physmem.num_reads::cpu.inst 228
system.physmem.num_reads::cpu.data 144
system.physmem.num_reads::total 372
system.physmem.bw_read::cpu.inst 458557893
system.physmem.bw_read::cpu.data 289615512
system.physmem.bw_read::total 748173405
system.physmem.bw_inst_read::cpu.inst 458557893
system.physmem.bw_inst_read::total 458557893
system.physmem.bw_total::cpu.inst 458557893
system.physmem.bw_total::cpu.data 289615512
system.physmem.bw_total::total 748173405
system.pwrStateResidencyTicks::UNDEFINED 31821500
system.cpu_clk_domain.clock 500
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
@@ -51,104 +51,108 @@ system.cpu.itb.hits 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 9
system.cpu.pwrStateResidencyTicks::ON 34045500
system.cpu.numCycles 68091
system.cpu.pwrStateResidencyTicks::ON 31821500
system.cpu.numCycles 63643
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
system.cpu.committedInsts 5550
system.cpu.committedOps 5558
system.cpu.num_int_alu_accesses 5557
system.cpu.committedInsts 5552
system.cpu.committedOps 5561
system.cpu.num_int_alu_accesses 5498
system.cpu.num_fp_alu_accesses 12
system.cpu.num_func_calls 291
system.cpu.num_vec_alu_accesses 0
system.cpu.num_func_calls 282
system.cpu.num_conditional_control_insts 914
system.cpu.num_int_insts 5557
system.cpu.num_int_insts 5498
system.cpu.num_fp_insts 12
system.cpu.num_int_register_reads 7540
system.cpu.num_int_register_writes 3562
system.cpu.num_vec_insts 0
system.cpu.num_int_register_reads 7038
system.cpu.num_int_register_writes 3414
system.cpu.num_fp_register_reads 12
system.cpu.num_fp_register_writes 0
system.cpu.num_mem_refs 2198
system.cpu.num_load_insts 1101
system.cpu.num_store_insts 1097
system.cpu.num_vec_register_reads 0
system.cpu.num_vec_register_writes 0
system.cpu.num_mem_refs 2162
system.cpu.num_load_insts 1082
system.cpu.num_store_insts 1080
system.cpu.num_idle_cycles 0
system.cpu.num_busy_cycles 68091
system.cpu.num_busy_cycles 63643
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction 0
system.cpu.Branches 1205
system.cpu.Branches 1196
system.cpu.op_class::No_OpClass 10 0.18% 0.18%
system.cpu.op_class::IntAlu 3353 60.23% 60.41%
system.cpu.op_class::IntMult 2 0.04% 60.45%
system.cpu.op_class::IntDiv 4 0.07% 60.52%
system.cpu.op_class::FloatAdd 0 0.00% 60.52%
system.cpu.op_class::FloatCmp 0 0.00% 60.52%
system.cpu.op_class::FloatCvt 0 0.00% 60.52%
system.cpu.op_class::FloatMult 0 0.00% 60.52%
system.cpu.op_class::FloatMultAcc 0 0.00% 60.52%
system.cpu.op_class::FloatDiv 0 0.00% 60.52%
system.cpu.op_class::FloatMisc 0 0.00% 60.52%
system.cpu.op_class::FloatSqrt 0 0.00% 60.52%
system.cpu.op_class::SimdAdd 0 0.00% 60.52%
system.cpu.op_class::SimdAddAcc 0 0.00% 60.52%
system.cpu.op_class::SimdAlu 0 0.00% 60.52%
system.cpu.op_class::SimdCmp 0 0.00% 60.52%
system.cpu.op_class::SimdCvt 0 0.00% 60.52%
system.cpu.op_class::SimdMisc 0 0.00% 60.52%
system.cpu.op_class::SimdMult 0 0.00% 60.52%
system.cpu.op_class::SimdMultAcc 0 0.00% 60.52%
system.cpu.op_class::SimdShift 0 0.00% 60.52%
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.52%
system.cpu.op_class::SimdSqrt 0 0.00% 60.52%
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.52%
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.52%
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.52%
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.52%
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.52%
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.52%
system.cpu.op_class::SimdFloatMult 0 0.00% 60.52%
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.52%
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.52%
system.cpu.op_class::MemRead 1101 19.78% 80.29%
system.cpu.op_class::MemWrite 1085 19.49% 99.78%
system.cpu.op_class::IntAlu 3392 60.90% 61.08%
system.cpu.op_class::IntMult 2 0.04% 61.11%
system.cpu.op_class::IntDiv 4 0.07% 61.18%
system.cpu.op_class::FloatAdd 0 0.00% 61.18%
system.cpu.op_class::FloatCmp 0 0.00% 61.18%
system.cpu.op_class::FloatCvt 0 0.00% 61.18%
system.cpu.op_class::FloatMult 0 0.00% 61.18%
system.cpu.op_class::FloatMultAcc 0 0.00% 61.18%
system.cpu.op_class::FloatDiv 0 0.00% 61.18%
system.cpu.op_class::FloatMisc 0 0.00% 61.18%
system.cpu.op_class::FloatSqrt 0 0.00% 61.18%
system.cpu.op_class::SimdAdd 0 0.00% 61.18%
system.cpu.op_class::SimdAddAcc 0 0.00% 61.18%
system.cpu.op_class::SimdAlu 0 0.00% 61.18%
system.cpu.op_class::SimdCmp 0 0.00% 61.18%
system.cpu.op_class::SimdCvt 0 0.00% 61.18%
system.cpu.op_class::SimdMisc 0 0.00% 61.18%
system.cpu.op_class::SimdMult 0 0.00% 61.18%
system.cpu.op_class::SimdMultAcc 0 0.00% 61.18%
system.cpu.op_class::SimdShift 0 0.00% 61.18%
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.18%
system.cpu.op_class::SimdSqrt 0 0.00% 61.18%
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.18%
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.18%
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.18%
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.18%
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.18%
system.cpu.op_class::SimdFloatMisc 0 0.00% 61.18%
system.cpu.op_class::SimdFloatMult 0 0.00% 61.18%
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.18%
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.18%
system.cpu.op_class::MemRead 1082 19.43% 80.61%
system.cpu.op_class::MemWrite 1068 19.17% 99.78%
system.cpu.op_class::FloatMemRead 0 0.00% 99.78%
system.cpu.op_class::FloatMemWrite 12 0.22% 100.00%
system.cpu.op_class::IprAccess 0 0.00% 100.00%
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
system.cpu.op_class::total 5567
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 34045500
system.cpu.op_class::total 5570
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31821500
system.cpu.dcache.tags.replacements 0
system.cpu.dcache.tags.tagsinuse 88.524153
system.cpu.dcache.tags.total_refs 2053
system.cpu.dcache.tags.sampled_refs 145
system.cpu.dcache.tags.avg_refs 14.158621
system.cpu.dcache.tags.tagsinuse 86.061155
system.cpu.dcache.tags.total_refs 2018
system.cpu.dcache.tags.sampled_refs 144
system.cpu.dcache.tags.avg_refs 14.013889
system.cpu.dcache.tags.warmup_cycle 0
system.cpu.dcache.tags.occ_blocks::cpu.data 88.524153
system.cpu.dcache.tags.occ_percent::cpu.data 0.021612
system.cpu.dcache.tags.occ_percent::total 0.021612
system.cpu.dcache.tags.occ_task_id_blocks::1024 145
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23
system.cpu.dcache.tags.age_task_id_blocks_1024::1 122
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035400
system.cpu.dcache.tags.tag_accesses 4541
system.cpu.dcache.tags.data_accesses 4541
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 34045500
system.cpu.dcache.ReadReq_hits::cpu.data 1032
system.cpu.dcache.ReadReq_hits::total 1032
system.cpu.dcache.WriteReq_hits::cpu.data 1007
system.cpu.dcache.WriteReq_hits::total 1007
system.cpu.dcache.LoadLockedReq_hits::cpu.data 6
system.cpu.dcache.LoadLockedReq_hits::total 6
system.cpu.dcache.tags.occ_blocks::cpu.data 86.061155
system.cpu.dcache.tags.occ_percent::cpu.data 0.021011
system.cpu.dcache.tags.occ_percent::total 0.021011
system.cpu.dcache.tags.occ_task_id_blocks::1024 144
system.cpu.dcache.tags.age_task_id_blocks_1024::0 30
system.cpu.dcache.tags.age_task_id_blocks_1024::1 114
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035156
system.cpu.dcache.tags.tag_accesses 4468
system.cpu.dcache.tags.data_accesses 4468
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31821500
system.cpu.dcache.ReadReq_hits::cpu.data 1013
system.cpu.dcache.ReadReq_hits::total 1013
system.cpu.dcache.WriteReq_hits::cpu.data 990
system.cpu.dcache.WriteReq_hits::total 990
system.cpu.dcache.LoadLockedReq_hits::cpu.data 7
system.cpu.dcache.LoadLockedReq_hits::total 7
system.cpu.dcache.StoreCondReq_hits::cpu.data 8
system.cpu.dcache.StoreCondReq_hits::total 8
system.cpu.dcache.demand_hits::cpu.data 2039
system.cpu.dcache.demand_hits::total 2039
system.cpu.dcache.overall_hits::cpu.data 2039
system.cpu.dcache.overall_hits::total 2039
system.cpu.dcache.demand_hits::cpu.data 2003
system.cpu.dcache.demand_hits::total 2003
system.cpu.dcache.overall_hits::cpu.data 2003
system.cpu.dcache.overall_hits::total 2003
system.cpu.dcache.ReadReq_misses::cpu.data 61
system.cpu.dcache.ReadReq_misses::total 61
system.cpu.dcache.WriteReq_misses::cpu.data 82
system.cpu.dcache.WriteReq_misses::total 82
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2
system.cpu.dcache.LoadLockedReq_misses::total 2
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1
system.cpu.dcache.LoadLockedReq_misses::total 1
system.cpu.dcache.demand_misses::cpu.data 143
system.cpu.dcache.demand_misses::total 143
system.cpu.dcache.overall_misses::cpu.data 143
@@ -157,34 +161,34 @@ system.cpu.dcache.ReadReq_miss_latency::cpu.data 3843000
system.cpu.dcache.ReadReq_miss_latency::total 3843000
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5166000
system.cpu.dcache.WriteReq_miss_latency::total 5166000
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000
system.cpu.dcache.LoadLockedReq_miss_latency::total 126000
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 63000
system.cpu.dcache.LoadLockedReq_miss_latency::total 63000
system.cpu.dcache.demand_miss_latency::cpu.data 9009000
system.cpu.dcache.demand_miss_latency::total 9009000
system.cpu.dcache.overall_miss_latency::cpu.data 9009000
system.cpu.dcache.overall_miss_latency::total 9009000
system.cpu.dcache.ReadReq_accesses::cpu.data 1093
system.cpu.dcache.ReadReq_accesses::total 1093
system.cpu.dcache.WriteReq_accesses::cpu.data 1089
system.cpu.dcache.WriteReq_accesses::total 1089
system.cpu.dcache.ReadReq_accesses::cpu.data 1074
system.cpu.dcache.ReadReq_accesses::total 1074
system.cpu.dcache.WriteReq_accesses::cpu.data 1072
system.cpu.dcache.WriteReq_accesses::total 1072
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 8
system.cpu.dcache.LoadLockedReq_accesses::total 8
system.cpu.dcache.StoreCondReq_accesses::cpu.data 8
system.cpu.dcache.StoreCondReq_accesses::total 8
system.cpu.dcache.demand_accesses::cpu.data 2182
system.cpu.dcache.demand_accesses::total 2182
system.cpu.dcache.overall_accesses::cpu.data 2182
system.cpu.dcache.overall_accesses::total 2182
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.055810
system.cpu.dcache.ReadReq_miss_rate::total 0.055810
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.075298
system.cpu.dcache.WriteReq_miss_rate::total 0.075298
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000
system.cpu.dcache.demand_miss_rate::cpu.data 0.065536
system.cpu.dcache.demand_miss_rate::total 0.065536
system.cpu.dcache.overall_miss_rate::cpu.data 0.065536
system.cpu.dcache.overall_miss_rate::total 0.065536
system.cpu.dcache.demand_accesses::cpu.data 2146
system.cpu.dcache.demand_accesses::total 2146
system.cpu.dcache.overall_accesses::cpu.data 2146
system.cpu.dcache.overall_accesses::total 2146
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.056797
system.cpu.dcache.ReadReq_miss_rate::total 0.056797
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.076493
system.cpu.dcache.WriteReq_miss_rate::total 0.076493
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.125000
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.125000
system.cpu.dcache.demand_miss_rate::cpu.data 0.066636
system.cpu.dcache.demand_miss_rate::total 0.066636
system.cpu.dcache.overall_miss_rate::cpu.data 0.066636
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system.cpu.l2cache.overall_mshr_misses::total 372
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4141000
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4141000
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14090000
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14090000
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3181500
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3181500
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14090000
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7322500
system.cpu.l2cache.demand_mshr_miss_latency::total 21412500
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14090000
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7322500
system.cpu.l2cache.overall_mshr_miss_latency::total 21412500
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11514500
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11514500
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3131000
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3131000
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11514500
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7272000
system.cpu.l2cache.demand_mshr_miss_latency::total 18786500
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11514500
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7272000
system.cpu.l2cache.overall_mshr_miss_latency::total 18786500
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1
@@ -447,83 +451,83 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
system.cpu.l2cache.overall_mshr_miss_rate::total 1
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.792115
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.792115
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.192982
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.192982
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.792115
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.192982
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.179245
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.792115
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.344086
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.192982
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.179245
system.cpu.toL2Bus.snoop_filter.tot_requests 424
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.344086
system.cpu.toL2Bus.snoop_filter.tot_requests 372
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
system.cpu.toL2Bus.snoop_filter.tot_snoops 0
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 34045500
system.cpu.toL2Bus.trans_dist::ReadResp 342
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31821500
system.cpu.toL2Bus.trans_dist::ReadResp 290
system.cpu.toL2Bus.trans_dist::ReadExReq 82
system.cpu.toL2Bus.trans_dist::ReadExResp 82
system.cpu.toL2Bus.trans_dist::ReadCleanReq 279
system.cpu.toL2Bus.trans_dist::ReadSharedReq 63
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 290
system.cpu.toL2Bus.pkt_count::total 848
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9280
system.cpu.toL2Bus.pkt_size::total 27136
system.cpu.toL2Bus.trans_dist::ReadCleanReq 228
system.cpu.toL2Bus.trans_dist::ReadSharedReq 62
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288
system.cpu.toL2Bus.pkt_count::total 744
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216
system.cpu.toL2Bus.pkt_size::total 23808
system.cpu.toL2Bus.snoops 0
system.cpu.toL2Bus.snoopTraffic 0
system.cpu.toL2Bus.snoop_fanout::samples 424
system.cpu.toL2Bus.snoop_fanout::samples 372
system.cpu.toL2Bus.snoop_fanout::mean 0
system.cpu.toL2Bus.snoop_fanout::stdev 0
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
system.cpu.toL2Bus.snoop_fanout::0 424 100.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::0 372 100.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::min_value 0
system.cpu.toL2Bus.snoop_fanout::max_value 0
system.cpu.toL2Bus.snoop_fanout::total 424
system.cpu.toL2Bus.reqLayer0.occupancy 212000
system.cpu.toL2Bus.snoop_fanout::total 372
system.cpu.toL2Bus.reqLayer0.occupancy 186000
system.cpu.toL2Bus.reqLayer0.utilization 0.6
system.cpu.toL2Bus.respLayer0.occupancy 418500
system.cpu.toL2Bus.respLayer0.utilization 1.2
system.cpu.toL2Bus.respLayer1.occupancy 217500
system.cpu.toL2Bus.respLayer1.utilization 0.6
system.membus.snoop_filter.tot_requests 424
system.cpu.toL2Bus.respLayer0.occupancy 342000
system.cpu.toL2Bus.respLayer0.utilization 1.1
system.cpu.toL2Bus.respLayer1.occupancy 216000
system.cpu.toL2Bus.respLayer1.utilization 0.7
system.membus.snoop_filter.tot_requests 372
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
system.membus.pwrStateResidencyTicks::UNDEFINED 34045500
system.membus.trans_dist::ReadResp 342
system.membus.pwrStateResidencyTicks::UNDEFINED 31821500
system.membus.trans_dist::ReadResp 290
system.membus.trans_dist::ReadExReq 82
system.membus.trans_dist::ReadExResp 82
system.membus.trans_dist::ReadSharedReq 342
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 848
system.membus.pkt_count::total 848
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27136
system.membus.pkt_size::total 27136
system.membus.trans_dist::ReadSharedReq 290
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 744
system.membus.pkt_count::total 744
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23808
system.membus.pkt_size::total 23808
system.membus.snoops 0
system.membus.snoopTraffic 0
system.membus.snoop_fanout::samples 424
system.membus.snoop_fanout::samples 372
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev 0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
system.membus.snoop_fanout::0 424 100.00% 100.00%
system.membus.snoop_fanout::0 372 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
system.membus.snoop_fanout::total 424
system.membus.reqLayer0.occupancy 424500
system.membus.snoop_fanout::total 372
system.membus.reqLayer0.occupancy 372500
system.membus.reqLayer0.utilization 1.2
system.membus.respLayer1.occupancy 2120000
system.membus.respLayer1.utilization 6.2
system.membus.respLayer1.occupancy 1860000
system.membus.respLayer1.utilization 5.8
---------- End Simulation Statistics ----------

11
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini
View File

@@ -116,9 +116,11 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
@@ -745,7 +747,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=insttest
cwd=
drivers=
@@ -754,14 +756,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest
executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100

15
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json
View File

@@ -297,6 +297,7 @@
"max_loads_all_threads": 0,
"executeMemoryIssueLimit": 1,
"decodeCycleInput": true,
"syscallRetryLatency": 10000,
"max_loads_any_thread": 0,
"executeLSQTransfersQueueSize": 2,
"p_state_clk_gate_max": 1000000000000,
@@ -1058,21 +1059,22 @@
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "LiveProcess",
"executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest",
"cxx_class": "Process",
"executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"input": "cin",
"ppid": 99,
"type": "LiveProcess",
"maxStackSize": 67108864,
"ppid": 0,
"type": "Process",
"cwd": "",
"pgid": 100,
"simpoint": 0,
"euid": 100,
"input": "cin",
"path": "system.cpu.workload",
"max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
@@ -1084,6 +1086,7 @@
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,

6
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr
View File

@@ -1,4 +1,6 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest'
info: Increasing stack size by one page.

12
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout
View File

@@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:29
gem5 executing on zizzer, pid 34061
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/minor-timing
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:12:00
gem5 executing on boldrock, pid 2001
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
lr.w/sc.w: PASS
sc.w, no preceding lr.d: PASS
amoswap.w: PASS
@@ -46,4 +44,4 @@ amomin.d: PASS
amomax.d: PASS
amominu.d: PASS
amomaxu.d: PASS
Exiting @ tick 167328500 because target called exit()
Exiting @ tick 179565500 because exiting with last active thread context

1550
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

876
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.ini Normal file
View File

@@ -0,0 +1,876 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
default_p_state=UNDEFINED
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numPhysVecRegs=256
numROBEntries=192
numRobs=1
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
wait_for_remote_gdb=false
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
opClass=IntDiv
opLat=20
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.fuPool.FUList3.opList3]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList4.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList3]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=Process
cmd=insttest
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

1155
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.json Normal file
View File

File diff suppressed because it is too large Load Diff

6
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simerr Executable file
View File

@@ -0,0 +1,6 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest'
info: Increasing stack size by one page.

47
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simout Executable file
View File

@@ -0,0 +1,47 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:25:07
gem5 executing on boldrock, pid 6011
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/o3-timing
Global frequency set at 1000000000000 ticks per second
lr.w/sc.w: PASS
sc.w, no preceding lr.d: PASS
amoswap.w: PASS
amoswap.w, sign extend: PASS
amoswap.w, truncate: PASS
amoadd.w: PASS
amoadd.w, truncate/overflow: PASS
amoadd.w, sign extend: PASS
amoxor.w, truncate: PASS
amoxor.w, sign extend: PASS
amoand.w, truncate: PASS
amoand.w, sign extend: PASS
amoor.w, truncate: PASS
amoor.w, sign extend: PASS
amomin.w, truncate: PASS
amomin.w, sign extend: PASS
amomax.w, truncate: PASS
amomax.w, sign extend: PASS
amominu.w, truncate: PASS
amominu.w, sign extend: PASS
amomaxu.w, truncate: PASS
amomaxu.w, sign extend: PASS
lr.d/sc.d: PASS
sc.d, no preceding lr.d: PASS
amoswap.d: PASS
amoadd.d: PASS
amoadd.d, overflow: PASS
amoxor.d (1): PASS
amoxor.d (0): PASS
amoand.d: PASS
amoor.d: PASS
amomin.d: PASS
amomax.d: PASS
amominu.d: PASS
amomaxu.d: PASS
Exiting @ tick 125677500 because exiting with last active thread context

1044
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/stats.txt Normal file
View File

File diff suppressed because it is too large Load Diff

11
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini
View File

@@ -88,8 +88,10 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
@@ -118,7 +120,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=insttest
cwd=
drivers=
@@ -127,14 +129,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest
executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100

15
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json
View File

@@ -192,6 +192,7 @@
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
"syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
@@ -216,21 +217,22 @@
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "LiveProcess",
"executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest",
"cxx_class": "Process",
"executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"input": "cin",
"ppid": 99,
"type": "LiveProcess",
"maxStackSize": 67108864,
"ppid": 0,
"type": "Process",
"cwd": "",
"pgid": 100,
"simpoint": 0,
"euid": 100,
"input": "cin",
"path": "system.cpu.workload",
"max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
@@ -242,6 +244,7 @@
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,

6
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr
View File

@@ -1,3 +1,5 @@
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest'
info: Increasing stack size by one page.

12
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout
View File

@@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:29
gem5 executing on zizzer, pid 34062
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-atomic
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:10:21
gem5 executing on boldrock, pid 1519
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
lr.w/sc.w: PASS
sc.w, no preceding lr.d: PASS
amoswap.w: PASS
@@ -46,4 +44,4 @@ amomin.d: PASS
amomax.d: PASS
amominu.d: PASS
amomaxu.d: PASS
Exiting @ tick 57010500 because target called exit()
Exiting @ tick 68573500 because exiting with last active thread context

308
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt
View File

@@ -1,156 +1,160 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000057 # Number of seconds simulated
sim_ticks 57010500 # Number of ticks simulated
final_tick 57010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 83371 # Simulator instruction rate (inst/s)
host_op_rate 83392 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 41711101 # Simulator tick rate (ticks/s)
host_mem_usage 233576 # Number of bytes of host memory used
host_seconds 1.37 # Real time elapsed on the host
sim_insts 113947 # Number of instructions simulated
sim_ops 113978 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 455964 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 156854 # Number of bytes read from this memory
system.physmem.bytes_read::total 612818 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 455964 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 455964 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 111519 # Number of bytes written to this memory
system.physmem.bytes_written::total 111519 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 113991 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 23779 # Number of read requests responded to by this memory
system.physmem.num_reads::total 137770 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 19912 # Number of write requests responded to by this memory
system.physmem.num_writes::total 19912 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7997895125 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2751317740 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10749212864 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7997895125 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7997895125 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1956113348 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1956113348 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7997895125 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4707431087 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12705326212 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.numSyscalls 43 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 57010500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 114022 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 113947 # Number of instructions committed
system.cpu.committedOps 113978 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 113979 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 8601 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 17313 # number of instructions that are conditional controls
system.cpu.num_int_insts 113979 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 152039 # number of times the integer registers were read
system.cpu.num_int_register_writes 76786 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 43694 # number of memory refs
system.cpu.num_load_insts 23779 # Number of load instructions
system.cpu.num_store_insts 19915 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 114022 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 25914 # Number of branches fetched
system.cpu.op_class::No_OpClass 43 0.04% 0.04% # Class of executed instruction
system.cpu.op_class::IntAlu 70180 61.55% 61.59% # Class of executed instruction
system.cpu.op_class::IntMult 105 0.09% 61.68% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::MemRead 23779 20.85% 82.53% # Class of executed instruction
system.cpu.op_class::MemWrite 19915 17.47% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 114022 # Class of executed instruction
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 137768 # Transaction distribution
system.membus.trans_dist::ReadResp 137770 # Transaction distribution
system.membus.trans_dist::WriteReq 19910 # Transaction distribution
system.membus.trans_dist::WriteResp 19910 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 2 # Transaction distribution
system.membus.trans_dist::StoreCondReq 4 # Transaction distribution
system.membus.trans_dist::StoreCondResp 4 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 227982 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 87386 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 315368 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 455964 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 268385 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 724349 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 157684 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 157684 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 157684 # Request fanout histogram
sim_seconds 0.000069
sim_ticks 68573500
final_tick 68573500
sim_freq 1000000000000
host_inst_rate 3619
host_op_rate 3627
host_tick_rate 2266534
host_mem_usage 259192
host_seconds 30.26
sim_insts 109485
sim_ops 109730
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
system.physmem.pwrStateResidencyTicks::UNDEFINED 68573500
system.physmem.bytes_read::cpu.inst 547612
system.physmem.bytes_read::cpu.data 174025
system.physmem.bytes_read::total 721637
system.physmem.bytes_inst_read::cpu.inst 547612
system.physmem.bytes_inst_read::total 547612
system.physmem.bytes_written::cpu.data 113591
system.physmem.bytes_written::total 113591
system.physmem.num_reads::cpu.inst 136903
system.physmem.num_reads::cpu.data 25597
system.physmem.num_reads::total 162500
system.physmem.num_writes::cpu.data 16677
system.physmem.num_writes::total 16677
system.physmem.bw_read::cpu.inst 7985767097
system.physmem.bw_read::cpu.data 2537787921
system.physmem.bw_read::total 10523555018
system.physmem.bw_inst_read::cpu.inst 7985767097
system.physmem.bw_inst_read::total 7985767097
system.physmem.bw_write::cpu.data 1656485377
system.physmem.bw_write::total 1656485377
system.physmem.bw_total::cpu.inst 7985767097
system.physmem.bw_total::cpu.data 4194273298
system.physmem.bw_total::total 12180040395
system.pwrStateResidencyTicks::UNDEFINED 68573500
system.cpu_clk_domain.clock 500
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
system.cpu.dtb.read_accesses 0
system.cpu.dtb.write_hits 0
system.cpu.dtb.write_misses 0
system.cpu.dtb.write_accesses 0
system.cpu.dtb.hits 0
system.cpu.dtb.misses 0
system.cpu.dtb.accesses 0
system.cpu.itb.read_hits 0
system.cpu.itb.read_misses 0
system.cpu.itb.read_accesses 0
system.cpu.itb.write_hits 0
system.cpu.itb.write_misses 0
system.cpu.itb.write_accesses 0
system.cpu.itb.hits 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 43
system.cpu.pwrStateResidencyTicks::ON 68573500
system.cpu.numCycles 137148
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
system.cpu.committedInsts 109485
system.cpu.committedOps 109730
system.cpu.num_int_alu_accesses 109164
system.cpu.num_fp_alu_accesses 12
system.cpu.num_vec_alu_accesses 0
system.cpu.num_func_calls 6221
system.cpu.num_conditional_control_insts 18218
system.cpu.num_int_insts 109164
system.cpu.num_fp_insts 12
system.cpu.num_vec_insts 0
system.cpu.num_int_register_reads 137211
system.cpu.num_int_register_writes 72083
system.cpu.num_fp_register_reads 12
system.cpu.num_fp_register_writes 0
system.cpu.num_vec_register_reads 0
system.cpu.num_vec_register_writes 0
system.cpu.num_mem_refs 42276
system.cpu.num_load_insts 25597
system.cpu.num_store_insts 16679
system.cpu.num_idle_cycles 0
system.cpu.num_busy_cycles 137148
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction 0
system.cpu.Branches 24439
system.cpu.op_class::No_OpClass 47 0.04% 0.04%
system.cpu.op_class::IntAlu 67339 61.34% 61.39%
system.cpu.op_class::IntMult 107 0.10% 61.48%
system.cpu.op_class::IntDiv 4 0.00% 61.49%
system.cpu.op_class::FloatAdd 0 0.00% 61.49%
system.cpu.op_class::FloatCmp 0 0.00% 61.49%
system.cpu.op_class::FloatCvt 0 0.00% 61.49%
system.cpu.op_class::FloatMult 0 0.00% 61.49%
system.cpu.op_class::FloatMultAcc 0 0.00% 61.49%
system.cpu.op_class::FloatDiv 0 0.00% 61.49%
system.cpu.op_class::FloatMisc 0 0.00% 61.49%
system.cpu.op_class::FloatSqrt 0 0.00% 61.49%
system.cpu.op_class::SimdAdd 0 0.00% 61.49%
system.cpu.op_class::SimdAddAcc 0 0.00% 61.49%
system.cpu.op_class::SimdAlu 0 0.00% 61.49%
system.cpu.op_class::SimdCmp 0 0.00% 61.49%
system.cpu.op_class::SimdCvt 0 0.00% 61.49%
system.cpu.op_class::SimdMisc 0 0.00% 61.49%
system.cpu.op_class::SimdMult 0 0.00% 61.49%
system.cpu.op_class::SimdMultAcc 0 0.00% 61.49%
system.cpu.op_class::SimdShift 0 0.00% 61.49%
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.49%
system.cpu.op_class::SimdSqrt 0 0.00% 61.49%
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.49%
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.49%
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.49%
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.49%
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.49%
system.cpu.op_class::SimdFloatMisc 0 0.00% 61.49%
system.cpu.op_class::SimdFloatMult 0 0.00% 61.49%
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.49%
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.49%
system.cpu.op_class::MemRead 25597 23.32% 84.81%
system.cpu.op_class::MemWrite 16667 15.18% 99.99%
system.cpu.op_class::FloatMemRead 0 0.00% 99.99%
system.cpu.op_class::FloatMemWrite 12 0.01% 100.00%
system.cpu.op_class::IprAccess 0 0.00% 100.00%
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
system.cpu.op_class::total 109773
system.membus.snoop_filter.tot_requests 0
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
system.membus.pwrStateResidencyTicks::UNDEFINED 68573500
system.membus.trans_dist::ReadReq 162224
system.membus.trans_dist::ReadResp 162500
system.membus.trans_dist::WriteReq 16401
system.membus.trans_dist::WriteResp 16401
system.membus.trans_dist::LoadLockedReq 276
system.membus.trans_dist::StoreCondReq 276
system.membus.trans_dist::StoreCondResp 276
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 273806
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 84548
system.membus.pkt_count::total 358354
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 547612
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 287616
system.membus.pkt_size::total 835228
system.membus.snoops 0
system.membus.snoopTraffic 0
system.membus.snoop_fanout::samples 179177
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev 0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
system.membus.snoop_fanout::0 179177 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
system.membus.snoop_fanout::total 179177
---------- End Simulation Statistics ----------

19
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini
View File

@@ -85,8 +85,10 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
@@ -122,7 +124,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=insttest
cwd=
drivers=
@@ -131,14 +133,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest
executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100
@@ -266,6 +269,7 @@ voltage_domain=system.voltage_domain
[system.ruby.dir_cntrl0]
type=Directory_Controller
children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory
addr_ranges=0:268435455:5:0:0:0
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
@@ -288,16 +292,14 @@ responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
ruby_system=system.ruby
system=system
to_memory_controller_latency=1
transitions_per_cycle=4
transitions_per_cycle=32
version=0
memory=system.mem_ctrls.port
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
addr_ranges=0:268435455:5:0:0:0
eventq_index=0
numa_high_bit=5
size=268435456
version=0
[system.ruby.dir_cntrl0.dmaRequestToDir]
type=MessageBuffer
@@ -349,6 +351,7 @@ randomization=false
[system.ruby.l1_cntrl0]
type=L1Cache_Controller
children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer
addr_ranges=0:18446744073709551615:0:0:0:0
buffer_size=0
cacheMemory=system.ruby.l1_cntrl0.cacheMemory
cache_response_latency=12

35
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json
View File

@@ -115,7 +115,6 @@
"path": "system.ruby.l1_cntrl0.requestFromCache",
"type": "MessageBuffer"
},
"cxx_class": "L1Cache_Controller",
"forwardToCache": {
"ordered": true,
"name": "forwardToCache",
@@ -168,8 +167,9 @@
"support_data_reqs": true,
"is_cpu_sequencer": true
},
"type": "L1Cache_Controller",
"cxx_class": "L1Cache_Controller",
"issue_latency": 2,
"type": "L1Cache_Controller",
"recycle_latency": 10,
"clk_domain": "system.cpu.clk_domain",
"version": 0,
@@ -241,6 +241,9 @@
},
"ruby_system": "system.ruby",
"name": "l1_cntrl0",
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"p_state_clk_gate_bins": 20,
"mandatoryQueue": {
"ordered": false,
@@ -1447,12 +1450,15 @@
"path": "system.ruby.dir_cntrl0.responseFromDir",
"type": "MessageBuffer"
},
"transitions_per_cycle": 4,
"transitions_per_cycle": 32,
"memory": {
"peer": "system.mem_ctrls.port",
"role": "MASTER"
},
"power_model": null,
"addr_ranges": [
"0:268435455:5:0:0:0"
],
"buffer_size": 0,
"ruby_system": "system.ruby",
"requestToDir": {
@@ -1487,13 +1493,13 @@
"p_state_clk_gate_bins": 20,
"directory": {
"name": "directory",
"version": 0,
"addr_ranges": [
"0:268435455:5:0:0:0"
],
"eventq_index": 0,
"cxx_class": "DirectoryMemory",
"path": "system.ruby.dir_cntrl0.directory",
"type": "RubyDirectoryMemory",
"numa_high_bit": 5,
"size": 268435456
"type": "RubyDirectoryMemory"
},
"path": "system.ruby.dir_cntrl0"
}
@@ -1548,6 +1554,7 @@
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1,
"syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
@@ -1572,21 +1579,22 @@
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "LiveProcess",
"executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest",
"cxx_class": "Process",
"executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"input": "cin",
"ppid": 99,
"type": "LiveProcess",
"maxStackSize": 67108864,
"ppid": 0,
"type": "Process",
"cwd": "",
"pgid": 100,
"simpoint": 0,
"euid": 100,
"input": "cin",
"path": "system.cpu.workload",
"max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
@@ -1598,6 +1606,7 @@
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,

8
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr
View File

@@ -4,8 +4,12 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest'
info: Increasing stack size by one page.

48
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout
View File

@@ -3,13 +3,45 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:31
gem5 executing on zizzer, pid 34069
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:11:52
gem5 executing on boldrock, pid 1958
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
lr.w/sc.w: FAIL (expected (-1, 0); found (-1, 1))
Exiting @ tick 796036 because target called exit()
lr.w/sc.w: PASS
sc.w, no preceding lr.d: PASS
amoswap.w: PASS
amoswap.w, sign extend: PASS
amoswap.w, truncate: PASS
amoadd.w: PASS
amoadd.w, truncate/overflow: PASS
amoadd.w, sign extend: PASS
amoxor.w, truncate: PASS
amoxor.w, sign extend: PASS
amoand.w, truncate: PASS
amoand.w, sign extend: PASS
amoor.w, truncate: PASS
amoor.w, sign extend: PASS
amomin.w, truncate: PASS
amomin.w, sign extend: PASS
amomax.w, truncate: PASS
amomax.w, sign extend: PASS
amominu.w, truncate: PASS
amominu.w, sign extend: PASS
amomaxu.w, truncate: PASS
amomaxu.w, sign extend: PASS
lr.d/sc.d: PASS
sc.d, no preceding lr.d: PASS
amoswap.d: PASS
amoadd.d: PASS
amoadd.d, overflow: PASS
amoxor.d (1): PASS
amoxor.d (0): PASS
amoand.d: PASS
amoor.d: PASS
amomin.d: PASS
amomax.d: PASS
amominu.d: PASS
amomaxu.d: PASS
Exiting @ tick 1861905 because exiting with last active thread context

1288
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt
View File

File diff suppressed because it is too large Load Diff

11
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini
View File

@@ -85,8 +85,10 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
@@ -287,7 +289,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=insttest
cwd=
drivers=
@@ -296,14 +298,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest
executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100

15
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json
View File

@@ -292,6 +292,7 @@
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
"syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
@@ -376,21 +377,22 @@
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "LiveProcess",
"executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest",
"cxx_class": "Process",
"executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"input": "cin",
"ppid": 99,
"type": "LiveProcess",
"maxStackSize": 67108864,
"ppid": 0,
"type": "Process",
"cwd": "",
"pgid": 100,
"simpoint": 0,
"euid": 100,
"input": "cin",
"path": "system.cpu.workload",
"max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
@@ -402,6 +404,7 @@
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,

6
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr
View File

@@ -1,3 +1,5 @@
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest'
info: Increasing stack size by one page.

48
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout
View File

@@ -3,13 +3,45 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:30
gem5 executing on zizzer, pid 34063
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:09:50
gem5 executing on boldrock, pid 1346
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
lr.w/sc.w: FAIL (expected (-1, 0); found (-1, 1))
Exiting @ tick 138549500 because target called exit()
lr.w/sc.w: PASS
sc.w, no preceding lr.d: PASS
amoswap.w: PASS
amoswap.w, sign extend: PASS
amoswap.w, truncate: PASS
amoadd.w: PASS
amoadd.w, truncate/overflow: PASS
amoadd.w, sign extend: PASS
amoxor.w, truncate: PASS
amoxor.w, sign extend: PASS
amoand.w, truncate: PASS
amoand.w, sign extend: PASS
amoor.w, truncate: PASS
amoor.w, sign extend: PASS
amomin.w, truncate: PASS
amomin.w, sign extend: PASS
amomax.w, truncate: PASS
amomax.w, sign extend: PASS
amominu.w, truncate: PASS
amominu.w, sign extend: PASS
amomaxu.w, truncate: PASS
amomaxu.w, sign extend: PASS
lr.d/sc.d: PASS
sc.d, no preceding lr.d: PASS
amoswap.d: PASS
amoadd.d: PASS
amoadd.d, overflow: PASS
amoxor.d (1): PASS
amoxor.d (0): PASS
amoand.d: PASS
amoor.d: PASS
amomin.d: PASS
amomax.d: PASS
amominu.d: PASS
amomaxu.d: PASS
Exiting @ tick 250490500 because exiting with last active thread context

1060
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

905
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/config.ini Normal file
View File

@@ -0,0 +1,905 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=MinorCPU
children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=system.cpu.branchPred
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
enableIdling=true
eventq_index=0
executeAllowEarlyMemoryIssue=true
executeBranchDelay=1
executeCommitLimit=2
executeCycleInput=true
executeFuncUnits=system.cpu.executeFuncUnits
executeInputBufferSize=7
executeInputWidth=2
executeIssueLimit=2
executeLSQMaxStoreBufferStoresPerCycle=2
executeLSQRequestsQueueSize=1
executeLSQStoreBufferSize=5
executeLSQTransfersQueueSize=2
executeMaxAccessesInMemory=2
executeMemoryCommitLimit=1
executeMemoryIssueLimit=1
executeMemoryWidth=0
executeSetTraceTimeOnCommit=true
executeSetTraceTimeOnIssue=false
fetch1FetchLimit=1
fetch1LineSnapWidth=0
fetch1LineWidth=0
fetch1ToFetch2BackwardDelay=1
fetch1ToFetch2ForwardDelay=1
fetch2CycleInput=true
fetch2InputBufferSize=2
fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.executeFuncUnits]
type=MinorFUPool
children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
eventq_index=0
funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
[system.cpu.executeFuncUnits.funcUnits0]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits0.timings
[system.cpu.executeFuncUnits.funcUnits0.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits0.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits1]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits1.timings
[system.cpu.executeFuncUnits.funcUnits1.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits1.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits2]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits2.timings
[system.cpu.executeFuncUnits.funcUnits2.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntMult
[system.cpu.executeFuncUnits.funcUnits2.timings]
type=MinorFUTiming
children=opClasses
description=Mul
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
srcRegsRelativeLats=0
suppress=false
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits3]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=9
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
opLat=9
timings=
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntDiv
[system.cpu.executeFuncUnits.funcUnits4]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
opLat=6
timings=system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
eventq_index=0
opClass=FloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
type=MinorOpClass
eventq_index=0
opClass=FloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
type=MinorOpClass
eventq_index=0
opClass=FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
type=MinorFUTiming
children=opClasses
description=FloatSimd
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits5]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
opLat=1
timings=system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1 opClasses2 opClasses3
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2]
type=MinorOpClass
eventq_index=0
opClass=FloatMemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3]
type=MinorOpClass
eventq_index=0
opClass=FloatMemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
description=Mem
eventq_index=0
extraAssumedLat=2
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
srcRegsRelativeLats=1
suppress=false
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits6]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
opLat=1
timings=
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=IprAccess
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=Process
cmd=insttest
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

1214
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/config.json Normal file
View File

File diff suppressed because it is too large Load Diff

6
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/simerr Executable file
View File

@@ -0,0 +1,6 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64c/insttest'
info: Increasing stack size by one page.

66
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/simout Executable file
View File

@@ -0,0 +1,66 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:25:07
gem5 executing on boldrock, pid 6004
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64c/minor-timing
Global frequency set at 1000000000000 ticks per second
c.lwsp: PASS
c.ldsp: PASS
c.fldsp: PASS
c.swsp: PASS
c.sdsp: PASS
c.fsdsp: PASS
c.lw, positive: PASS
c.lw, negative: PASS
c.ld: PASS
c.fld: PASS
c.sw: PASS
c.sd: PASS
c.fsd: PASS
c.j: PASS
c.jr: PASS
c.jalr: PASS
c.beqz, zero: PASS
c.beqz, not zero: PASS
c.bnez, not zero: PASS
c.bnez, zero: PASS
c.li: PASS
c.li, sign extend: PASS
c.lui: PASS
c.addi: PASS
c.addiw: PASS
c.addiw, overflow: PASS
c.addiw, truncate: PASS
c.addi16sp: PASS
c.addi4spn: PASS
c.slli: PASS
c.slli, overflow: PASS
c.srli: PASS
c.srli, overflow: PASS
c.srli, -1: PASS
c.srai: PASS
c.srai, overflow: PASS
c.srai, -1: PASS
c.andi (0): PASS
c.andi (1): PASS
c.mv: PASS
c.add: PASS
c.and (0): PASS
c.and (-1): PASS
c.or (1): PASS
c.or (A): PASS
c.xor (1): PASS
c.xor (0): PASS
c.sub: PASS
c.addw: PASS
c.addw, overflow: PASS
c.addw, truncate: PASS
c.subw: PASS
c.subw, "overflow": PASS
c.subw, truncate: PASS
Exiting @ tick 196383500 because exiting with last active thread context

773
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/stats.txt Normal file
View File

@@ -0,0 +1,773 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000196
sim_ticks 196383500
final_tick 196383500
sim_freq 1000000000000
host_inst_rate 4107
host_op_rate 4117
host_tick_rate 6138676
host_mem_usage 272768
host_seconds 31.99
sim_insts 131410
sim_ops 131710
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
system.physmem.pwrStateResidencyTicks::UNDEFINED 196383500
system.physmem.bytes_read::cpu.inst 63296
system.physmem.bytes_read::cpu.data 29824
system.physmem.bytes_read::total 93120
system.physmem.bytes_inst_read::cpu.inst 63296
system.physmem.bytes_inst_read::total 63296
system.physmem.num_reads::cpu.inst 989
system.physmem.num_reads::cpu.data 466
system.physmem.num_reads::total 1455
system.physmem.bw_read::cpu.inst 322308136
system.physmem.bw_read::cpu.data 151866119
system.physmem.bw_read::total 474174255
system.physmem.bw_inst_read::cpu.inst 322308136
system.physmem.bw_inst_read::total 322308136
system.physmem.bw_total::cpu.inst 322308136
system.physmem.bw_total::cpu.data 151866119
system.physmem.bw_total::total 474174255
system.physmem.readReqs 1455
system.physmem.writeReqs 0
system.physmem.readBursts 1455
system.physmem.writeBursts 0
system.physmem.bytesReadDRAM 93120
system.physmem.bytesReadWrQ 0
system.physmem.bytesWritten 0
system.physmem.bytesReadSys 93120
system.physmem.bytesWrittenSys 0
system.physmem.servicedByWrQ 0
system.physmem.mergedWrBursts 0
system.physmem.neitherReadNorWriteReqs 0
system.physmem.perBankRdBursts::0 117
system.physmem.perBankRdBursts::1 145
system.physmem.perBankRdBursts::2 103
system.physmem.perBankRdBursts::3 116
system.physmem.perBankRdBursts::4 49
system.physmem.perBankRdBursts::5 67
system.physmem.perBankRdBursts::6 49
system.physmem.perBankRdBursts::7 24
system.physmem.perBankRdBursts::8 76
system.physmem.perBankRdBursts::9 112
system.physmem.perBankRdBursts::10 175
system.physmem.perBankRdBursts::11 146
system.physmem.perBankRdBursts::12 109
system.physmem.perBankRdBursts::13 48
system.physmem.perBankRdBursts::14 52
system.physmem.perBankRdBursts::15 67
system.physmem.perBankWrBursts::0 0
system.physmem.perBankWrBursts::1 0
system.physmem.perBankWrBursts::2 0
system.physmem.perBankWrBursts::3 0
system.physmem.perBankWrBursts::4 0
system.physmem.perBankWrBursts::5 0
system.physmem.perBankWrBursts::6 0
system.physmem.perBankWrBursts::7 0
system.physmem.perBankWrBursts::8 0
system.physmem.perBankWrBursts::9 0
system.physmem.perBankWrBursts::10 0
system.physmem.perBankWrBursts::11 0
system.physmem.perBankWrBursts::12 0
system.physmem.perBankWrBursts::13 0
system.physmem.perBankWrBursts::14 0
system.physmem.perBankWrBursts::15 0
system.physmem.numRdRetry 0
system.physmem.numWrRetry 0
system.physmem.totGap 196287000
system.physmem.readPktSize::0 0
system.physmem.readPktSize::1 0
system.physmem.readPktSize::2 0
system.physmem.readPktSize::3 0
system.physmem.readPktSize::4 0
system.physmem.readPktSize::5 0
system.physmem.readPktSize::6 1455
system.physmem.writePktSize::0 0
system.physmem.writePktSize::1 0
system.physmem.writePktSize::2 0
system.physmem.writePktSize::3 0
system.physmem.writePktSize::4 0
system.physmem.writePktSize::5 0
system.physmem.writePktSize::6 0
system.physmem.rdQLenPdf::0 1237
system.physmem.rdQLenPdf::1 201
system.physmem.rdQLenPdf::2 17
system.physmem.rdQLenPdf::3 0
system.physmem.rdQLenPdf::4 0
system.physmem.rdQLenPdf::5 0
system.physmem.rdQLenPdf::6 0
system.physmem.rdQLenPdf::7 0
system.physmem.rdQLenPdf::8 0
system.physmem.rdQLenPdf::9 0
system.physmem.rdQLenPdf::10 0
system.physmem.rdQLenPdf::11 0
system.physmem.rdQLenPdf::12 0
system.physmem.rdQLenPdf::13 0
system.physmem.rdQLenPdf::14 0
system.physmem.rdQLenPdf::15 0
system.physmem.rdQLenPdf::16 0
system.physmem.rdQLenPdf::17 0
system.physmem.rdQLenPdf::18 0
system.physmem.rdQLenPdf::19 0
system.physmem.rdQLenPdf::20 0
system.physmem.rdQLenPdf::21 0
system.physmem.rdQLenPdf::22 0
system.physmem.rdQLenPdf::23 0
system.physmem.rdQLenPdf::24 0
system.physmem.rdQLenPdf::25 0
system.physmem.rdQLenPdf::26 0
system.physmem.rdQLenPdf::27 0
system.physmem.rdQLenPdf::28 0
system.physmem.rdQLenPdf::29 0
system.physmem.rdQLenPdf::30 0
system.physmem.rdQLenPdf::31 0
system.physmem.wrQLenPdf::0 0
system.physmem.wrQLenPdf::1 0
system.physmem.wrQLenPdf::2 0
system.physmem.wrQLenPdf::3 0
system.physmem.wrQLenPdf::4 0
system.physmem.wrQLenPdf::5 0
system.physmem.wrQLenPdf::6 0
system.physmem.wrQLenPdf::7 0
system.physmem.wrQLenPdf::8 0
system.physmem.wrQLenPdf::9 0
system.physmem.wrQLenPdf::10 0
system.physmem.wrQLenPdf::11 0
system.physmem.wrQLenPdf::12 0
system.physmem.wrQLenPdf::13 0
system.physmem.wrQLenPdf::14 0
system.physmem.wrQLenPdf::15 0
system.physmem.wrQLenPdf::16 0
system.physmem.wrQLenPdf::17 0
system.physmem.wrQLenPdf::18 0
system.physmem.wrQLenPdf::19 0
system.physmem.wrQLenPdf::20 0
system.physmem.wrQLenPdf::21 0
system.physmem.wrQLenPdf::22 0
system.physmem.wrQLenPdf::23 0
system.physmem.wrQLenPdf::24 0
system.physmem.wrQLenPdf::25 0
system.physmem.wrQLenPdf::26 0
system.physmem.wrQLenPdf::27 0
system.physmem.wrQLenPdf::28 0
system.physmem.wrQLenPdf::29 0
system.physmem.wrQLenPdf::30 0
system.physmem.wrQLenPdf::31 0
system.physmem.wrQLenPdf::32 0
system.physmem.wrQLenPdf::33 0
system.physmem.wrQLenPdf::34 0
system.physmem.wrQLenPdf::35 0
system.physmem.wrQLenPdf::36 0
system.physmem.wrQLenPdf::37 0
system.physmem.wrQLenPdf::38 0
system.physmem.wrQLenPdf::39 0
system.physmem.wrQLenPdf::40 0
system.physmem.wrQLenPdf::41 0
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system.physmem.wrQLenPdf::43 0
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system.physmem.wrQLenPdf::45 0
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system.physmem.wrQLenPdf::56 0
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system.physmem.wrQLenPdf::59 0
system.physmem.wrQLenPdf::60 0
system.physmem.wrQLenPdf::61 0
system.physmem.wrQLenPdf::62 0
system.physmem.wrQLenPdf::63 0
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system.physmem.bytesPerActivate::mean 305.165562
system.physmem.bytesPerActivate::gmean 204.277568
system.physmem.bytesPerActivate::stdev 268.702145
system.physmem.bytesPerActivate::0-127 89 29.47% 29.47%
system.physmem.bytesPerActivate::128-255 65 21.52% 50.99%
system.physmem.bytesPerActivate::256-383 50 16.55% 67.54%
system.physmem.bytesPerActivate::384-511 32 10.59% 78.14%
system.physmem.bytesPerActivate::512-639 19 6.29% 84.43%
system.physmem.bytesPerActivate::640-767 20 6.62% 91.05%
system.physmem.bytesPerActivate::768-895 8 2.64% 93.70%
system.physmem.bytesPerActivate::896-1023 5 1.65% 95.36%
system.physmem.bytesPerActivate::1024-1151 14 4.63% 99.99%
system.physmem.bytesPerActivate::total 302
system.physmem.totQLat 18866500
system.physmem.totMemAccLat 46147750
system.physmem.totBusLat 7275000
system.physmem.avgQLat 12966.66
system.physmem.avgBusLat 5000.00
system.physmem.avgMemAccLat 31716.66
system.physmem.avgRdBW 474.17
system.physmem.avgWrBW 0.00
system.physmem.avgRdBWSys 474.17
system.physmem.avgWrBWSys 0.00
system.physmem.peakBW 12800.00
system.physmem.busUtil 3.70
system.physmem.busUtilRead 3.70
system.physmem.busUtilWrite 0.00
system.physmem.avgRdQLen 1.13
system.physmem.avgWrQLen 0.00
system.physmem.readRowHits 1149
system.physmem.writeRowHits 0
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system.physmem.writeRowHitRate nan
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system.physmem.pageHitRate 78.96
system.physmem_0.actEnergy 892500
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system.physmem_0.readEnergy 4783800
system.physmem_0.writeEnergy 0
system.physmem_0.refreshEnergy 15366000
system.physmem_0.actBackEnergy 11874240
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system.physmem_0.actPowerDownEnergy 70338000
system.physmem_0.prePowerDownEnergy 5840160
system.physmem_0.selfRefreshEnergy 0
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system.physmem_0.averagePower 559.644675
system.physmem_0.totalIdleTime 169431500
system.physmem_0.memoryStateTime::IDLE 168000
system.physmem_0.memoryStateTime::REF 6500000
system.physmem_0.memoryStateTime::SREF 0
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system.physmem_0.memoryStateTime::ACT 20238000
system.physmem_0.memoryStateTime::ACT_PDN 154272500
system.physmem_1.actEnergy 1292340
system.physmem_1.preEnergy 675510
system.physmem_1.readEnergy 5604900
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system.physmem_1.refreshEnergy 15366000
system.physmem_1.actBackEnergy 12968070
system.physmem_1.preBackEnergy 367200
system.physmem_1.actPowerDownEnergy 69567360
system.physmem_1.prePowerDownEnergy 5540640
system.physmem_1.selfRefreshEnergy 0
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system.physmem_1.averagePower 567.165154
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system.physmem_1.memoryStateTime::REF 6500000
system.physmem_1.memoryStateTime::SREF 0
system.physmem_1.memoryStateTime::PRE_PDN 14422750
system.physmem_1.memoryStateTime::ACT 22638000
system.physmem_1.memoryStateTime::ACT_PDN 152581250
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system.cpu.branchPred.condPredicted 25966
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system.cpu.branchPred.BTBLookups 28426
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system.cpu.op_class_0::IntDiv 4 0.00% 60.62%
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system.cpu.l2cache.WritebackClean_hits::writebacks 96
system.cpu.l2cache.WritebackClean_hits::total 96
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 11
system.cpu.l2cache.ReadCleanReq_hits::total 11
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1
system.cpu.l2cache.ReadSharedReq_hits::total 1
system.cpu.l2cache.demand_hits::cpu.inst 11
system.cpu.l2cache.demand_hits::cpu.data 1
system.cpu.l2cache.demand_hits::total 12
system.cpu.l2cache.overall_hits::cpu.inst 11
system.cpu.l2cache.overall_hits::cpu.data 1
system.cpu.l2cache.overall_hits::total 12
system.cpu.l2cache.ReadExReq_misses::cpu.data 221
system.cpu.l2cache.ReadExReq_misses::total 221
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 990
system.cpu.l2cache.ReadCleanReq_misses::total 990
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 245
system.cpu.l2cache.ReadSharedReq_misses::total 245
system.cpu.l2cache.demand_misses::cpu.inst 990
system.cpu.l2cache.demand_misses::cpu.data 466
system.cpu.l2cache.demand_misses::total 1456
system.cpu.l2cache.overall_misses::cpu.inst 990
system.cpu.l2cache.overall_misses::cpu.data 466
system.cpu.l2cache.overall_misses::total 1456
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17846000
system.cpu.l2cache.ReadExReq_miss_latency::total 17846000
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 81202500
system.cpu.l2cache.ReadCleanReq_miss_latency::total 81202500
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21332500
system.cpu.l2cache.ReadSharedReq_miss_latency::total 21332500
system.cpu.l2cache.demand_miss_latency::cpu.inst 81202500
system.cpu.l2cache.demand_miss_latency::cpu.data 39178500
system.cpu.l2cache.demand_miss_latency::total 120381000
system.cpu.l2cache.overall_miss_latency::cpu.inst 81202500
system.cpu.l2cache.overall_miss_latency::cpu.data 39178500
system.cpu.l2cache.overall_miss_latency::total 120381000
system.cpu.l2cache.WritebackClean_accesses::writebacks 96
system.cpu.l2cache.WritebackClean_accesses::total 96
system.cpu.l2cache.ReadExReq_accesses::cpu.data 221
system.cpu.l2cache.ReadExReq_accesses::total 221
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1001
system.cpu.l2cache.ReadCleanReq_accesses::total 1001
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 246
system.cpu.l2cache.ReadSharedReq_accesses::total 246
system.cpu.l2cache.demand_accesses::cpu.inst 1001
system.cpu.l2cache.demand_accesses::cpu.data 467
system.cpu.l2cache.demand_accesses::total 1468
system.cpu.l2cache.overall_accesses::cpu.inst 1001
system.cpu.l2cache.overall_accesses::cpu.data 467
system.cpu.l2cache.overall_accesses::total 1468
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1
system.cpu.l2cache.ReadExReq_miss_rate::total 1
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.989010
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.989010
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.995934
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.995934
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.989010
system.cpu.l2cache.demand_miss_rate::cpu.data 0.997858
system.cpu.l2cache.demand_miss_rate::total 0.991825
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.989010
system.cpu.l2cache.overall_miss_rate::cpu.data 0.997858
system.cpu.l2cache.overall_miss_rate::total 0.991825
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80751.131221
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80751.131221
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82022.727272
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82022.727272
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87071.428571
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87071.428571
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82022.727272
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84074.034334
system.cpu.l2cache.demand_avg_miss_latency::total 82679.258241
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82022.727272
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84074.034334
system.cpu.l2cache.overall_avg_miss_latency::total 82679.258241
system.cpu.l2cache.blocked_cycles::no_mshrs 0
system.cpu.l2cache.blocked_cycles::no_targets 0
system.cpu.l2cache.blocked::no_mshrs 0
system.cpu.l2cache.blocked::no_targets 0
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 221
system.cpu.l2cache.ReadExReq_mshr_misses::total 221
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 990
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 990
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 245
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 245
system.cpu.l2cache.demand_mshr_misses::cpu.inst 990
system.cpu.l2cache.demand_mshr_misses::cpu.data 466
system.cpu.l2cache.demand_mshr_misses::total 1456
system.cpu.l2cache.overall_mshr_misses::cpu.inst 990
system.cpu.l2cache.overall_mshr_misses::cpu.data 466
system.cpu.l2cache.overall_mshr_misses::total 1456
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15636000
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15636000
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 71312500
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 71312500
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18882500
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18882500
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71312500
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 34518500
system.cpu.l2cache.demand_mshr_miss_latency::total 105831000
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71312500
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 34518500
system.cpu.l2cache.overall_mshr_miss_latency::total 105831000
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.989010
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.989010
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.995934
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.995934
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.989010
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.997858
system.cpu.l2cache.demand_mshr_miss_rate::total 0.991825
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.989010
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.997858
system.cpu.l2cache.overall_mshr_miss_rate::total 0.991825
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70751.131221
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70751.131221
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72032.828282
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72032.828282
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77071.428571
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77071.428571
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72032.828282
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74074.034334
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72686.126373
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72032.828282
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74074.034334
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72686.126373
system.cpu.toL2Bus.snoop_filter.tot_requests 1564
system.cpu.toL2Bus.snoop_filter.hit_single_requests 97
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
system.cpu.toL2Bus.snoop_filter.tot_snoops 0
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 196383500
system.cpu.toL2Bus.trans_dist::ReadResp 1246
system.cpu.toL2Bus.trans_dist::WritebackClean 96
system.cpu.toL2Bus.trans_dist::ReadExReq 221
system.cpu.toL2Bus.trans_dist::ReadExResp 221
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1001
system.cpu.toL2Bus.trans_dist::ReadSharedReq 246
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2097
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 934
system.cpu.toL2Bus.pkt_count::total 3031
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70144
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29888
system.cpu.toL2Bus.pkt_size::total 100032
system.cpu.toL2Bus.snoops 0
system.cpu.toL2Bus.snoopTraffic 0
system.cpu.toL2Bus.snoop_fanout::samples 1468
system.cpu.toL2Bus.snoop_fanout::mean 0.000681
system.cpu.toL2Bus.snoop_fanout::stdev 0.026099
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
system.cpu.toL2Bus.snoop_fanout::0 1467 99.93% 99.93%
system.cpu.toL2Bus.snoop_fanout::1 1 0.06% 99.99%
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 99.99%
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 99.99%
system.cpu.toL2Bus.snoop_fanout::min_value 0
system.cpu.toL2Bus.snoop_fanout::max_value 1
system.cpu.toL2Bus.snoop_fanout::total 1468
system.cpu.toL2Bus.reqLayer0.occupancy 878000
system.cpu.toL2Bus.reqLayer0.utilization 0.4
system.cpu.toL2Bus.respLayer0.occupancy 1500000
system.cpu.toL2Bus.respLayer0.utilization 0.7
system.cpu.toL2Bus.respLayer1.occupancy 700500
system.cpu.toL2Bus.respLayer1.utilization 0.3
system.membus.snoop_filter.tot_requests 1455
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
system.membus.pwrStateResidencyTicks::UNDEFINED 196383500
system.membus.trans_dist::ReadResp 1234
system.membus.trans_dist::ReadExReq 221
system.membus.trans_dist::ReadExResp 221
system.membus.trans_dist::ReadSharedReq 1234
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2910
system.membus.pkt_count::total 2910
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 93120
system.membus.pkt_size::total 93120
system.membus.snoops 0
system.membus.snoopTraffic 0
system.membus.snoop_fanout::samples 1455
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev -0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
system.membus.snoop_fanout::0 1455 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
system.membus.snoop_fanout::total 1455
system.membus.reqLayer0.occupancy 1688000
system.membus.reqLayer0.utilization 0.8
system.membus.respLayer1.occupancy 7746500
system.membus.respLayer1.utilization 3.9
---------- End Simulation Statistics ----------

876
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/config.ini Normal file
View File

@@ -0,0 +1,876 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
default_p_state=UNDEFINED
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numPhysVecRegs=256
numROBEntries=192
numRobs=1
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
wait_for_remote_gdb=false
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
opClass=IntDiv
opLat=20
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.fuPool.FUList3.opList3]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList4.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList3]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=Process
cmd=insttest
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

1155
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/config.json Normal file
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File diff suppressed because it is too large Load Diff

6
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/simerr Executable file
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@@ -0,0 +1,6 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64c/insttest'
info: Increasing stack size by one page.

66
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/simout Executable file
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@@ -0,0 +1,66 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:25:07
gem5 executing on boldrock, pid 6007
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64c/o3-timing
Global frequency set at 1000000000000 ticks per second
c.lwsp: PASS
c.ldsp: PASS
c.fldsp: PASS
c.swsp: PASS
c.sdsp: PASS
c.fsdsp: PASS
c.lw, positive: PASS
c.lw, negative: PASS
c.ld: PASS
c.fld: PASS
c.sw: PASS
c.sd: PASS
c.fsd: PASS
c.j: PASS
c.jr: PASS
c.jalr: PASS
c.beqz, zero: PASS
c.beqz, not zero: PASS
c.bnez, not zero: PASS
c.bnez, zero: PASS
c.li: PASS
c.li, sign extend: PASS
c.lui: PASS
c.addi: PASS
c.addiw: PASS
c.addiw, overflow: PASS
c.addiw, truncate: PASS
c.addi16sp: PASS
c.addi4spn: PASS
c.slli: PASS
c.slli, overflow: PASS
c.srli: PASS
c.srli, overflow: PASS
c.srli, -1: PASS
c.srai: PASS
c.srai, overflow: PASS
c.srai, -1: PASS
c.andi (0): PASS
c.andi (1): PASS
c.mv: PASS
c.add: PASS
c.and (0): PASS
c.and (-1): PASS
c.or (1): PASS
c.or (A): PASS
c.xor (1): PASS
c.xor (0): PASS
c.sub: PASS
c.addw: PASS
c.addw, overflow: PASS
c.addw, truncate: PASS
c.subw: PASS
c.subw, "overflow": PASS
c.subw, truncate: PASS
Exiting @ tick 141034000 because exiting with last active thread context

1051
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/stats.txt Normal file
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File diff suppressed because it is too large Load Diff

214
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/config.ini Normal file
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@@ -0,0 +1,214 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=Process
cmd=insttest
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

292
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/config.json Normal file
View File

@@ -0,0 +1,292 @@
{
"name": null,
"sim_quantum": 0,
"system": {
"kernel": "",
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"point_of_coherency": true,
"system": "system",
"response_latency": 2,
"cxx_class": "CoherentXBar",
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"width": 16,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 3,
"slave": {
"peer": [
"system.system_port",
"system.cpu.icache_port",
"system.cpu.dcache_port"
],
"role": "SLAVE"
},
"p_state_clk_gate_min": 1000,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
"max_capacity": 8388608,
"eventq_index": 0,
"cxx_class": "SnoopFilter",
"path": "system.membus.snoop_filter",
"type": "SnoopFilter",
"lookup_latency": 1
},
"power_model": null,
"path": "system.membus",
"snoop_response_latency": 4,
"name": "membus",
"p_state_clk_gate_bins": 20,
"use_default_range": false
},
"symbolfile": "",
"readfile": "",
"thermal_model": null,
"cxx_class": "System",
"work_begin_cpu_id_exit": -1,
"load_offset": 0,
"work_begin_exit_count": 0,
"p_state_clk_gate_min": 1000,
"memories": [
"system.physmem"
],
"work_begin_ckpt_count": 0,
"clk_domain": {
"name": "clk_domain",
"clock": [
1000
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"mem_ranges": [],
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"dvfs_handler": {
"enable": false,
"name": "dvfs_handler",
"sys_clk_domain": "system.clk_domain",
"transition_latency": 100000000,
"eventq_index": 0,
"cxx_class": "DVFSHandler",
"domains": [],
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "System",
"voltage_domain": {
"name": "voltage_domain",
"eventq_index": 0,
"voltage": [
"1.0"
],
"cxx_class": "VoltageDomain",
"path": "system.voltage_domain",
"type": "VoltageDomain"
},
"cache_line_size": 64,
"boot_osflags": "a",
"system_port": {
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"physmem": {
"range": "0:134217727:0:0:0:0",
"latency": 30000,
"name": "physmem",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"kvm_map": true,
"clk_domain": "system.clk_domain",
"power_model": null,
"latency_var": 0,
"bandwidth": "73.000000",
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"p_state_clk_gate_max": 1000000000000,
"path": "system.physmem",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[0]",
"role": "SLAVE"
},
"in_addr_map": true
},
"power_model": null,
"work_cpus_ckpt_count": 0,
"thermal_components": [],
"path": "system",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
"clock": [
500
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.cpu_clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"work_end_ckpt_count": 0,
"mem_mode": "atomic",
"name": "system",
"init_param": 0,
"p_state_clk_gate_bins": 20,
"load_addr_mask": 1099511627775,
"cpu": [
{
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
"name": "itb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.itb",
"type": "RiscvTLB",
"size": 64
},
"simulate_data_stalls": false,
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "AtomicSimpleCPU",
"max_loads_all_threads": 0,
"system": "system",
"clk_domain": "system.cpu_clk_domain",
"function_trace_start": 0,
"cpu_id": 0,
"width": 1,
"checker": null,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"do_quiesce": true,
"type": "AtomicSimpleCPU",
"fastmem": false,
"profile": 0,
"icache_port": {
"peer": "system.membus.slave[1]",
"role": "MASTER"
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
"syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
"path": "system.cpu.interrupts",
"type": "RiscvInterrupts",
"name": "interrupts",
"cxx_class": "RiscvISA::Interrupts"
}
],
"dcache_port": {
"peer": "system.membus.slave[2]",
"role": "MASTER"
},
"socket_id": 0,
"power_model": null,
"max_insts_all_threads": 0,
"path": "system.cpu",
"max_loads_any_thread": 0,
"switched_out": false,
"workload": [
{
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "Process",
"executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"maxStackSize": 67108864,
"ppid": 0,
"type": "Process",
"cwd": "",
"pgid": 100,
"simpoint": 0,
"euid": 100,
"input": "cin",
"path": "system.cpu.workload",
"name": "workload",
"cmd": [
"insttest"
],
"errout": "cerr",
"useArchPT": false,
"egid": 100,
"output": "cout"
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.dtb",
"type": "RiscvTLB",
"size": 64
},
"simpoint_start_insts": [],
"max_insts_any_thread": 0,
"simulate_inst_stalls": false,
"progress_interval": 0,
"branchPred": null,
"isa": [
{
"eventq_index": 0,
"path": "system.cpu.isa",
"type": "RiscvISA",
"name": "isa",
"cxx_class": "RiscvISA::ISA"
}
],
"tracer": {
"eventq_index": 0,
"path": "system.cpu.tracer",
"type": "ExeTracer",
"name": "tracer",
"cxx_class": "Trace::ExeTracer"
}
}
],
"multi_thread": false,
"exit_on_work_items": false,
"work_item_id": -1,
"num_work_ids": 16
},
"time_sync_period": 100000000000,
"eventq_index": 0,
"time_sync_spin_threshold": 100000000,
"cxx_class": "Root",
"path": "root",
"time_sync_enable": false,
"type": "Root",
"full_system": false
}

5
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/simerr Executable file
View File

@@ -0,0 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64c/insttest'
info: Increasing stack size by one page.

66
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/simout Executable file
View File

@@ -0,0 +1,66 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:25:07
gem5 executing on boldrock, pid 6005
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64c/simple-atomic
Global frequency set at 1000000000000 ticks per second
c.lwsp: PASS
c.ldsp: PASS
c.fldsp: PASS
c.swsp: PASS
c.sdsp: PASS
c.fsdsp: PASS
c.lw, positive: PASS
c.lw, negative: PASS
c.ld: PASS
c.fld: PASS
c.sw: PASS
c.sd: PASS
c.fsd: PASS
c.j: PASS
c.jr: PASS
c.jalr: PASS
c.beqz, zero: PASS
c.beqz, not zero: PASS
c.bnez, not zero: PASS
c.bnez, zero: PASS
c.li: PASS
c.li, sign extend: PASS
c.lui: PASS
c.addi: PASS
c.addiw: PASS
c.addiw, overflow: PASS
c.addiw, truncate: PASS
c.addi16sp: PASS
c.addi4spn: PASS
c.slli: PASS
c.slli, overflow: PASS
c.srli: PASS
c.srli, overflow: PASS
c.srli, -1: PASS
c.srai: PASS
c.srai, overflow: PASS
c.srai, -1: PASS
c.andi (0): PASS
c.andi (1): PASS
c.mv: PASS
c.add: PASS
c.and (0): PASS
c.and (-1): PASS
c.or (1): PASS
c.or (A): PASS
c.xor (1): PASS
c.xor (0): PASS
c.sub: PASS
c.addw: PASS
c.addw, overflow: PASS
c.addw, truncate: PASS
c.subw: PASS
c.subw, "overflow": PASS
c.subw, truncate: PASS
Exiting @ tick 76505000 because exiting with last active thread context

160
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/stats.txt Normal file
View File

@@ -0,0 +1,160 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000076
sim_ticks 76505000
final_tick 76505000
sim_freq 1000000000000
host_inst_rate 4162
host_op_rate 4172
host_tick_rate 2424659
host_mem_usage 259192
host_seconds 31.55
sim_insts 131348
sim_ops 131648
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
system.physmem.pwrStateResidencyTicks::UNDEFINED 76505000
system.physmem.bytes_read::cpu.inst 610844
system.physmem.bytes_read::cpu.data 214914
system.physmem.bytes_read::total 825758
system.physmem.bytes_inst_read::cpu.inst 610844
system.physmem.bytes_inst_read::total 610844
system.physmem.bytes_written::cpu.data 137066
system.physmem.bytes_written::total 137066
system.physmem.num_reads::cpu.inst 152711
system.physmem.num_reads::cpu.data 31667
system.physmem.num_reads::total 184378
system.physmem.num_writes::cpu.data 20181
system.physmem.num_writes::total 20181
system.physmem.bw_read::cpu.inst 7984367034
system.physmem.bw_read::cpu.data 2809149728
system.physmem.bw_read::total 10793516763
system.physmem.bw_inst_read::cpu.inst 7984367034
system.physmem.bw_inst_read::total 7984367034
system.physmem.bw_write::cpu.data 1791595320
system.physmem.bw_write::total 1791595320
system.physmem.bw_total::cpu.inst 7984367034
system.physmem.bw_total::cpu.data 4600745049
system.physmem.bw_total::total 12585112084
system.pwrStateResidencyTicks::UNDEFINED 76505000
system.cpu_clk_domain.clock 500
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
system.cpu.dtb.read_accesses 0
system.cpu.dtb.write_hits 0
system.cpu.dtb.write_misses 0
system.cpu.dtb.write_accesses 0
system.cpu.dtb.hits 0
system.cpu.dtb.misses 0
system.cpu.dtb.accesses 0
system.cpu.itb.read_hits 0
system.cpu.itb.read_misses 0
system.cpu.itb.read_accesses 0
system.cpu.itb.write_hits 0
system.cpu.itb.write_misses 0
system.cpu.itb.write_accesses 0
system.cpu.itb.hits 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 62
system.cpu.pwrStateResidencyTicks::ON 76505000
system.cpu.numCycles 153011
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
system.cpu.committedInsts 131348
system.cpu.committedOps 131648
system.cpu.num_int_alu_accesses 130924
system.cpu.num_fp_alu_accesses 40
system.cpu.num_vec_alu_accesses 0
system.cpu.num_func_calls 7702
system.cpu.num_conditional_control_insts 21044
system.cpu.num_int_insts 130924
system.cpu.num_fp_insts 40
system.cpu.num_vec_insts 0
system.cpu.num_int_register_reads 163963
system.cpu.num_int_register_writes 87008
system.cpu.num_fp_register_reads 31
system.cpu.num_fp_register_writes 16
system.cpu.num_vec_register_reads 0
system.cpu.num_vec_register_writes 0
system.cpu.num_mem_refs 51848
system.cpu.num_load_insts 31667
system.cpu.num_store_insts 20181
system.cpu.num_idle_cycles -0
system.cpu.num_busy_cycles 153011
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction -0
system.cpu.Branches 28746
system.cpu.op_class::No_OpClass 66 0.05% 0.05%
system.cpu.op_class::IntAlu 79621 60.45% 60.50%
system.cpu.op_class::IntMult 164 0.12% 60.62%
system.cpu.op_class::IntDiv 4 0.00% 60.62%
system.cpu.op_class::FloatAdd 2 0.00% 60.63%
system.cpu.op_class::FloatCmp 3 0.00% 60.63%
system.cpu.op_class::FloatCvt 2 0.00% 60.63%
system.cpu.op_class::FloatMult 0 0.00% 60.63%
system.cpu.op_class::FloatMultAcc 0 0.00% 60.63%
system.cpu.op_class::FloatDiv 0 0.00% 60.63%
system.cpu.op_class::FloatMisc 0 0.00% 60.63%
system.cpu.op_class::FloatSqrt 0 0.00% 60.63%
system.cpu.op_class::SimdAdd 0 0.00% 60.63%
system.cpu.op_class::SimdAddAcc 0 0.00% 60.63%
system.cpu.op_class::SimdAlu 0 0.00% 60.63%
system.cpu.op_class::SimdCmp 0 0.00% 60.63%
system.cpu.op_class::SimdCvt 0 0.00% 60.63%
system.cpu.op_class::SimdMisc 0 0.00% 60.63%
system.cpu.op_class::SimdMult 0 0.00% 60.63%
system.cpu.op_class::SimdMultAcc 0 0.00% 60.63%
system.cpu.op_class::SimdShift 0 0.00% 60.63%
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.63%
system.cpu.op_class::SimdSqrt 0 0.00% 60.63%
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.63%
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.63%
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.63%
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.63%
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.63%
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.63%
system.cpu.op_class::SimdFloatMult 0 0.00% 60.63%
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.63%
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.63%
system.cpu.op_class::MemRead 31653 24.03% 84.66%
system.cpu.op_class::MemWrite 20162 15.30% 99.97%
system.cpu.op_class::FloatMemRead 14 0.01% 99.98%
system.cpu.op_class::FloatMemWrite 19 0.01% 99.99%
system.cpu.op_class::IprAccess 0 0.00% 99.99%
system.cpu.op_class::InstPrefetch 0 0.00% 99.99%
system.cpu.op_class::total 131710
system.membus.snoop_filter.tot_requests 0
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
system.membus.pwrStateResidencyTicks::UNDEFINED 76505000
system.membus.trans_dist::ReadReq 184044
system.membus.trans_dist::ReadResp 184378
system.membus.trans_dist::WriteReq 19847
system.membus.trans_dist::WriteResp 19847
system.membus.trans_dist::LoadLockedReq 334
system.membus.trans_dist::StoreCondReq 334
system.membus.trans_dist::StoreCondResp 334
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 305422
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 103696
system.membus.pkt_count::total 409118
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 610844
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 351980
system.membus.pkt_size::total 962824
system.membus.snoops 0
system.membus.snoopTraffic 0
system.membus.snoop_fanout::samples 204559
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev -0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
system.membus.snoop_fanout::0 204559 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
system.membus.snoop_fanout::total 204559
---------- End Simulation Statistics ----------

1268
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/config.ini Normal file
View File

File diff suppressed because it is too large Load Diff

1743
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/config.json Normal file
View File

File diff suppressed because it is too large Load Diff

15
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/simerr Executable file
View File

@@ -0,0 +1,15 @@
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
info: Entering event queue @ 0. Starting simulation...
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64c/insttest'
info: Increasing stack size by one page.

66
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/simout Executable file
View File

@@ -0,0 +1,66 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:25:07
gem5 executing on boldrock, pid 6003
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
c.lwsp: PASS
c.ldsp: PASS
c.fldsp: PASS
c.swsp: PASS
c.sdsp: PASS
c.fsdsp: PASS
c.lw, positive: PASS
c.lw, negative: PASS
c.ld: PASS
c.fld: PASS
c.sw: PASS
c.sd: PASS
c.fsd: PASS
c.j: PASS
c.jr: PASS
c.jalr: PASS
c.beqz, zero: PASS
c.beqz, not zero: PASS
c.bnez, not zero: PASS
c.bnez, zero: PASS
c.li: PASS
c.li, sign extend: PASS
c.lui: PASS
c.addi: PASS
c.addiw: PASS
c.addiw, overflow: PASS
c.addiw, truncate: PASS
c.addi16sp: PASS
c.addi4spn: PASS
c.slli: PASS
c.slli, overflow: PASS
c.srli: PASS
c.srli, overflow: PASS
c.srli, -1: PASS
c.srai: PASS
c.srai, overflow: PASS
c.srai, -1: PASS
c.andi (0): PASS
c.andi (1): PASS
c.mv: PASS
c.add: PASS
c.and (0): PASS
c.and (-1): PASS
c.or (1): PASS
c.or (A): PASS
c.xor (1): PASS
c.xor (0): PASS
c.sub: PASS
c.addw: PASS
c.addw, overflow: PASS
c.addw, truncate: PASS
c.subw: PASS
c.subw, "overflow": PASS
c.subw, truncate: PASS
Exiting @ tick 2280417 because exiting with last active thread context

739
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing-ruby/stats.txt Normal file
View File

@@ -0,0 +1,739 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.002280
sim_ticks 2280417
final_tick 2280417
sim_freq 1000000000
host_inst_rate 4031
host_op_rate 4040
host_tick_rate 69995
host_mem_usage 438656
host_seconds 32.57
sim_insts 131348
sim_ops 131648
system.voltage_domain.voltage 1
system.clk_domain.clock 1
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 2280417
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 2256640
system.mem_ctrls.bytes_read::total 2256640
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 2256384
system.mem_ctrls.bytes_written::total 2256384
system.mem_ctrls.num_reads::ruby.dir_cntrl0 35260
system.mem_ctrls.num_reads::total 35260
system.mem_ctrls.num_writes::ruby.dir_cntrl0 35256
system.mem_ctrls.num_writes::total 35256
system.mem_ctrls.bw_read::ruby.dir_cntrl0 989573398
system.mem_ctrls.bw_read::total 989573398
system.mem_ctrls.bw_write::ruby.dir_cntrl0 989461138
system.mem_ctrls.bw_write::total 989461138
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1979034536
system.mem_ctrls.bw_total::total 1979034536
system.mem_ctrls.readReqs 35260
system.mem_ctrls.writeReqs 35256
system.mem_ctrls.readBursts 35260
system.mem_ctrls.writeBursts 35256
system.mem_ctrls.bytesReadDRAM 1018944
system.mem_ctrls.bytesReadWrQ 1237696
system.mem_ctrls.bytesWritten 1071232
system.mem_ctrls.bytesReadSys 2256640
system.mem_ctrls.bytesWrittenSys 2256384
system.mem_ctrls.servicedByWrQ 19339
system.mem_ctrls.mergedWrBursts 18496
system.mem_ctrls.neitherReadNorWriteReqs 0
system.mem_ctrls.perBankRdBursts::0 307
system.mem_ctrls.perBankRdBursts::1 1030
system.mem_ctrls.perBankRdBursts::2 505
system.mem_ctrls.perBankRdBursts::3 1507
system.mem_ctrls.perBankRdBursts::4 770
system.mem_ctrls.perBankRdBursts::5 107
system.mem_ctrls.perBankRdBursts::6 87
system.mem_ctrls.perBankRdBursts::7 323
system.mem_ctrls.perBankRdBursts::8 641
system.mem_ctrls.perBankRdBursts::9 1801
system.mem_ctrls.perBankRdBursts::10 1103
system.mem_ctrls.perBankRdBursts::11 2113
system.mem_ctrls.perBankRdBursts::12 820
system.mem_ctrls.perBankRdBursts::13 2610
system.mem_ctrls.perBankRdBursts::14 1268
system.mem_ctrls.perBankRdBursts::15 929
system.mem_ctrls.perBankWrBursts::0 311
system.mem_ctrls.perBankWrBursts::1 1043
system.mem_ctrls.perBankWrBursts::2 526
system.mem_ctrls.perBankWrBursts::3 1565
system.mem_ctrls.perBankWrBursts::4 796
system.mem_ctrls.perBankWrBursts::5 112
system.mem_ctrls.perBankWrBursts::6 89
system.mem_ctrls.perBankWrBursts::7 324
system.mem_ctrls.perBankWrBursts::8 663
system.mem_ctrls.perBankWrBursts::9 1954
system.mem_ctrls.perBankWrBursts::10 1119
system.mem_ctrls.perBankWrBursts::11 2193
system.mem_ctrls.perBankWrBursts::12 843
system.mem_ctrls.perBankWrBursts::13 2940
system.mem_ctrls.perBankWrBursts::14 1307
system.mem_ctrls.perBankWrBursts::15 953
system.mem_ctrls.numRdRetry 0
system.mem_ctrls.numWrRetry 0
system.mem_ctrls.totGap 2280337
system.mem_ctrls.readPktSize::0 0
system.mem_ctrls.readPktSize::1 0
system.mem_ctrls.readPktSize::2 0
system.mem_ctrls.readPktSize::3 0
system.mem_ctrls.readPktSize::4 0
system.mem_ctrls.readPktSize::5 0
system.mem_ctrls.readPktSize::6 35260
system.mem_ctrls.writePktSize::0 0
system.mem_ctrls.writePktSize::1 0
system.mem_ctrls.writePktSize::2 0
system.mem_ctrls.writePktSize::3 0
system.mem_ctrls.writePktSize::4 0
system.mem_ctrls.writePktSize::5 0
system.mem_ctrls.writePktSize::6 35256
system.mem_ctrls.rdQLenPdf::0 15921
system.mem_ctrls.rdQLenPdf::1 0
system.mem_ctrls.rdQLenPdf::2 0
system.mem_ctrls.rdQLenPdf::3 0
system.mem_ctrls.rdQLenPdf::4 0
system.mem_ctrls.rdQLenPdf::5 0
system.mem_ctrls.rdQLenPdf::6 0
system.mem_ctrls.rdQLenPdf::7 0
system.mem_ctrls.rdQLenPdf::8 0
system.mem_ctrls.rdQLenPdf::9 0
system.mem_ctrls.rdQLenPdf::10 0
system.mem_ctrls.rdQLenPdf::11 0
system.mem_ctrls.rdQLenPdf::12 0
system.mem_ctrls.rdQLenPdf::13 0
system.mem_ctrls.rdQLenPdf::14 0
system.mem_ctrls.rdQLenPdf::15 0
system.mem_ctrls.rdQLenPdf::16 0
system.mem_ctrls.rdQLenPdf::17 0
system.mem_ctrls.rdQLenPdf::18 0
system.mem_ctrls.rdQLenPdf::19 0
system.mem_ctrls.rdQLenPdf::20 0
system.mem_ctrls.rdQLenPdf::21 0
system.mem_ctrls.rdQLenPdf::22 0
system.mem_ctrls.rdQLenPdf::23 0
system.mem_ctrls.rdQLenPdf::24 0
system.mem_ctrls.rdQLenPdf::25 0
system.mem_ctrls.rdQLenPdf::26 0
system.mem_ctrls.rdQLenPdf::27 0
system.mem_ctrls.rdQLenPdf::28 0
system.mem_ctrls.rdQLenPdf::29 0
system.mem_ctrls.rdQLenPdf::30 0
system.mem_ctrls.rdQLenPdf::31 0
system.mem_ctrls.wrQLenPdf::0 1
system.mem_ctrls.wrQLenPdf::1 1
system.mem_ctrls.wrQLenPdf::2 1
system.mem_ctrls.wrQLenPdf::3 1
system.mem_ctrls.wrQLenPdf::4 1
system.mem_ctrls.wrQLenPdf::5 1
system.mem_ctrls.wrQLenPdf::6 1
system.mem_ctrls.wrQLenPdf::7 1
system.mem_ctrls.wrQLenPdf::8 1
system.mem_ctrls.wrQLenPdf::9 1
system.mem_ctrls.wrQLenPdf::10 1
system.mem_ctrls.wrQLenPdf::11 1
system.mem_ctrls.wrQLenPdf::12 1
system.mem_ctrls.wrQLenPdf::13 1
system.mem_ctrls.wrQLenPdf::14 1
system.mem_ctrls.wrQLenPdf::15 181
system.mem_ctrls.wrQLenPdf::16 231
system.mem_ctrls.wrQLenPdf::17 903
system.mem_ctrls.wrQLenPdf::18 1029
system.mem_ctrls.wrQLenPdf::19 1037
system.mem_ctrls.wrQLenPdf::20 1062
system.mem_ctrls.wrQLenPdf::21 1102
system.mem_ctrls.wrQLenPdf::22 1057
system.mem_ctrls.wrQLenPdf::23 1015
system.mem_ctrls.wrQLenPdf::24 1016
system.mem_ctrls.wrQLenPdf::25 1013
system.mem_ctrls.wrQLenPdf::26 1013
system.mem_ctrls.wrQLenPdf::27 1016
system.mem_ctrls.wrQLenPdf::28 1013
system.mem_ctrls.wrQLenPdf::29 1015
system.mem_ctrls.wrQLenPdf::30 1014
system.mem_ctrls.wrQLenPdf::31 1013
system.mem_ctrls.wrQLenPdf::32 1013
system.mem_ctrls.wrQLenPdf::33 2
system.mem_ctrls.wrQLenPdf::34 0
system.mem_ctrls.wrQLenPdf::35 0
system.mem_ctrls.wrQLenPdf::36 0
system.mem_ctrls.wrQLenPdf::37 0
system.mem_ctrls.wrQLenPdf::38 0
system.mem_ctrls.wrQLenPdf::39 0
system.mem_ctrls.wrQLenPdf::40 0
system.mem_ctrls.wrQLenPdf::41 0
system.mem_ctrls.wrQLenPdf::42 0
system.mem_ctrls.wrQLenPdf::43 0
system.mem_ctrls.wrQLenPdf::44 0
system.mem_ctrls.wrQLenPdf::45 0
system.mem_ctrls.wrQLenPdf::46 0
system.mem_ctrls.wrQLenPdf::47 0
system.mem_ctrls.wrQLenPdf::48 0
system.mem_ctrls.wrQLenPdf::49 0
system.mem_ctrls.wrQLenPdf::50 0
system.mem_ctrls.wrQLenPdf::51 0
system.mem_ctrls.wrQLenPdf::52 0
system.mem_ctrls.wrQLenPdf::53 0
system.mem_ctrls.wrQLenPdf::54 0
system.mem_ctrls.wrQLenPdf::55 0
system.mem_ctrls.wrQLenPdf::56 0
system.mem_ctrls.wrQLenPdf::57 0
system.mem_ctrls.wrQLenPdf::58 0
system.mem_ctrls.wrQLenPdf::59 0
system.mem_ctrls.wrQLenPdf::60 0
system.mem_ctrls.wrQLenPdf::61 0
system.mem_ctrls.wrQLenPdf::62 0
system.mem_ctrls.wrQLenPdf::63 0
system.mem_ctrls.bytesPerActivate::samples 7008
system.mem_ctrls.bytesPerActivate::mean 297.808219
system.mem_ctrls.bytesPerActivate::gmean 198.709989
system.mem_ctrls.bytesPerActivate::stdev 279.585331
system.mem_ctrls.bytesPerActivate::0-127 1768 25.22% 25.22%
system.mem_ctrls.bytesPerActivate::128-255 2231 31.83% 57.06%
system.mem_ctrls.bytesPerActivate::256-383 891 12.71% 69.77%
system.mem_ctrls.bytesPerActivate::384-511 748 10.67% 80.45%
system.mem_ctrls.bytesPerActivate::512-639 341 4.86% 85.31%
system.mem_ctrls.bytesPerActivate::640-767 239 3.41% 88.72%
system.mem_ctrls.bytesPerActivate::768-895 202 2.88% 91.60%
system.mem_ctrls.bytesPerActivate::896-1023 173 2.46% 94.07%
system.mem_ctrls.bytesPerActivate::1024-1151 415 5.92% 99.99%
system.mem_ctrls.bytesPerActivate::total 7008
system.mem_ctrls.rdPerTurnAround::samples 1013
system.mem_ctrls.rdPerTurnAround::mean 15.711747
system.mem_ctrls.rdPerTurnAround::gmean 15.626594
system.mem_ctrls.rdPerTurnAround::stdev 1.691594
system.mem_ctrls.rdPerTurnAround::12-13 69 6.81% 6.81%
system.mem_ctrls.rdPerTurnAround::14-15 428 42.25% 49.06%
system.mem_ctrls.rdPerTurnAround::16-17 387 38.20% 87.26%
system.mem_ctrls.rdPerTurnAround::18-19 107 10.56% 97.82%
system.mem_ctrls.rdPerTurnAround::20-21 21 2.07% 99.90%
system.mem_ctrls.rdPerTurnAround::34-35 1 0.09% 99.99%
system.mem_ctrls.rdPerTurnAround::total 1013
system.mem_ctrls.wrPerTurnAround::samples 1013
system.mem_ctrls.wrPerTurnAround::mean 16.523198
system.mem_ctrls.wrPerTurnAround::gmean 16.491866
system.mem_ctrls.wrPerTurnAround::stdev 1.053276
system.mem_ctrls.wrPerTurnAround::16 795 78.47% 78.47%
system.mem_ctrls.wrPerTurnAround::17 20 1.97% 80.45%
system.mem_ctrls.wrPerTurnAround::18 93 9.18% 89.63%
system.mem_ctrls.wrPerTurnAround::19 96 9.47% 99.11%
system.mem_ctrls.wrPerTurnAround::20 9 0.88% 99.99%
system.mem_ctrls.wrPerTurnAround::total 1013
system.mem_ctrls.totQLat 316546
system.mem_ctrls.totMemAccLat 619045
system.mem_ctrls.totBusLat 79605
system.mem_ctrls.avgQLat 19.88
system.mem_ctrls.avgBusLat 5.00
system.mem_ctrls.avgMemAccLat 38.88
system.mem_ctrls.avgRdBW 446.82
system.mem_ctrls.avgWrBW 469.75
system.mem_ctrls.avgRdBWSys 989.57
system.mem_ctrls.avgWrBWSys 989.46
system.mem_ctrls.peakBW 12800.00
system.mem_ctrls.busUtil 7.16
system.mem_ctrls.busUtilRead 3.49
system.mem_ctrls.busUtilWrite 3.66
system.mem_ctrls.avgRdQLen 0.99
system.mem_ctrls.avgWrQLen 25.87
system.mem_ctrls.readRowHits 10688
system.mem_ctrls.writeRowHits 14955
system.mem_ctrls.readRowHitRate 67.13
system.mem_ctrls.writeRowHitRate 89.23
system.mem_ctrls.avgGap 32.33
system.mem_ctrls.pageHitRate 78.46
system.mem_ctrls_0.actEnergy 14529900
system.mem_ctrls_0.preEnergy 7847784
system.mem_ctrls_0.readEnergy 52961664
system.mem_ctrls_0.writeEnergy 39805632
system.mem_ctrls_0.refreshEnergy 173328480
system.mem_ctrls_0.actBackEnergy 286548576
system.mem_ctrls_0.preBackEnergy 4581504
system.mem_ctrls_0.actPowerDownEnergy 618489672
system.mem_ctrls_0.prePowerDownEnergy 62474112
system.mem_ctrls_0.selfRefreshEnergy 32367840
system.mem_ctrls_0.totalEnergy 1292935164
system.mem_ctrls_0.averagePower 566.973129
system.mem_ctrls_0.totalIdleTime 1640053
system.mem_ctrls_0.memoryStateTime::IDLE 4041
system.mem_ctrls_0.memoryStateTime::REF 73356
system.mem_ctrls_0.memoryStateTime::SREF 121060
system.mem_ctrls_0.memoryStateTime::PRE_PDN 162693
system.mem_ctrls_0.memoryStateTime::ACT 562930
system.mem_ctrls_0.memoryStateTime::ACT_PDN 1356337
system.mem_ctrls_1.actEnergy 35564340
system.mem_ctrls_1.preEnergy 19231128
system.mem_ctrls_1.readEnergy 128919840
system.mem_ctrls_1.writeEnergy 99990144
system.mem_ctrls_1.refreshEnergy 180704160
system.mem_ctrls_1.actBackEnergy 269818392
system.mem_ctrls_1.preBackEnergy 4233600
system.mem_ctrls_1.actPowerDownEnergy 715528296
system.mem_ctrls_1.prePowerDownEnergy 33203328
system.mem_ctrls_1.selfRefreshEnergy 8059680
system.mem_ctrls_1.totalEnergy 1495252908
system.mem_ctrls_1.averagePower 655.692756
system.mem_ctrls_1.totalIdleTime 1677525
system.mem_ctrls_1.memoryStateTime::IDLE 2762
system.mem_ctrls_1.memoryStateTime::REF 76470
system.mem_ctrls_1.memoryStateTime::SREF 22077
system.mem_ctrls_1.memoryStateTime::PRE_PDN 86467
system.mem_ctrls_1.memoryStateTime::ACT 523500
system.mem_ctrls_1.memoryStateTime::ACT_PDN 1569141
system.pwrStateResidencyTicks::UNDEFINED 2280417
system.cpu.clk_domain.clock 1
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
system.cpu.dtb.read_accesses 0
system.cpu.dtb.write_hits 0
system.cpu.dtb.write_misses 0
system.cpu.dtb.write_accesses 0
system.cpu.dtb.hits 0
system.cpu.dtb.misses 0
system.cpu.dtb.accesses 0
system.cpu.itb.read_hits 0
system.cpu.itb.read_misses 0
system.cpu.itb.read_accesses 0
system.cpu.itb.write_hits 0
system.cpu.itb.write_misses 0
system.cpu.itb.write_accesses 0
system.cpu.itb.hits 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 62
system.cpu.pwrStateResidencyTicks::ON 2280417
system.cpu.numCycles 2280417
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
system.cpu.committedInsts 131348
system.cpu.committedOps 131648
system.cpu.num_int_alu_accesses 130924
system.cpu.num_fp_alu_accesses 40
system.cpu.num_vec_alu_accesses 0
system.cpu.num_func_calls 7702
system.cpu.num_conditional_control_insts 21044
system.cpu.num_int_insts 130924
system.cpu.num_fp_insts 40
system.cpu.num_vec_insts 0
system.cpu.num_int_register_reads 163963
system.cpu.num_int_register_writes 87008
system.cpu.num_fp_register_reads 31
system.cpu.num_fp_register_writes 16
system.cpu.num_vec_register_reads 0
system.cpu.num_vec_register_writes 0
system.cpu.num_mem_refs 51848
system.cpu.num_load_insts 31667
system.cpu.num_store_insts 20181
system.cpu.num_idle_cycles -0
system.cpu.num_busy_cycles 2280417
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction -0
system.cpu.Branches 28746
system.cpu.op_class::No_OpClass 66 0.05% 0.05%
system.cpu.op_class::IntAlu 79621 60.45% 60.50%
system.cpu.op_class::IntMult 164 0.12% 60.62%
system.cpu.op_class::IntDiv 4 0.00% 60.62%
system.cpu.op_class::FloatAdd 2 0.00% 60.63%
system.cpu.op_class::FloatCmp 3 0.00% 60.63%
system.cpu.op_class::FloatCvt 2 0.00% 60.63%
system.cpu.op_class::FloatMult 0 0.00% 60.63%
system.cpu.op_class::FloatMultAcc 0 0.00% 60.63%
system.cpu.op_class::FloatDiv 0 0.00% 60.63%
system.cpu.op_class::FloatMisc 0 0.00% 60.63%
system.cpu.op_class::FloatSqrt 0 0.00% 60.63%
system.cpu.op_class::SimdAdd 0 0.00% 60.63%
system.cpu.op_class::SimdAddAcc 0 0.00% 60.63%
system.cpu.op_class::SimdAlu 0 0.00% 60.63%
system.cpu.op_class::SimdCmp 0 0.00% 60.63%
system.cpu.op_class::SimdCvt 0 0.00% 60.63%
system.cpu.op_class::SimdMisc 0 0.00% 60.63%
system.cpu.op_class::SimdMult 0 0.00% 60.63%
system.cpu.op_class::SimdMultAcc 0 0.00% 60.63%
system.cpu.op_class::SimdShift 0 0.00% 60.63%
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.63%
system.cpu.op_class::SimdSqrt 0 0.00% 60.63%
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.63%
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.63%
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.63%
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.63%
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.63%
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.63%
system.cpu.op_class::SimdFloatMult 0 0.00% 60.63%
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.63%
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.63%
system.cpu.op_class::MemRead 31653 24.03% 84.66%
system.cpu.op_class::MemWrite 20162 15.30% 99.97%
system.cpu.op_class::FloatMemRead 14 0.01% 99.98%
system.cpu.op_class::FloatMemWrite 19 0.01% 99.99%
system.cpu.op_class::IprAccess 0 0.00% 99.99%
system.cpu.op_class::InstPrefetch 0 0.00% 99.99%
system.cpu.op_class::total 131710
system.ruby.clk_domain.clock 1
system.ruby.pwrStateResidencyTicks::UNDEFINED 2280417
system.ruby.delayHist::bucket_size 1
system.ruby.delayHist::max_bucket 9
system.ruby.delayHist::samples 70516
system.ruby.delayHist | 70516 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.delayHist::total 70516
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 204560
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 204560 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 204560
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 204559
system.ruby.latency_hist_seqr::mean 10.147967
system.ruby.latency_hist_seqr::gmean 1.945479
system.ruby.latency_hist_seqr::stdev 24.772910
system.ruby.latency_hist_seqr | 189107 92.44% 92.44% | 14491 7.08% 99.53% | 645 0.31% 99.84% | 109 0.05% 99.89% | 114 0.05% 99.95% | 73 0.03% 99.99% | 9 0.00% 99.99% | 1 0.00% 99.99% | 0 0.00% 99.99% | 10 0.00% 99.99%
system.ruby.latency_hist_seqr::total 204559
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
system.ruby.hit_latency_hist_seqr::samples 169299
system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 169299 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 169299
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 35260
system.ruby.miss_latency_hist_seqr::mean 54.071440
system.ruby.miss_latency_hist_seqr::gmean 47.508689
system.ruby.miss_latency_hist_seqr::stdev 35.060895
system.ruby.miss_latency_hist_seqr | 19808 56.17% 56.17% | 14491 41.09% 97.27% | 645 1.82% 99.10% | 109 0.30% 99.41% | 114 0.32% 99.73% | 73 0.20% 99.94% | 9 0.02% 99.96% | 1 0.00% 99.97% | 0 0.00% 99.97% | 10 0.02% 99.99%
system.ruby.miss_latency_hist_seqr::total 35260
system.ruby.Directory.incomplete_times_seqr 35259
system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015460
system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999835
system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.030922
system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.751966
system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015462
system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999969
system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.030922
system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999970
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 2280417
system.ruby.l1_cntrl0.cacheMemory.demand_hits 169299
system.ruby.l1_cntrl0.cacheMemory.demand_misses 35260
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 204559
system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015460
system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.998827
system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.089702
system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999999
system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061844
system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999997
system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015462
system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999769
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 2280417
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 2280417
system.ruby.memctrl_clk_domain.clock 3
system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015460
system.ruby.network.routers0.port_buffers03.avg_stall_time 5.998997
system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015462
system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999805
system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.092763
system.ruby.network.routers0.port_buffers07.avg_stall_time 6.752001
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 2280417
system.ruby.network.routers0.percent_links_utilized 7.730603
system.ruby.network.routers0.msg_count.Control::2 35260
system.ruby.network.routers0.msg_count.Data::2 35256
system.ruby.network.routers0.msg_count.Response_Data::4 35260
system.ruby.network.routers0.msg_count.Writeback_Control::3 35256
system.ruby.network.routers0.msg_bytes.Control::2 282080
system.ruby.network.routers0.msg_bytes.Data::2 2538432
system.ruby.network.routers0.msg_bytes.Response_Data::4 2538720
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 282048
system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030922
system.ruby.network.routers1.port_buffers02.avg_stall_time 10.751975
system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015460
system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999669
system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015462
system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999938
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 2280417
system.ruby.network.routers1.percent_links_utilized 7.730603
system.ruby.network.routers1.msg_count.Control::2 35260
system.ruby.network.routers1.msg_count.Data::2 35256
system.ruby.network.routers1.msg_count.Response_Data::4 35260
system.ruby.network.routers1.msg_count.Writeback_Control::3 35256
system.ruby.network.routers1.msg_bytes.Control::2 282080
system.ruby.network.routers1.msg_bytes.Data::2 2538432
system.ruby.network.routers1.msg_bytes.Response_Data::4 2538720
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 282048
system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030922
system.ruby.network.int_link_buffers02.avg_stall_time 7.751996
system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015460
system.ruby.network.int_link_buffers08.avg_stall_time 2.999502
system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015462
system.ruby.network.int_link_buffers09.avg_stall_time 2.999906
system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015460
system.ruby.network.int_link_buffers13.avg_stall_time 4.999166
system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015462
system.ruby.network.int_link_buffers14.avg_stall_time 4.999839
system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030922
system.ruby.network.int_link_buffers17.avg_stall_time 9.751983
system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015460
system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999335
system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015462
system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999873
system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030922
system.ruby.network.routers2.port_buffers07.avg_stall_time 8.751990
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 2280417
system.ruby.network.routers2.percent_links_utilized 7.730603
system.ruby.network.routers2.msg_count.Control::2 35260
system.ruby.network.routers2.msg_count.Data::2 35256
system.ruby.network.routers2.msg_count.Response_Data::4 35260
system.ruby.network.routers2.msg_count.Writeback_Control::3 35256
system.ruby.network.routers2.msg_bytes.Control::2 282080
system.ruby.network.routers2.msg_bytes.Data::2 2538432
system.ruby.network.routers2.msg_bytes.Response_Data::4 2538720
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 282048
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 2280417
system.ruby.network.msg_count.Control 105780
system.ruby.network.msg_count.Data 105768
system.ruby.network.msg_count.Response_Data 105780
system.ruby.network.msg_count.Writeback_Control 105768
system.ruby.network.msg_byte.Control 846240
system.ruby.network.msg_byte.Data 7615296
system.ruby.network.msg_byte.Response_Data 7616160
system.ruby.network.msg_byte.Writeback_Control 846144
system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 2280417
system.ruby.network.routers0.throttle0.link_utilization 7.730954
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 35260
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 35256
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 2538720
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 282048
system.ruby.network.routers0.throttle1.link_utilization 7.730252
system.ruby.network.routers0.throttle1.msg_count.Control::2 35260
system.ruby.network.routers0.throttle1.msg_count.Data::2 35256
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 282080
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 2538432
system.ruby.network.routers1.throttle0.link_utilization 7.730252
system.ruby.network.routers1.throttle0.msg_count.Control::2 35260
system.ruby.network.routers1.throttle0.msg_count.Data::2 35256
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 282080
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 2538432
system.ruby.network.routers1.throttle1.link_utilization 7.730954
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 35260
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 35256
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 2538720
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 282048
system.ruby.network.routers2.throttle0.link_utilization 7.730954
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 35260
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 35256
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 2538720
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 282048
system.ruby.network.routers2.throttle1.link_utilization 7.730252
system.ruby.network.routers2.throttle1.msg_count.Control::2 35260
system.ruby.network.routers2.throttle1.msg_count.Data::2 35256
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 282080
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 2538432
system.ruby.delayVCHist.vnet_1::bucket_size 1
system.ruby.delayVCHist.vnet_1::max_bucket 9
system.ruby.delayVCHist.vnet_1::samples 35260
system.ruby.delayVCHist.vnet_1 | 35260 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.delayVCHist.vnet_1::total 35260
system.ruby.delayVCHist.vnet_2::bucket_size 1
system.ruby.delayVCHist.vnet_2::max_bucket 9
system.ruby.delayVCHist.vnet_2::samples 35256
system.ruby.delayVCHist.vnet_2 | 35256 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.delayVCHist.vnet_2::total 35256
system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 31333
system.ruby.LD.latency_hist_seqr::mean 27.317684
system.ruby.LD.latency_hist_seqr::gmean 7.086728
system.ruby.LD.latency_hist_seqr::stdev 34.908453
system.ruby.LD.latency_hist_seqr | 24762 79.02% 79.02% | 6164 19.67% 98.70% | 288 0.91% 99.62% | 45 0.14% 99.76% | 40 0.12% 99.89% | 30 0.09% 99.98% | 2 0.00% 99.99% | 1 0.00% 99.99% | 0 0.00% 99.99% | 1 0.00% 99.99%
system.ruby.LD.latency_hist_seqr::total 31333
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
system.ruby.LD.hit_latency_hist_seqr::samples 15338
system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 15338 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 15338
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 15995
system.ruby.LD.miss_latency_hist_seqr::mean 52.554360
system.ruby.LD.miss_latency_hist_seqr::gmean 46.340340
system.ruby.LD.miss_latency_hist_seqr::stdev 32.955680
system.ruby.LD.miss_latency_hist_seqr | 9424 58.91% 58.91% | 6164 38.53% 97.45% | 288 1.80% 99.25% | 45 0.28% 99.53% | 40 0.25% 99.78% | 30 0.18% 99.97% | 2 0.01% 99.98% | 1 0.00% 99.99% | 0 0.00% 99.99% | 1 0.00% 99.99%
system.ruby.LD.miss_latency_hist_seqr::total 15995
system.ruby.ST.latency_hist_seqr::bucket_size 64
system.ruby.ST.latency_hist_seqr::max_bucket 639
system.ruby.ST.latency_hist_seqr::samples 19847
system.ruby.ST.latency_hist_seqr::mean 14.612032
system.ruby.ST.latency_hist_seqr::gmean 3.146952
system.ruby.ST.latency_hist_seqr::stdev 27.153113
system.ruby.ST.latency_hist_seqr | 18401 92.71% 92.71% | 1320 6.65% 99.36% | 91 0.45% 99.82% | 15 0.07% 99.89% | 8 0.04% 99.93% | 5 0.02% 99.96% | 2 0.01% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.02% 99.99%
system.ruby.ST.latency_hist_seqr::total 19847
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
system.ruby.ST.hit_latency_hist_seqr::samples 13672
system.ruby.ST.hit_latency_hist_seqr::mean 1
system.ruby.ST.hit_latency_hist_seqr::gmean 1
system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 13672 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::total 13672
system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
system.ruby.ST.miss_latency_hist_seqr::samples 6175
system.ruby.ST.miss_latency_hist_seqr::mean 44.750283
system.ruby.ST.miss_latency_hist_seqr::gmean 39.834879
system.ruby.ST.miss_latency_hist_seqr::stdev 32.422439
system.ruby.ST.miss_latency_hist_seqr | 4729 76.58% 76.58% | 1320 21.37% 97.95% | 91 1.47% 99.43% | 15 0.24% 99.67% | 8 0.12% 99.80% | 5 0.08% 99.88% | 2 0.03% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 5 0.08% 99.99%
system.ruby.ST.miss_latency_hist_seqr::total 6175
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 152711
system.ruby.IFETCH.latency_hist_seqr::mean 6.083458
system.ruby.IFETCH.latency_hist_seqr::gmean 1.405754
system.ruby.IFETCH.latency_hist_seqr::stdev 19.904521
system.ruby.IFETCH.latency_hist_seqr | 145279 95.13% 95.13% | 7004 4.58% 99.71% | 266 0.17% 99.89% | 49 0.03% 99.92% | 66 0.04% 99.96% | 38 0.02% 99.99% | 5 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 4 0.00% 99.99%
system.ruby.IFETCH.latency_hist_seqr::total 152711
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
system.ruby.IFETCH.hit_latency_hist_seqr::samples 139625
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 139625 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 139625
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 13086
system.ruby.IFETCH.miss_latency_hist_seqr::mean 60.322940
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 53.219754
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 37.495192
system.ruby.IFETCH.miss_latency_hist_seqr | 5654 43.20% 43.20% | 7004 53.52% 96.72% | 266 2.03% 98.76% | 49 0.37% 99.13% | 66 0.50% 99.64% | 38 0.29% 99.93% | 5 0.03% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 4 0.03% 99.99%
system.ruby.IFETCH.miss_latency_hist_seqr::total 13086
system.ruby.Load_Linked.latency_hist_seqr::bucket_size 8
system.ruby.Load_Linked.latency_hist_seqr::max_bucket 79
system.ruby.Load_Linked.latency_hist_seqr::samples 334
system.ruby.Load_Linked.latency_hist_seqr::mean 1.685628
system.ruby.Load_Linked.latency_hist_seqr::gmean 1.049320
system.ruby.Load_Linked.latency_hist_seqr::stdev 6.454272
system.ruby.Load_Linked.latency_hist_seqr | 330 98.80% 98.80% | 0 0.00% 98.80% | 0 0.00% 98.80% | 0 0.00% 98.80% | 1 0.29% 99.10% | 0 0.00% 99.10% | 0 0.00% 99.10% | 0 0.00% 99.10% | 3 0.89% 99.99% | 0 0.00% 99.99%
system.ruby.Load_Linked.latency_hist_seqr::total 334
system.ruby.Load_Linked.hit_latency_hist_seqr::bucket_size 1
system.ruby.Load_Linked.hit_latency_hist_seqr::max_bucket 9
system.ruby.Load_Linked.hit_latency_hist_seqr::samples 330
system.ruby.Load_Linked.hit_latency_hist_seqr::mean 1
system.ruby.Load_Linked.hit_latency_hist_seqr::gmean 1
system.ruby.Load_Linked.hit_latency_hist_seqr | 0 0.00% 0.00% | 330 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Load_Linked.hit_latency_hist_seqr::total 330
system.ruby.Load_Linked.miss_latency_hist_seqr::bucket_size 8
system.ruby.Load_Linked.miss_latency_hist_seqr::max_bucket 79
system.ruby.Load_Linked.miss_latency_hist_seqr::samples 4
system.ruby.Load_Linked.miss_latency_hist_seqr::mean 58.250000
system.ruby.Load_Linked.miss_latency_hist_seqr::gmean 55.698512
system.ruby.Load_Linked.miss_latency_hist_seqr::stdev 17.500000
system.ruby.Load_Linked.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 3 75.00% 100.00% | 0 0.00% 100.00%
system.ruby.Load_Linked.miss_latency_hist_seqr::total 4
system.ruby.Store_Conditional.latency_hist_seqr::bucket_size 1
system.ruby.Store_Conditional.latency_hist_seqr::max_bucket 9
system.ruby.Store_Conditional.latency_hist_seqr::samples 334
system.ruby.Store_Conditional.latency_hist_seqr::mean 1
system.ruby.Store_Conditional.latency_hist_seqr::gmean 1
system.ruby.Store_Conditional.latency_hist_seqr | 0 0.00% 0.00% | 334 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Store_Conditional.latency_hist_seqr::total 334
system.ruby.Store_Conditional.hit_latency_hist_seqr::bucket_size 1
system.ruby.Store_Conditional.hit_latency_hist_seqr::max_bucket 9
system.ruby.Store_Conditional.hit_latency_hist_seqr::samples 334
system.ruby.Store_Conditional.hit_latency_hist_seqr::mean 1
system.ruby.Store_Conditional.hit_latency_hist_seqr::gmean 1
system.ruby.Store_Conditional.hit_latency_hist_seqr | 0 0.00% 0.00% | 334 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Store_Conditional.hit_latency_hist_seqr::total 334
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 35260
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 54.071440
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 47.508689
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.060895
system.ruby.Directory.miss_mach_latency_hist_seqr | 19808 56.17% 56.17% | 14491 41.09% 97.27% | 645 1.82% 99.10% | 109 0.30% 99.41% | 114 0.32% 99.73% | 73 0.20% 99.94% | 9 0.02% 99.96% | 1 0.00% 99.97% | 0 0.00% 99.97% | 10 0.02% 99.99%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 35260
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 74.999999
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 15995
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.554360
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.340340
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.955680
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 9424 58.91% 58.91% | 6164 38.53% 97.45% | 288 1.80% 99.25% | 45 0.28% 99.53% | 40 0.25% 99.78% | 30 0.18% 99.97% | 2 0.01% 99.98% | 1 0.00% 99.99% | 0 0.00% 99.99% | 1 0.00% 99.99%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 15995
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 6175
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 44.750283
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 39.834879
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 32.422439
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 4729 76.58% 76.58% | 1320 21.37% 97.95% | 91 1.47% 99.43% | 15 0.24% 99.67% | 8 0.12% 99.80% | 5 0.08% 99.88% | 2 0.03% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 5 0.08% 99.99%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 6175
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 13086
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 60.322940
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 53.219754
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 37.495192
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 5654 43.20% 43.20% | 7004 53.52% 96.72% | 266 2.03% 98.76% | 49 0.37% 99.13% | 66 0.50% 99.64% | 38 0.29% 99.93% | 5 0.03% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 4 0.03% 99.99%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 13086
system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::bucket_size 8
system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::max_bucket 79
system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::samples 4
system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::mean 58.250000
system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::gmean 55.698512
system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::stdev 17.500000
system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 3 75.00% 100.00% | 0 0.00% 100.00%
system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::total 4
system.ruby.Directory_Controller.GETX 35260 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 35256 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 35260 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 35256 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 35260 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 35256 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 35260 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 35256 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 31333 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 152711 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 20515 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 35260 0.00% 0.00%
system.ruby.L1Cache_Controller.Replacement 35256 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 35256 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 15995 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 13086 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 6179 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 15338 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 139625 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 14336 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Replacement 35256 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 35256 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 29081 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 6179 0.00% 0.00%
---------- End Simulation Statistics ----------

383
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/config.ini Normal file
View File

@@ -0,0 +1,383 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=Process
cmd=insttest
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

511
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/config.json Normal file
View File

@@ -0,0 +1,511 @@
{
"name": null,
"sim_quantum": 0,
"system": {
"kernel": "",
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"point_of_coherency": true,
"system": "system",
"response_latency": 2,
"cxx_class": "CoherentXBar",
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"width": 16,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 3,
"slave": {
"peer": [
"system.system_port",
"system.cpu.l2cache.mem_side"
],
"role": "SLAVE"
},
"p_state_clk_gate_min": 1000,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
"max_capacity": 8388608,
"eventq_index": 0,
"cxx_class": "SnoopFilter",
"path": "system.membus.snoop_filter",
"type": "SnoopFilter",
"lookup_latency": 1
},
"power_model": null,
"path": "system.membus",
"snoop_response_latency": 4,
"name": "membus",
"p_state_clk_gate_bins": 20,
"use_default_range": false
},
"symbolfile": "",
"readfile": "",
"thermal_model": null,
"cxx_class": "System",
"work_begin_cpu_id_exit": -1,
"load_offset": 0,
"work_begin_exit_count": 0,
"p_state_clk_gate_min": 1000,
"memories": [
"system.physmem"
],
"work_begin_ckpt_count": 0,
"clk_domain": {
"name": "clk_domain",
"clock": [
1000
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"mem_ranges": [],
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"dvfs_handler": {
"enable": false,
"name": "dvfs_handler",
"sys_clk_domain": "system.clk_domain",
"transition_latency": 100000000,
"eventq_index": 0,
"cxx_class": "DVFSHandler",
"domains": [],
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "System",
"voltage_domain": {
"name": "voltage_domain",
"eventq_index": 0,
"voltage": [
"1.0"
],
"cxx_class": "VoltageDomain",
"path": "system.voltage_domain",
"type": "VoltageDomain"
},
"cache_line_size": 64,
"boot_osflags": "a",
"system_port": {
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"physmem": {
"range": "0:134217727:0:0:0:0",
"latency": 30000,
"name": "physmem",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"kvm_map": true,
"clk_domain": "system.clk_domain",
"power_model": null,
"latency_var": 0,
"bandwidth": "73.000000",
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"p_state_clk_gate_max": 1000000000000,
"path": "system.physmem",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[0]",
"role": "SLAVE"
},
"in_addr_map": true
},
"power_model": null,
"work_cpus_ckpt_count": 0,
"thermal_components": [],
"path": "system",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
"clock": [
500
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.cpu_clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"work_end_ckpt_count": 0,
"mem_mode": "timing",
"name": "system",
"init_param": 0,
"p_state_clk_gate_bins": 20,
"load_addr_mask": 1099511627775,
"cpu": [
{
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
"name": "itb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.itb",
"type": "RiscvTLB",
"size": 64
},
"system": "system",
"icache": {
"cpu_side": {
"peer": "system.cpu.icache_port",
"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"system": "system",
"write_buffers": 8,
"response_latency": 2,
"cxx_class": "Cache",
"size": 131072,
"type": "Cache",
"clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": {
"peer": "system.cpu.toL2Bus.slave[0]",
"role": "MASTER"
},
"mshrs": 4,
"writeback_clean": true,
"p_state_clk_gate_min": 1000,
"tags": {
"size": 131072,
"tag_latency": 2,
"name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false,
"assoc": 2,
"cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.icache.tags",
"block_size": 64,
"type": "LRU",
"data_latency": 2
},
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"is_read_only": true,
"prefetch_on_access": false,
"path": "system.cpu.icache",
"data_latency": 2,
"tag_latency": 2,
"name": "icache",
"p_state_clk_gate_bins": 20,
"sequential_access": false,
"assoc": 2
},
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "TimingSimpleCPU",
"max_loads_all_threads": 0,
"clk_domain": "system.cpu_clk_domain",
"function_trace_start": 0,
"cpu_id": 0,
"checker": null,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"toL2Bus": {
"point_of_coherency": false,
"system": "system",
"response_latency": 1,
"cxx_class": "CoherentXBar",
"forward_latency": 0,
"clk_domain": "system.cpu_clk_domain",
"width": 32,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.cpu.l2cache.cpu_side"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 1,
"slave": {
"peer": [
"system.cpu.icache.mem_side",
"system.cpu.dcache.mem_side"
],
"role": "SLAVE"
},
"p_state_clk_gate_min": 1000,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
"max_capacity": 8388608,
"eventq_index": 0,
"cxx_class": "SnoopFilter",
"path": "system.cpu.toL2Bus.snoop_filter",
"type": "SnoopFilter",
"lookup_latency": 0
},
"power_model": null,
"path": "system.cpu.toL2Bus",
"snoop_response_latency": 1,
"name": "toL2Bus",
"p_state_clk_gate_bins": 20,
"use_default_range": false
},
"do_quiesce": true,
"type": "TimingSimpleCPU",
"profile": 0,
"icache_port": {
"peer": "system.cpu.icache.cpu_side",
"role": "MASTER"
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
"syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
"path": "system.cpu.interrupts",
"type": "RiscvInterrupts",
"name": "interrupts",
"cxx_class": "RiscvISA::Interrupts"
}
],
"dcache_port": {
"peer": "system.cpu.dcache.cpu_side",
"role": "MASTER"
},
"socket_id": 0,
"power_model": null,
"max_insts_all_threads": 0,
"l2cache": {
"cpu_side": {
"peer": "system.cpu.toL2Bus.master[0]",
"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"system": "system",
"write_buffers": 8,
"response_latency": 20,
"cxx_class": "Cache",
"size": 2097152,
"type": "Cache",
"clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": {
"peer": "system.membus.slave[1]",
"role": "MASTER"
},
"mshrs": 20,
"writeback_clean": false,
"p_state_clk_gate_min": 1000,
"tags": {
"size": 2097152,
"tag_latency": 20,
"name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false,
"assoc": 8,
"cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.l2cache.tags",
"block_size": 64,
"type": "LRU",
"data_latency": 20
},
"tgts_per_mshr": 12,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"is_read_only": false,
"prefetch_on_access": false,
"path": "system.cpu.l2cache",
"data_latency": 20,
"tag_latency": 20,
"name": "l2cache",
"p_state_clk_gate_bins": 20,
"sequential_access": false,
"assoc": 8
},
"path": "system.cpu",
"max_loads_any_thread": 0,
"switched_out": false,
"workload": [
{
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "Process",
"executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"maxStackSize": 67108864,
"ppid": 0,
"type": "Process",
"cwd": "",
"pgid": 100,
"simpoint": 0,
"euid": 100,
"input": "cin",
"path": "system.cpu.workload",
"name": "workload",
"cmd": [
"insttest"
],
"errout": "cerr",
"useArchPT": false,
"egid": 100,
"output": "cout"
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.dtb",
"type": "RiscvTLB",
"size": 64
},
"simpoint_start_insts": [],
"max_insts_any_thread": 0,
"progress_interval": 0,
"branchPred": null,
"dcache": {
"cpu_side": {
"peer": "system.cpu.dcache_port",
"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"system": "system",
"write_buffers": 8,
"response_latency": 2,
"cxx_class": "Cache",
"size": 262144,
"type": "Cache",
"clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": {
"peer": "system.cpu.toL2Bus.slave[1]",
"role": "MASTER"
},
"mshrs": 4,
"writeback_clean": false,
"p_state_clk_gate_min": 1000,
"tags": {
"size": 262144,
"tag_latency": 2,
"name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false,
"assoc": 2,
"cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.dcache.tags",
"block_size": 64,
"type": "LRU",
"data_latency": 2
},
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"is_read_only": false,
"prefetch_on_access": false,
"path": "system.cpu.dcache",
"data_latency": 2,
"tag_latency": 2,
"name": "dcache",
"p_state_clk_gate_bins": 20,
"sequential_access": false,
"assoc": 2
},
"isa": [
{
"eventq_index": 0,
"path": "system.cpu.isa",
"type": "RiscvISA",
"name": "isa",
"cxx_class": "RiscvISA::ISA"
}
],
"tracer": {
"eventq_index": 0,
"path": "system.cpu.tracer",
"type": "ExeTracer",
"name": "tracer",
"cxx_class": "Trace::ExeTracer"
}
}
],
"multi_thread": false,
"exit_on_work_items": false,
"work_item_id": -1,
"num_work_ids": 16
},
"time_sync_period": 100000000000,
"eventq_index": 0,
"time_sync_spin_threshold": 100000000,
"cxx_class": "Root",
"path": "root",
"time_sync_enable": false,
"type": "Root",
"full_system": false
}

5
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/simerr Executable file
View File

@@ -0,0 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64c/insttest'
info: Increasing stack size by one page.

66
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/simout Executable file
View File

@@ -0,0 +1,66 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:25:07
gem5 executing on boldrock, pid 6010
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64c/simple-timing
Global frequency set at 1000000000000 ticks per second
c.lwsp: PASS
c.ldsp: PASS
c.fldsp: PASS
c.swsp: PASS
c.sdsp: PASS
c.fsdsp: PASS
c.lw, positive: PASS
c.lw, negative: PASS
c.ld: PASS
c.fld: PASS
c.sw: PASS
c.sd: PASS
c.fsd: PASS
c.j: PASS
c.jr: PASS
c.jalr: PASS
c.beqz, zero: PASS
c.beqz, not zero: PASS
c.bnez, not zero: PASS
c.bnez, zero: PASS
c.li: PASS
c.li, sign extend: PASS
c.lui: PASS
c.addi: PASS
c.addiw: PASS
c.addiw, overflow: PASS
c.addiw, truncate: PASS
c.addi16sp: PASS
c.addi4spn: PASS
c.slli: PASS
c.slli, overflow: PASS
c.srli: PASS
c.srli, overflow: PASS
c.srli, -1: PASS
c.srai: PASS
c.srai, overflow: PASS
c.srai, -1: PASS
c.andi (0): PASS
c.andi (1): PASS
c.mv: PASS
c.add: PASS
c.and (0): PASS
c.and (-1): PASS
c.or (1): PASS
c.or (A): PASS
c.xor (1): PASS
c.xor (0): PASS
c.sub: PASS
c.addw: PASS
c.addw, overflow: PASS
c.addw, truncate: PASS
c.subw: PASS
c.subw, "overflow": PASS
c.subw, truncate: PASS
Exiting @ tick 277930500 because exiting with last active thread context

549
tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-timing/stats.txt Normal file
View File

@@ -0,0 +1,549 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000277
sim_ticks 277930500
final_tick 277930500
sim_freq 1000000000000
host_inst_rate 4092
host_op_rate 4101
host_tick_rate 8659912
host_mem_usage 269952
host_seconds 32.09
sim_insts 131348
sim_ops 131648
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
system.physmem.pwrStateResidencyTicks::UNDEFINED 277930500
system.physmem.bytes_read::cpu.inst 46336
system.physmem.bytes_read::cpu.data 29376
system.physmem.bytes_read::total 75712
system.physmem.bytes_inst_read::cpu.inst 46336
system.physmem.bytes_inst_read::total 46336
system.physmem.num_reads::cpu.inst 724
system.physmem.num_reads::cpu.data 459
system.physmem.num_reads::total 1183
system.physmem.bw_read::cpu.inst 166717938
system.physmem.bw_read::cpu.data 105695488
system.physmem.bw_read::total 272413427
system.physmem.bw_inst_read::cpu.inst 166717938
system.physmem.bw_inst_read::total 166717938
system.physmem.bw_total::cpu.inst 166717938
system.physmem.bw_total::cpu.data 105695488
system.physmem.bw_total::total 272413427
system.pwrStateResidencyTicks::UNDEFINED 277930500
system.cpu_clk_domain.clock 500
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
system.cpu.dtb.read_accesses 0
system.cpu.dtb.write_hits 0
system.cpu.dtb.write_misses 0
system.cpu.dtb.write_accesses 0
system.cpu.dtb.hits 0
system.cpu.dtb.misses 0
system.cpu.dtb.accesses 0
system.cpu.itb.read_hits 0
system.cpu.itb.read_misses 0
system.cpu.itb.read_accesses 0
system.cpu.itb.write_hits 0
system.cpu.itb.write_misses 0
system.cpu.itb.write_accesses 0
system.cpu.itb.hits 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 62
system.cpu.pwrStateResidencyTicks::ON 277930500
system.cpu.numCycles 555861
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
system.cpu.committedInsts 131348
system.cpu.committedOps 131648
system.cpu.num_int_alu_accesses 130924
system.cpu.num_fp_alu_accesses 40
system.cpu.num_vec_alu_accesses 0
system.cpu.num_func_calls 7702
system.cpu.num_conditional_control_insts 21044
system.cpu.num_int_insts 130924
system.cpu.num_fp_insts 40
system.cpu.num_vec_insts 0
system.cpu.num_int_register_reads 163963
system.cpu.num_int_register_writes 87008
system.cpu.num_fp_register_reads 31
system.cpu.num_fp_register_writes 16
system.cpu.num_vec_register_reads 0
system.cpu.num_vec_register_writes 0
system.cpu.num_mem_refs 51848
system.cpu.num_load_insts 31667
system.cpu.num_store_insts 20181
system.cpu.num_idle_cycles -0
system.cpu.num_busy_cycles 555861
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction -0
system.cpu.Branches 28746
system.cpu.op_class::No_OpClass 66 0.05% 0.05%
system.cpu.op_class::IntAlu 79621 60.45% 60.50%
system.cpu.op_class::IntMult 164 0.12% 60.62%
system.cpu.op_class::IntDiv 4 0.00% 60.62%
system.cpu.op_class::FloatAdd 2 0.00% 60.63%
system.cpu.op_class::FloatCmp 3 0.00% 60.63%
system.cpu.op_class::FloatCvt 2 0.00% 60.63%
system.cpu.op_class::FloatMult 0 0.00% 60.63%
system.cpu.op_class::FloatMultAcc 0 0.00% 60.63%
system.cpu.op_class::FloatDiv 0 0.00% 60.63%
system.cpu.op_class::FloatMisc 0 0.00% 60.63%
system.cpu.op_class::FloatSqrt 0 0.00% 60.63%
system.cpu.op_class::SimdAdd 0 0.00% 60.63%
system.cpu.op_class::SimdAddAcc 0 0.00% 60.63%
system.cpu.op_class::SimdAlu 0 0.00% 60.63%
system.cpu.op_class::SimdCmp 0 0.00% 60.63%
system.cpu.op_class::SimdCvt 0 0.00% 60.63%
system.cpu.op_class::SimdMisc 0 0.00% 60.63%
system.cpu.op_class::SimdMult 0 0.00% 60.63%
system.cpu.op_class::SimdMultAcc 0 0.00% 60.63%
system.cpu.op_class::SimdShift 0 0.00% 60.63%
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.63%
system.cpu.op_class::SimdSqrt 0 0.00% 60.63%
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.63%
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.63%
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.63%
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.63%
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.63%
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.63%
system.cpu.op_class::SimdFloatMult 0 0.00% 60.63%
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.63%
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.63%
system.cpu.op_class::MemRead 31653 24.03% 84.66%
system.cpu.op_class::MemWrite 20162 15.30% 99.97%
system.cpu.op_class::FloatMemRead 14 0.01% 99.98%
system.cpu.op_class::FloatMemWrite 19 0.01% 99.99%
system.cpu.op_class::IprAccess 0 0.00% 99.99%
system.cpu.op_class::InstPrefetch 0 0.00% 99.99%
system.cpu.op_class::total 131710
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 277930500
system.cpu.dcache.tags.replacements 0
system.cpu.dcache.tags.tagsinuse 345.626018
system.cpu.dcache.tags.total_refs 51389
system.cpu.dcache.tags.sampled_refs 459
system.cpu.dcache.tags.avg_refs 111.958605
system.cpu.dcache.tags.warmup_cycle 0
system.cpu.dcache.tags.occ_blocks::cpu.data 345.626018
system.cpu.dcache.tags.occ_percent::cpu.data 0.084381
system.cpu.dcache.tags.occ_percent::total 0.084381
system.cpu.dcache.tags.occ_task_id_blocks::1024 459
system.cpu.dcache.tags.age_task_id_blocks_1024::0 14
system.cpu.dcache.tags.age_task_id_blocks_1024::1 9
system.cpu.dcache.tags.age_task_id_blocks_1024::2 436
system.cpu.dcache.tags.occ_task_id_percent::1024 0.112060
system.cpu.dcache.tags.tag_accesses 104155
system.cpu.dcache.tags.data_accesses 104155
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 277930500
system.cpu.dcache.ReadReq_hits::cpu.data 31097
system.cpu.dcache.ReadReq_hits::total 31097
system.cpu.dcache.WriteReq_hits::cpu.data 19625
system.cpu.dcache.WriteReq_hits::total 19625
system.cpu.dcache.LoadLockedReq_hits::cpu.data 333
system.cpu.dcache.LoadLockedReq_hits::total 333
system.cpu.dcache.StoreCondReq_hits::cpu.data 334
system.cpu.dcache.StoreCondReq_hits::total 334
system.cpu.dcache.demand_hits::cpu.data 50722
system.cpu.dcache.demand_hits::total 50722
system.cpu.dcache.overall_hits::cpu.data 50722
system.cpu.dcache.overall_hits::total 50722
system.cpu.dcache.ReadReq_misses::cpu.data 236
system.cpu.dcache.ReadReq_misses::total 236
system.cpu.dcache.WriteReq_misses::cpu.data 222
system.cpu.dcache.WriteReq_misses::total 222
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1
system.cpu.dcache.LoadLockedReq_misses::total 1
system.cpu.dcache.demand_misses::cpu.data 458
system.cpu.dcache.demand_misses::total 458
system.cpu.dcache.overall_misses::cpu.data 458
system.cpu.dcache.overall_misses::total 458
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14868000
system.cpu.dcache.ReadReq_miss_latency::total 14868000
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13986000
system.cpu.dcache.WriteReq_miss_latency::total 13986000
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 63000
system.cpu.dcache.LoadLockedReq_miss_latency::total 63000
system.cpu.dcache.demand_miss_latency::cpu.data 28854000
system.cpu.dcache.demand_miss_latency::total 28854000
system.cpu.dcache.overall_miss_latency::cpu.data 28854000
system.cpu.dcache.overall_miss_latency::total 28854000
system.cpu.dcache.ReadReq_accesses::cpu.data 31333
system.cpu.dcache.ReadReq_accesses::total 31333
system.cpu.dcache.WriteReq_accesses::cpu.data 19847
system.cpu.dcache.WriteReq_accesses::total 19847
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 334
system.cpu.dcache.LoadLockedReq_accesses::total 334
system.cpu.dcache.StoreCondReq_accesses::cpu.data 334
system.cpu.dcache.StoreCondReq_accesses::total 334
system.cpu.dcache.demand_accesses::cpu.data 51180
system.cpu.dcache.demand_accesses::total 51180
system.cpu.dcache.overall_accesses::cpu.data 51180
system.cpu.dcache.overall_accesses::total 51180
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007531
system.cpu.dcache.ReadReq_miss_rate::total 0.007531
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011185
system.cpu.dcache.WriteReq_miss_rate::total 0.011185
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002994
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002994
system.cpu.dcache.demand_miss_rate::cpu.data 0.008948
system.cpu.dcache.demand_miss_rate::total 0.008948
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system.cpu.dcache.overall_miss_rate::total 0.008948
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000
system.cpu.dcache.ReadReq_avg_miss_latency::total 63000
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000
system.cpu.dcache.WriteReq_avg_miss_latency::total 63000
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000
system.cpu.dcache.demand_avg_miss_latency::total 63000
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system.cpu.dcache.overall_avg_miss_latency::total 63000
system.cpu.dcache.blocked_cycles::no_mshrs 0
system.cpu.dcache.blocked_cycles::no_targets 0
system.cpu.dcache.blocked::no_mshrs 0
system.cpu.dcache.blocked::no_targets 0
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 236
system.cpu.dcache.ReadReq_mshr_misses::total 236
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222
system.cpu.dcache.WriteReq_mshr_misses::total 222
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1
system.cpu.dcache.demand_mshr_misses::cpu.data 458
system.cpu.dcache.demand_mshr_misses::total 458
system.cpu.dcache.overall_mshr_misses::cpu.data 458
system.cpu.dcache.overall_mshr_misses::total 458
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14632000
system.cpu.dcache.ReadReq_mshr_miss_latency::total 14632000
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13764000
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13764000
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 62000
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 62000
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28396000
system.cpu.dcache.demand_mshr_miss_latency::total 28396000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28396000
system.cpu.dcache.overall_mshr_miss_latency::total 28396000
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007531
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007531
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002994
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system.cpu.dcache.overall_mshr_miss_rate::total 0.008948
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 62000
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 62000
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000
system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000
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system.cpu.icache.blocked::no_mshrs 0
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system.cpu.icache.avg_blocked_cycles::no_targets nan
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system.cpu.l2cache.tags.sampled_refs 1183
system.cpu.l2cache.tags.avg_refs 0.034657
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 461.806279
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.010548
system.cpu.l2cache.tags.occ_percent::total 0.024641
system.cpu.l2cache.tags.occ_task_id_blocks::1024 1183
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1045
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.036102
system.cpu.l2cache.tags.tag_accesses 10975
system.cpu.l2cache.tags.data_accesses 10975
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 277930500
system.cpu.l2cache.WritebackClean_hits::writebacks 39
system.cpu.l2cache.WritebackClean_hits::total 39
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2
system.cpu.l2cache.ReadCleanReq_hits::total 2
system.cpu.l2cache.demand_hits::cpu.inst 2
system.cpu.l2cache.demand_hits::total 2
system.cpu.l2cache.overall_hits::cpu.inst 2
system.cpu.l2cache.overall_hits::total 2
system.cpu.l2cache.ReadExReq_misses::cpu.data 222
system.cpu.l2cache.ReadExReq_misses::total 222
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 724
system.cpu.l2cache.ReadCleanReq_misses::total 724
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 237
system.cpu.l2cache.ReadSharedReq_misses::total 237
system.cpu.l2cache.demand_misses::cpu.inst 724
system.cpu.l2cache.demand_misses::cpu.data 459
system.cpu.l2cache.demand_misses::total 1183
system.cpu.l2cache.overall_misses::cpu.inst 724
system.cpu.l2cache.overall_misses::cpu.data 459
system.cpu.l2cache.overall_misses::total 1183
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13431000
system.cpu.l2cache.ReadExReq_miss_latency::total 13431000
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 43803000
system.cpu.l2cache.ReadCleanReq_miss_latency::total 43803000
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14338500
system.cpu.l2cache.ReadSharedReq_miss_latency::total 14338500
system.cpu.l2cache.demand_miss_latency::cpu.inst 43803000
system.cpu.l2cache.demand_miss_latency::cpu.data 27769500
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system.cpu.l2cache.overall_miss_latency::cpu.data 27769500
system.cpu.l2cache.overall_miss_latency::total 71572500
system.cpu.l2cache.WritebackClean_accesses::writebacks 39
system.cpu.l2cache.WritebackClean_accesses::total 39
system.cpu.l2cache.ReadExReq_accesses::cpu.data 222
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system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726
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system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 237
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system.cpu.l2cache.overall_accesses::cpu.inst 726
system.cpu.l2cache.overall_accesses::cpu.data 459
system.cpu.l2cache.overall_accesses::total 1185
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1
system.cpu.l2cache.ReadExReq_miss_rate::total 1
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997245
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system.cpu.l2cache.overall_miss_rate::cpu.data 1
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.381215
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.381215
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500
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system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.381215
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500
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system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500
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system.cpu.l2cache.blocked_cycles::no_mshrs 0
system.cpu.l2cache.blocked_cycles::no_targets 0
system.cpu.l2cache.blocked::no_mshrs 0
system.cpu.l2cache.blocked::no_targets 0
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 222
system.cpu.l2cache.ReadExReq_mshr_misses::total 222
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 724
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 724
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 237
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system.cpu.l2cache.demand_mshr_misses::cpu.inst 724
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system.cpu.l2cache.overall_mshr_misses::cpu.inst 724
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system.cpu.l2cache.overall_mshr_misses::total 1183
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11211000
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system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 36563000
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system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1
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system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997245
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997245
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998312
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500
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system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.381215
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system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.381215
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500
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system.cpu.toL2Bus.snoop_filter.tot_requests 1224
system.cpu.toL2Bus.snoop_filter.hit_single_requests 39
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
system.cpu.toL2Bus.snoop_filter.tot_snoops 0
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 277930500
system.cpu.toL2Bus.trans_dist::ReadResp 963
system.cpu.toL2Bus.trans_dist::WritebackClean 39
system.cpu.toL2Bus.trans_dist::ReadExReq 222
system.cpu.toL2Bus.trans_dist::ReadExResp 222
system.cpu.toL2Bus.trans_dist::ReadCleanReq 726
system.cpu.toL2Bus.trans_dist::ReadSharedReq 237
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1491
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 918
system.cpu.toL2Bus.pkt_count::total 2409
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 48960
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29376
system.cpu.toL2Bus.pkt_size::total 78336
system.cpu.toL2Bus.snoops 0
system.cpu.toL2Bus.snoopTraffic 0
system.cpu.toL2Bus.snoop_fanout::samples 1185
system.cpu.toL2Bus.snoop_fanout::mean 0
system.cpu.toL2Bus.snoop_fanout::stdev -0
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
system.cpu.toL2Bus.snoop_fanout::0 1185 100.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::min_value 0
system.cpu.toL2Bus.snoop_fanout::max_value 0
system.cpu.toL2Bus.snoop_fanout::total 1185
system.cpu.toL2Bus.reqLayer0.occupancy 651000
system.cpu.toL2Bus.reqLayer0.utilization 0.2
system.cpu.toL2Bus.respLayer0.occupancy 1089000
system.cpu.toL2Bus.respLayer0.utilization 0.3
system.cpu.toL2Bus.respLayer1.occupancy 688500
system.cpu.toL2Bus.respLayer1.utilization 0.2
system.membus.snoop_filter.tot_requests 1183
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
system.membus.pwrStateResidencyTicks::UNDEFINED 277930500
system.membus.trans_dist::ReadResp 961
system.membus.trans_dist::ReadExReq 222
system.membus.trans_dist::ReadExResp 222
system.membus.trans_dist::ReadSharedReq 961
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2366
system.membus.pkt_count::total 2366
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 75712
system.membus.pkt_size::total 75712
system.membus.snoops 0
system.membus.snoopTraffic 0
system.membus.snoop_fanout::samples 1183
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev -0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
system.membus.snoop_fanout::0 1183 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
system.membus.snoop_fanout::total 1183
system.membus.reqLayer0.occupancy 1184000
system.membus.reqLayer0.utilization 0.4
system.membus.respLayer1.occupancy 5915000
system.membus.respLayer1.utilization 2.1
---------- End Simulation Statistics ----------

11
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini
View File

@@ -116,9 +116,11 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
@@ -745,7 +747,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=insttest
cwd=
drivers=
@@ -754,14 +756,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest
executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100

15
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json
View File

@@ -297,6 +297,7 @@
"max_loads_all_threads": 0,
"executeMemoryIssueLimit": 1,
"decodeCycleInput": true,
"syscallRetryLatency": 10000,
"max_loads_any_thread": 0,
"executeLSQTransfersQueueSize": 2,
"p_state_clk_gate_max": 1000000000000,
@@ -1058,21 +1059,22 @@
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "LiveProcess",
"executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest",
"cxx_class": "Process",
"executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"input": "cin",
"ppid": 99,
"type": "LiveProcess",
"maxStackSize": 67108864,
"ppid": 0,
"type": "Process",
"cwd": "",
"pgid": 100,
"simpoint": 0,
"euid": 100,
"input": "cin",
"path": "system.cpu.workload",
"max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
@@ -1084,6 +1086,7 @@
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,

6
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr
View File

@@ -1,4 +1,6 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest'
info: Increasing stack size by one page.

70
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout
View File

@@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:31
gem5 executing on zizzer, pid 34070
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/minor-timing
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:09:50
gem5 executing on boldrock, pid 1350
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
fld: PASS
fsd: PASS
fmadd.d: PASS
@@ -165,4 +163,62 @@ fcvt.w.d, truncate negative: PASS
fcvt.w.d, 0.0: PASS
fcvt.w.d, -0.0: PASS
fcvt.w.d, overflow: FAIL (expected 2147483647; found -2147483648)
Exiting @ tick 339160000 because target called exit()
fcvt.w.d, underflow: PASS
fcvt.w.d, infinity: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, -infinity: PASS
fcvt.w.d, quiet NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, quiet -NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, signaling NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.wu.d, truncate positive: PASS
fcvt.wu.d, truncate negative: PASS
fcvt.wu.d, 0.0: PASS
fcvt.wu.d, -0.0: PASS
fcvt.wu.d, overflow: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, underflow: PASS
fcvt.wu.d, infinity: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, -infinity: PASS
fcvt.wu.d, quiet NaN: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, quiet -NaN: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, signaling NaN: PASS
fcvt.d.w, 0: PASS
fcvt.d.w, negative: PASS
fcvt.d.w, truncate: PASS
fcvt.d.wu, 0: PASS
fcvt.d.wu: PASS
fcvt.d.wu, truncate: PASS
fcvt.l.d, truncate positive: PASS
fcvt.l.d, truncate negative: PASS
fcvt.l.d, 0.0: PASS
fcvt.l.d, -0.0: PASS
fcvt.l.d, 32-bit overflow: PASS
fcvt.l.d, overflow: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, underflow: PASS
fcvt.l.d, infinity: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, -infinity: PASS
fcvt.l.d, quiet NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, quiet -NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, signaling NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.lu.d, truncate positive: PASS
fcvt.lu.d, truncate negative: PASS
fcvt.lu.d, 0.0: PASS
fcvt.lu.d, -0.0: PASS
fcvt.lu.d, 32-bit overflow: PASS
fcvt.lu.d, overflow: FAIL (expected 18446744073709551615; found 0)
fcvt.lu.d, underflow: PASS
fcvt.lu.d, infinity: FAIL (expected 18446744073709551615; found 0)
fcvt.lu.d, -infinity: PASS
fcvt.lu.d, quiet NaN: FAIL (expected 18446744073709551615; found 9223372036854775808)
fcvt.lu.d, quiet -NaN: FAIL (expected 18446744073709551615; found 9223372036854775808)
fcvt.lu.d, signaling NaN: PASS
fmv.x.d, positive: PASS
fmv.x.d, negative: PASS
fmv.x.d, 0.0: PASS
fmv.x.d, -0.0: PASS
fcvt.d.l, 0: PASS
fcvt.d.l, negative: PASS
fcvt.d.l, 32-bit truncate: PASS
fcvt.d.lu, 0: PASS
fcvt.d.lu: PASS
fcvt.d.lu, 32-bit truncate: PASS
fmv.d.x: PASS
Exiting @ tick 432134500 because exiting with last active thread context

1551
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

876
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/config.ini Normal file
View File

@@ -0,0 +1,876 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
default_p_state=UNDEFINED
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numPhysVecRegs=256
numROBEntries=192
numRobs=1
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
wait_for_remote_gdb=false
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
opClass=IntDiv
opLat=20
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.fuPool.FUList3.opList3]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList4.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList3]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=Process
cmd=insttest
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

1155
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/config.json Normal file
View File

File diff suppressed because it is too large Load Diff

6
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simerr Executable file
View File

@@ -0,0 +1,6 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest'
info: Increasing stack size by one page.

224
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simout Executable file
View File

@@ -0,0 +1,224 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/o3-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:25:07
gem5 executing on boldrock, pid 6006
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/o3-timing
Global frequency set at 1000000000000 ticks per second
fld: PASS
fsd: PASS
fmadd.d: PASS
fmadd.d, quiet NaN: PASS
fmadd.d, signaling NaN: PASS
fmadd.d, infinity: PASS
fmadd.d, -infinity: PASS
fmsub.d: PASS
fmsub.d, quiet NaN: PASS
fmsub.d, signaling NaN: PASS
fmsub.d, infinity: PASS
fmsub.d, -infinity: PASS
fmsub.d, subtract infinity: PASS
fnmsub.d: PASS
fnmsub.d, quiet NaN: PASS
fnmsub.d, signaling NaN: PASS
fnmsub.d, infinity: PASS
fnmsub.d, -infinity: PASS
fnmsub.d, subtract infinity: PASS
fnmadd.d: PASS
fnmadd.d, quiet NaN: PASS
fnmadd.d, signaling NaN: PASS
fnmadd.d, infinity: PASS
fnmadd.d, -infinity: PASS
fadd.d: PASS
fadd.d, quiet NaN: PASS
fadd.d, signaling NaN: PASS
fadd.d, infinity: PASS
fadd.d, -infinity: PASS
fsub.d: PASS
fsub.d, quiet NaN: PASS
fsub.d, signaling NaN: PASS
fsub.d, infinity: PASS
fsub.d, -infinity: PASS
fsub.d, subtract infinity: PASS
fmul.d: PASS
fmul.d, quiet NaN: PASS
fmul.d, signaling NaN: PASS
fmul.d, infinity: PASS
fmul.d, -infinity: PASS
fmul.d, 0*infinity: PASS
fmul.d, overflow: PASS
fmul.d, underflow: PASS
fdiv.d: PASS
fdiv.d, quiet NaN: PASS
fdiv.d, signaling NaN: PASS
fdiv.d/0: PASS
fdiv.d/infinity: PASS
fdiv.d, infinity/infinity: PASS
fdiv.d, 0/0: PASS
fdiv.d, infinity/0: PASS
fdiv.d, 0/infinity: PASS
fdiv.d, underflow: PASS
fdiv.d, overflow: PASS
fsqrt.d: PASS
fsqrt.d, NaN: PASS
fsqrt.d, quiet NaN: PASS
fsqrt.d, signaling NaN: PASS
fsqrt.d, infinity: PASS
fsgnj.d, ++: PASS
fsgnj.d, +-: PASS
fsgnj.d, -+: PASS
fsgnj.d, --: PASS
fsgnj.d, quiet NaN: PASS
fsgnj.d, signaling NaN: PASS
fsgnj.d, inject NaN: PASS
fsgnj.d, inject -NaN: PASS
fsgnjn.d, ++: PASS
fsgnjn.d, +-: PASS
fsgnjn.d, -+: PASS
fsgnjn.d, --: PASS
fsgnjn.d, quiet NaN: PASS
fsgnjn.d, signaling NaN: PASS
fsgnjn.d, inject NaN: PASS
fsgnjn.d, inject NaN: PASS
fsgnjx.d, ++: PASS
fsgnjx.d, +-: PASS
fsgnjx.d, -+: PASS
fsgnjx.d, --: PASS
fsgnjx.d, quiet NaN: PASS
fsgnjx.d, signaling NaN: PASS
fsgnjx.d, inject NaN: PASS
fsgnjx.d, inject NaN: PASS
fmin.d: PASS
fmin.d, -infinity: PASS
fmin.d, infinity: PASS
fmin.d, quiet NaN first: PASS
fmin.d, quiet NaN second: PASS
fmin.d, quiet NaN both: PASS
fmin.d, signaling NaN first: PASS
fmin.d, signaling NaN second: PASS
fmin.d, signaling NaN both: PASS
fmax.d: PASS
fmax.d, -infinity: PASS
fmax.d, infinity: PASS
fmax.d, quiet NaN first: PASS
fmax.d, quiet NaN second: PASS
fmax.d, quiet NaN both: PASS
fmax.d, signaling NaN first: PASS
fmax.d, signaling NaN second: PASS
fmax.d, signaling NaN both: PASS
fcvt.s.d: PASS
fcvt.s.d, quiet NaN: PASS
fcvt.s.d, signaling NaN: PASS
fcvt.s.d, infinity: PASS
fcvt.s.d, overflow: PASS
fcvt.s.d, underflow: PASS
fcvt.d.s: PASS
fcvt.d.s, quiet NaN: PASS
fcvt.d.s, signaling NaN: PASS
fcvt.d.s, infinity: PASS
feq.d, equal: PASS
feq.d, not equal: PASS
feq.d, 0 == -0: PASS
feq.d, quiet NaN first: PASS
feq.d, quiet NaN second: PASS
feq.d, quiet NaN both: PASS
feq.d, signaling NaN first: PASS
feq.d, signaling NaN second: PASS
feq.d, signaling NaN both: PASS
flt.d, equal: PASS
flt.d, less: PASS
flt.d, greater: PASS
flt.d, quiet NaN first: PASS
flt.d, quiet NaN second: PASS
flt.d, quiet NaN both: PASS
flt.d, signaling NaN first: PASS
flt.d, signaling NaN second: PASS
flt.d, signaling NaN both: PASS
fle.d, equal: PASS
fle.d, less: PASS
fle.d, greater: PASS
fle.d, 0 == -0: PASS
fle.d, quiet NaN first: PASS
fle.d, quiet NaN second: PASS
fle.d, quiet NaN both: PASS
fle.d, signaling NaN first: PASS
fle.d, signaling NaN second: PASS
fle.d, signaling NaN both: PASS
fclass.d, -infinity: PASS
fclass.d, -normal: PASS
fclass.d, -subnormal: PASS
fclass.d, -0.0: PASS
fclass.d, 0.0: PASS
fclass.d, subnormal: PASS
fclass.d, normal: PASS
fclass.d, infinity: PASS
fclass.d, signaling NaN: PASS
fclass.s, quiet NaN: PASS
fcvt.w.d, truncate positive: PASS
fcvt.w.d, truncate negative: PASS
fcvt.w.d, 0.0: PASS
fcvt.w.d, -0.0: PASS
fcvt.w.d, overflow: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, underflow: PASS
fcvt.w.d, infinity: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, -infinity: PASS
fcvt.w.d, quiet NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, quiet -NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, signaling NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.wu.d, truncate positive: PASS
fcvt.wu.d, truncate negative: PASS
fcvt.wu.d, 0.0: PASS
fcvt.wu.d, -0.0: PASS
fcvt.wu.d, overflow: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, underflow: PASS
fcvt.wu.d, infinity: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, -infinity: PASS
fcvt.wu.d, quiet NaN: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, quiet -NaN: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, signaling NaN: PASS
fcvt.d.w, 0: PASS
fcvt.d.w, negative: PASS
fcvt.d.w, truncate: PASS
fcvt.d.wu, 0: PASS
fcvt.d.wu: PASS
fcvt.d.wu, truncate: PASS
fcvt.l.d, truncate positive: PASS
fcvt.l.d, truncate negative: PASS
fcvt.l.d, 0.0: PASS
fcvt.l.d, -0.0: PASS
fcvt.l.d, 32-bit overflow: PASS
fcvt.l.d, overflow: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, underflow: PASS
fcvt.l.d, infinity: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, -infinity: PASS
fcvt.l.d, quiet NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, quiet -NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, signaling NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.lu.d, truncate positive: PASS
fcvt.lu.d, truncate negative: PASS
fcvt.lu.d, 0.0: PASS
fcvt.lu.d, -0.0: PASS
fcvt.lu.d, 32-bit overflow: PASS
fcvt.lu.d, overflow: FAIL (expected 18446744073709551615; found 0)
fcvt.lu.d, underflow: PASS
fcvt.lu.d, infinity: FAIL (expected 18446744073709551615; found 0)
fcvt.lu.d, -infinity: PASS
fcvt.lu.d, quiet NaN: FAIL (expected 18446744073709551615; found 9223372036854775808)
fcvt.lu.d, quiet -NaN: FAIL (expected 18446744073709551615; found 9223372036854775808)
fcvt.lu.d, signaling NaN: PASS
fmv.x.d, positive: PASS
fmv.x.d, negative: PASS
fmv.x.d, 0.0: PASS
fmv.x.d, -0.0: PASS
fcvt.d.l, 0: PASS
fcvt.d.l, negative: PASS
fcvt.d.l, 32-bit truncate: PASS
fcvt.d.lu, 0: PASS
fcvt.d.lu: PASS
fcvt.d.lu, 32-bit truncate: PASS
fmv.d.x: PASS
Exiting @ tick 357345500 because exiting with last active thread context

1059
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/stats.txt Normal file
View File

File diff suppressed because it is too large Load Diff

11
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini
View File

@@ -88,8 +88,10 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
@@ -118,7 +120,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=insttest
cwd=
drivers=
@@ -127,14 +129,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest
executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100

15
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json
View File

@@ -192,6 +192,7 @@
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
"syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
@@ -216,21 +217,22 @@
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "LiveProcess",
"executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest",
"cxx_class": "Process",
"executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"input": "cin",
"ppid": 99,
"type": "LiveProcess",
"maxStackSize": 67108864,
"ppid": 0,
"type": "Process",
"cwd": "",
"pgid": 100,
"simpoint": 0,
"euid": 100,
"input": "cin",
"path": "system.cpu.workload",
"max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
@@ -242,6 +244,7 @@
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,

6
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr
View File

@@ -1,3 +1,5 @@
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest'
info: Increasing stack size by one page.

70
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout
View File

@@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:31
gem5 executing on zizzer, pid 34072
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-atomic
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:12:11
gem5 executing on boldrock, pid 2055
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
fld: PASS
fsd: PASS
fmadd.d: PASS
@@ -165,4 +163,62 @@ fcvt.w.d, truncate negative: PASS
fcvt.w.d, 0.0: PASS
fcvt.w.d, -0.0: PASS
fcvt.w.d, overflow: FAIL (expected 2147483647; found -2147483648)
Exiting @ tick 149676500 because target called exit()
fcvt.w.d, underflow: PASS
fcvt.w.d, infinity: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, -infinity: PASS
fcvt.w.d, quiet NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, quiet -NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, signaling NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.wu.d, truncate positive: PASS
fcvt.wu.d, truncate negative: PASS
fcvt.wu.d, 0.0: PASS
fcvt.wu.d, -0.0: PASS
fcvt.wu.d, overflow: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, underflow: PASS
fcvt.wu.d, infinity: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, -infinity: PASS
fcvt.wu.d, quiet NaN: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, quiet -NaN: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, signaling NaN: PASS
fcvt.d.w, 0: PASS
fcvt.d.w, negative: PASS
fcvt.d.w, truncate: PASS
fcvt.d.wu, 0: PASS
fcvt.d.wu: PASS
fcvt.d.wu, truncate: PASS
fcvt.l.d, truncate positive: PASS
fcvt.l.d, truncate negative: PASS
fcvt.l.d, 0.0: PASS
fcvt.l.d, -0.0: PASS
fcvt.l.d, 32-bit overflow: PASS
fcvt.l.d, overflow: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, underflow: PASS
fcvt.l.d, infinity: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, -infinity: PASS
fcvt.l.d, quiet NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, quiet -NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, signaling NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.lu.d, truncate positive: PASS
fcvt.lu.d, truncate negative: PASS
fcvt.lu.d, 0.0: PASS
fcvt.lu.d, -0.0: PASS
fcvt.lu.d, 32-bit overflow: PASS
fcvt.lu.d, overflow: FAIL (expected 18446744073709551615; found 0)
fcvt.lu.d, underflow: PASS
fcvt.lu.d, infinity: FAIL (expected 18446744073709551615; found 0)
fcvt.lu.d, -infinity: PASS
fcvt.lu.d, quiet NaN: FAIL (expected 18446744073709551615; found 9223372036854775808)
fcvt.lu.d, quiet -NaN: FAIL (expected 18446744073709551615; found 9223372036854775808)
fcvt.lu.d, signaling NaN: PASS
fmv.x.d, positive: PASS
fmv.x.d, negative: PASS
fmv.x.d, 0.0: PASS
fmv.x.d, -0.0: PASS
fcvt.d.l, 0: PASS
fcvt.d.l, negative: PASS
fcvt.d.l, 32-bit truncate: PASS
fcvt.d.lu, 0: PASS
fcvt.d.lu: PASS
fcvt.d.lu, 32-bit truncate: PASS
fmv.d.x: PASS
Exiting @ tick 255853000 because exiting with last active thread context

305
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt
View File

@@ -1,153 +1,160 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000150 # Number of seconds simulated
sim_ticks 149676500 # Number of ticks simulated
final_tick 149676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 28553 # Simulator instruction rate (inst/s)
host_op_rate 28553 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 14284274 # Simulator tick rate (ticks/s)
host_mem_usage 234416 # Number of bytes of host memory used
host_seconds 10.48 # Real time elapsed on the host
sim_insts 299191 # Number of instructions simulated
sim_ops 299191 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 1197416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 459717 # Number of bytes read from this memory
system.physmem.bytes_read::total 1657133 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1197416 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1197416 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 301409 # Number of bytes written to this memory
system.physmem.bytes_written::total 301409 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 299354 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 69843 # Number of read requests responded to by this memory
system.physmem.num_reads::total 369197 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 48546 # Number of write requests responded to by this memory
system.physmem.num_writes::total 48546 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 8000026724 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3071403995 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11071430719 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8000026724 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8000026724 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2013736291 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2013736291 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8000026724 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5085140286 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13085167010 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.numSyscalls 162 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 149676500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 299354 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 299191 # Number of instructions committed
system.cpu.committedOps 299191 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses
system.cpu.num_func_calls 21816 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls
system.cpu.num_int_insts 299008 # number of integer instructions
system.cpu.num_fp_insts 1025 # number of float instructions
system.cpu.num_int_register_reads 394163 # number of times the integer registers were read
system.cpu.num_int_register_writes 205779 # number of times the integer registers were written
system.cpu.num_fp_register_reads 851 # number of times the floating registers were read
system.cpu.num_fp_register_writes 688 # number of times the floating registers were written
system.cpu.num_mem_refs 118390 # number of memory refs
system.cpu.num_load_insts 69843 # Number of load instructions
system.cpu.num_store_insts 48547 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 299354 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 66377 # Number of branches fetched
system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction
system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction
system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction
system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction
system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction
system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction
system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction
system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction
system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction
system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 299354 # Class of executed instruction
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 369197 # Transaction distribution
system.membus.trans_dist::ReadResp 369197 # Transaction distribution
system.membus.trans_dist::WriteReq 48546 # Transaction distribution
system.membus.trans_dist::WriteResp 48546 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 598708 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 236778 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 835486 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1197416 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 761126 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1958542 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 417743 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 417743 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 417743 # Request fanout histogram
sim_seconds 0.000255
sim_ticks 255853000
final_tick 255853000
sim_freq 1000000000000
host_inst_rate 4946
host_op_rate 4960
host_tick_rate 2910956
host_mem_usage 259288
host_seconds 87.89
sim_insts 434729
sim_ops 436032
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
system.physmem.pwrStateResidencyTicks::UNDEFINED 255853000
system.physmem.bytes_read::cpu.inst 2041616
system.physmem.bytes_read::cpu.data 725609
system.physmem.bytes_read::total 2767225
system.physmem.bytes_inst_read::cpu.inst 2041616
system.physmem.bytes_inst_read::total 2041616
system.physmem.bytes_written::cpu.data 458503
system.physmem.bytes_written::total 458503
system.physmem.num_reads::cpu.inst 510404
system.physmem.num_reads::cpu.data 110145
system.physmem.num_reads::total 620549
system.physmem.num_writes::cpu.data 67023
system.physmem.num_writes::total 67023
system.physmem.bw_read::cpu.inst 7979644561
system.physmem.bw_read::cpu.data 2836038662
system.physmem.bw_read::total 10815683224
system.physmem.bw_inst_read::cpu.inst 7979644561
system.physmem.bw_inst_read::total 7979644561
system.physmem.bw_write::cpu.data 1792056376
system.physmem.bw_write::total 1792056376
system.physmem.bw_total::cpu.inst 7979644561
system.physmem.bw_total::cpu.data 4628095038
system.physmem.bw_total::total 12607739600
system.pwrStateResidencyTicks::UNDEFINED 255853000
system.cpu_clk_domain.clock 500
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
system.cpu.dtb.read_accesses 0
system.cpu.dtb.write_hits 0
system.cpu.dtb.write_misses 0
system.cpu.dtb.write_accesses 0
system.cpu.dtb.hits 0
system.cpu.dtb.misses 0
system.cpu.dtb.accesses 0
system.cpu.itb.read_hits 0
system.cpu.itb.read_misses 0
system.cpu.itb.read_accesses 0
system.cpu.itb.write_hits 0
system.cpu.itb.write_misses 0
system.cpu.itb.write_accesses 0
system.cpu.itb.hits 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 220
system.cpu.pwrStateResidencyTicks::ON 255853000
system.cpu.numCycles 511707
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
system.cpu.committedInsts 434729
system.cpu.committedOps 436032
system.cpu.num_int_alu_accesses 433908
system.cpu.num_fp_alu_accesses 1229
system.cpu.num_vec_alu_accesses 0
system.cpu.num_func_calls 23870
system.cpu.num_conditional_control_insts 71049
system.cpu.num_int_insts 433908
system.cpu.num_fp_insts 1229
system.cpu.num_vec_insts 0
system.cpu.num_int_register_reads 549660
system.cpu.num_int_register_writes 288600
system.cpu.num_fp_register_reads 988
system.cpu.num_fp_register_writes 800
system.cpu.num_vec_register_reads 0
system.cpu.num_vec_register_writes 0
system.cpu.num_mem_refs 177168
system.cpu.num_load_insts 110145
system.cpu.num_store_insts 67023
system.cpu.num_idle_cycles -0
system.cpu.num_busy_cycles 511707
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction -0
system.cpu.Branches 94919
system.cpu.op_class::No_OpClass 224 0.05% 0.05%
system.cpu.op_class::IntAlu 256681 58.83% 58.88%
system.cpu.op_class::IntMult 710 0.16% 59.05%
system.cpu.op_class::IntDiv 992 0.22% 59.27%
system.cpu.op_class::FloatAdd 133 0.03% 59.30%
system.cpu.op_class::FloatCmp 170 0.03% 59.34%
system.cpu.op_class::FloatCvt 128 0.02% 59.37%
system.cpu.op_class::FloatMult 30 0.00% 59.38%
system.cpu.op_class::FloatMultAcc 0 0.00% 59.38%
system.cpu.op_class::FloatDiv 11 0.00% 59.38%
system.cpu.op_class::FloatMisc 0 0.00% 59.38%
system.cpu.op_class::FloatSqrt 5 0.00% 59.38%
system.cpu.op_class::SimdAdd 0 0.00% 59.38%
system.cpu.op_class::SimdAddAcc 0 0.00% 59.38%
system.cpu.op_class::SimdAlu 0 0.00% 59.38%
system.cpu.op_class::SimdCmp 0 0.00% 59.38%
system.cpu.op_class::SimdCvt 0 0.00% 59.38%
system.cpu.op_class::SimdMisc 0 0.00% 59.38%
system.cpu.op_class::SimdMult 0 0.00% 59.38%
system.cpu.op_class::SimdMultAcc 0 0.00% 59.38%
system.cpu.op_class::SimdShift 0 0.00% 59.38%
system.cpu.op_class::SimdShiftAcc 0 0.00% 59.38%
system.cpu.op_class::SimdSqrt 0 0.00% 59.38%
system.cpu.op_class::SimdFloatAdd 0 0.00% 59.38%
system.cpu.op_class::SimdFloatAlu 0 0.00% 59.38%
system.cpu.op_class::SimdFloatCmp 0 0.00% 59.38%
system.cpu.op_class::SimdFloatCvt 0 0.00% 59.38%
system.cpu.op_class::SimdFloatDiv 0 0.00% 59.38%
system.cpu.op_class::SimdFloatMisc 0 0.00% 59.38%
system.cpu.op_class::SimdFloatMult 0 0.00% 59.38%
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.38%
system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.38%
system.cpu.op_class::MemRead 109574 25.11% 84.50%
system.cpu.op_class::MemWrite 66842 15.32% 99.82%
system.cpu.op_class::FloatMemRead 571 0.13% 99.95%
system.cpu.op_class::FloatMemWrite 181 0.04% 99.99%
system.cpu.op_class::IprAccess 0 0.00% 99.99%
system.cpu.op_class::InstPrefetch 0 0.00% 99.99%
system.cpu.op_class::total 436252
system.membus.snoop_filter.tot_requests 0
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
system.membus.pwrStateResidencyTicks::UNDEFINED 255853000
system.membus.trans_dist::ReadReq 618790
system.membus.trans_dist::ReadResp 620549
system.membus.trans_dist::WriteReq 65264
system.membus.trans_dist::WriteResp 65264
system.membus.trans_dist::LoadLockedReq 1759
system.membus.trans_dist::StoreCondReq 1759
system.membus.trans_dist::StoreCondResp 1759
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1020808
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 354336
system.membus.pkt_count::total 1375144
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2041616
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1184112
system.membus.pkt_size::total 3225728
system.membus.snoops 0
system.membus.snoopTraffic 0
system.membus.snoop_fanout::samples 687572
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev -0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
system.membus.snoop_fanout::0 687572 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
system.membus.snoop_fanout::total 687572
---------- End Simulation Statistics ----------

19
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini
View File

@@ -85,8 +85,10 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
@@ -122,7 +124,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=insttest
cwd=
drivers=
@@ -131,14 +133,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest
executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100
@@ -266,6 +269,7 @@ voltage_domain=system.voltage_domain
[system.ruby.dir_cntrl0]
type=Directory_Controller
children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory
addr_ranges=0:268435455:5:0:0:0
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
@@ -288,16 +292,14 @@ responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
ruby_system=system.ruby
system=system
to_memory_controller_latency=1
transitions_per_cycle=4
transitions_per_cycle=32
version=0
memory=system.mem_ctrls.port
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
addr_ranges=0:268435455:5:0:0:0
eventq_index=0
numa_high_bit=5
size=268435456
version=0
[system.ruby.dir_cntrl0.dmaRequestToDir]
type=MessageBuffer
@@ -349,6 +351,7 @@ randomization=false
[system.ruby.l1_cntrl0]
type=L1Cache_Controller
children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer
addr_ranges=0:18446744073709551615:0:0:0:0
buffer_size=0
cacheMemory=system.ruby.l1_cntrl0.cacheMemory
cache_response_latency=12

35
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json
View File

@@ -115,7 +115,6 @@
"path": "system.ruby.l1_cntrl0.requestFromCache",
"type": "MessageBuffer"
},
"cxx_class": "L1Cache_Controller",
"forwardToCache": {
"ordered": true,
"name": "forwardToCache",
@@ -168,8 +167,9 @@
"support_data_reqs": true,
"is_cpu_sequencer": true
},
"type": "L1Cache_Controller",
"cxx_class": "L1Cache_Controller",
"issue_latency": 2,
"type": "L1Cache_Controller",
"recycle_latency": 10,
"clk_domain": "system.cpu.clk_domain",
"version": 0,
@@ -241,6 +241,9 @@
},
"ruby_system": "system.ruby",
"name": "l1_cntrl0",
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"p_state_clk_gate_bins": 20,
"mandatoryQueue": {
"ordered": false,
@@ -1447,12 +1450,15 @@
"path": "system.ruby.dir_cntrl0.responseFromDir",
"type": "MessageBuffer"
},
"transitions_per_cycle": 4,
"transitions_per_cycle": 32,
"memory": {
"peer": "system.mem_ctrls.port",
"role": "MASTER"
},
"power_model": null,
"addr_ranges": [
"0:268435455:5:0:0:0"
],
"buffer_size": 0,
"ruby_system": "system.ruby",
"requestToDir": {
@@ -1487,13 +1493,13 @@
"p_state_clk_gate_bins": 20,
"directory": {
"name": "directory",
"version": 0,
"addr_ranges": [
"0:268435455:5:0:0:0"
],
"eventq_index": 0,
"cxx_class": "DirectoryMemory",
"path": "system.ruby.dir_cntrl0.directory",
"type": "RubyDirectoryMemory",
"numa_high_bit": 5,
"size": 268435456
"type": "RubyDirectoryMemory"
},
"path": "system.ruby.dir_cntrl0"
}
@@ -1548,6 +1554,7 @@
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1,
"syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
@@ -1572,21 +1579,22 @@
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "LiveProcess",
"executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest",
"cxx_class": "Process",
"executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"input": "cin",
"ppid": 99,
"type": "LiveProcess",
"maxStackSize": 67108864,
"ppid": 0,
"type": "Process",
"cwd": "",
"pgid": 100,
"simpoint": 0,
"euid": 100,
"input": "cin",
"path": "system.cpu.workload",
"max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
@@ -1598,6 +1606,7 @@
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,

8
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr
View File

@@ -4,8 +4,12 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest'
info: Increasing stack size by one page.

70
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout
View File

@@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:32
gem5 executing on zizzer, pid 34074
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:09:50
gem5 executing on boldrock, pid 1344
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
fld: PASS
fsd: PASS
fmadd.d: PASS
@@ -165,4 +163,62 @@ fcvt.w.d, truncate negative: PASS
fcvt.w.d, 0.0: PASS
fcvt.w.d, -0.0: PASS
fcvt.w.d, overflow: FAIL (expected 2147483647; found -2147483648)
Exiting @ tick 6393532 because target called exit()
fcvt.w.d, underflow: PASS
fcvt.w.d, infinity: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, -infinity: PASS
fcvt.w.d, quiet NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, quiet -NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, signaling NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.wu.d, truncate positive: PASS
fcvt.wu.d, truncate negative: PASS
fcvt.wu.d, 0.0: PASS
fcvt.wu.d, -0.0: PASS
fcvt.wu.d, overflow: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, underflow: PASS
fcvt.wu.d, infinity: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, -infinity: PASS
fcvt.wu.d, quiet NaN: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, quiet -NaN: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, signaling NaN: PASS
fcvt.d.w, 0: PASS
fcvt.d.w, negative: PASS
fcvt.d.w, truncate: PASS
fcvt.d.wu, 0: PASS
fcvt.d.wu: PASS
fcvt.d.wu, truncate: PASS
fcvt.l.d, truncate positive: PASS
fcvt.l.d, truncate negative: PASS
fcvt.l.d, 0.0: PASS
fcvt.l.d, -0.0: PASS
fcvt.l.d, 32-bit overflow: PASS
fcvt.l.d, overflow: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, underflow: PASS
fcvt.l.d, infinity: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, -infinity: PASS
fcvt.l.d, quiet NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, quiet -NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, signaling NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.lu.d, truncate positive: PASS
fcvt.lu.d, truncate negative: PASS
fcvt.lu.d, 0.0: PASS
fcvt.lu.d, -0.0: PASS
fcvt.lu.d, 32-bit overflow: PASS
fcvt.lu.d, overflow: FAIL (expected 18446744073709551615; found 0)
fcvt.lu.d, underflow: PASS
fcvt.lu.d, infinity: FAIL (expected 18446744073709551615; found 0)
fcvt.lu.d, -infinity: PASS
fcvt.lu.d, quiet NaN: FAIL (expected 18446744073709551615; found 9223372036854775808)
fcvt.lu.d, quiet -NaN: FAIL (expected 18446744073709551615; found 9223372036854775808)
fcvt.lu.d, signaling NaN: PASS
fmv.x.d, positive: PASS
fmv.x.d, negative: PASS
fmv.x.d, 0.0: PASS
fmv.x.d, -0.0: PASS
fcvt.d.l, 0: PASS
fcvt.d.l, negative: PASS
fcvt.d.l, 32-bit truncate: PASS
fcvt.d.lu, 0: PASS
fcvt.d.lu: PASS
fcvt.d.lu, 32-bit truncate: PASS
fmv.d.x: PASS
Exiting @ tick 8234747 because exiting with last active thread context

1284
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt
View File

File diff suppressed because it is too large Load Diff

11
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini
View File

@@ -85,8 +85,10 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
@@ -287,7 +289,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
type=Process
cmd=insttest
cwd=
drivers=
@@ -296,14 +298,15 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest
executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=99
ppid=0
simpoint=0
system=system
uid=100

15
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json
View File

@@ -292,6 +292,7 @@
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
"syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
@@ -376,21 +377,22 @@
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "LiveProcess",
"executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest",
"cxx_class": "Process",
"executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"input": "cin",
"ppid": 99,
"type": "LiveProcess",
"maxStackSize": 67108864,
"ppid": 0,
"type": "Process",
"cwd": "",
"pgid": 100,
"simpoint": 0,
"euid": 100,
"input": "cin",
"path": "system.cpu.workload",
"max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
@@ -402,6 +404,7 @@
}
],
"name": "cpu",
"wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,

6
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr
View File

@@ -1,3 +1,5 @@
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest'
info: Increasing stack size by one page.

70
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout
View File

@@ -3,14 +3,12 @@ Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv6
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:31
gem5 executing on zizzer, pid 34073
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing
gem5 compiled Jul 13 2017 17:09:45
gem5 started Jul 13 2017 17:11:34
gem5 executing on boldrock, pid 1863
command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
fld: PASS
fsd: PASS
fmadd.d: PASS
@@ -165,4 +163,62 @@ fcvt.w.d, truncate negative: PASS
fcvt.w.d, 0.0: PASS
fcvt.w.d, -0.0: PASS
fcvt.w.d, overflow: FAIL (expected 2147483647; found -2147483648)
Exiting @ tick 497165500 because target called exit()
fcvt.w.d, underflow: PASS
fcvt.w.d, infinity: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, -infinity: PASS
fcvt.w.d, quiet NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, quiet -NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.w.d, signaling NaN: FAIL (expected 2147483647; found -2147483648)
fcvt.wu.d, truncate positive: PASS
fcvt.wu.d, truncate negative: PASS
fcvt.wu.d, 0.0: PASS
fcvt.wu.d, -0.0: PASS
fcvt.wu.d, overflow: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, underflow: PASS
fcvt.wu.d, infinity: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, -infinity: PASS
fcvt.wu.d, quiet NaN: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, quiet -NaN: FAIL (expected 18446744073709551615; found 0)
fcvt.wu.d, signaling NaN: PASS
fcvt.d.w, 0: PASS
fcvt.d.w, negative: PASS
fcvt.d.w, truncate: PASS
fcvt.d.wu, 0: PASS
fcvt.d.wu: PASS
fcvt.d.wu, truncate: PASS
fcvt.l.d, truncate positive: PASS
fcvt.l.d, truncate negative: PASS
fcvt.l.d, 0.0: PASS
fcvt.l.d, -0.0: PASS
fcvt.l.d, 32-bit overflow: PASS
fcvt.l.d, overflow: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, underflow: PASS
fcvt.l.d, infinity: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, -infinity: PASS
fcvt.l.d, quiet NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, quiet -NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.l.d, signaling NaN: FAIL (expected 9223372036854775807; found -9223372036854775808)
fcvt.lu.d, truncate positive: PASS
fcvt.lu.d, truncate negative: PASS
fcvt.lu.d, 0.0: PASS
fcvt.lu.d, -0.0: PASS
fcvt.lu.d, 32-bit overflow: PASS
fcvt.lu.d, overflow: FAIL (expected 18446744073709551615; found 0)
fcvt.lu.d, underflow: PASS
fcvt.lu.d, infinity: FAIL (expected 18446744073709551615; found 0)
fcvt.lu.d, -infinity: PASS
fcvt.lu.d, quiet NaN: FAIL (expected 18446744073709551615; found 9223372036854775808)
fcvt.lu.d, quiet -NaN: FAIL (expected 18446744073709551615; found 9223372036854775808)
fcvt.lu.d, signaling NaN: PASS
fmv.x.d, positive: PASS
fmv.x.d, negative: PASS
fmv.x.d, 0.0: PASS
fmv.x.d, -0.0: PASS
fcvt.d.l, 0: PASS
fcvt.d.l, negative: PASS
fcvt.d.l, 32-bit truncate: PASS
fcvt.d.lu, 0: PASS
fcvt.d.lu: PASS
fcvt.d.lu, 32-bit truncate: PASS
fmv.d.x: PASS
Exiting @ tick 787032500 because exiting with last active thread context

1063
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

Some files were not shown because too many files have changed in this diff Show More