Commit Graph

17757 Commits

Author SHA1 Message Date
Gabe Black
6811158b28 scons: Use sets instead of lists to track needed target environments.
This simple change intrinsically collapses away duplicates.

Change-Id: I697c21897a81c47cbf540caa49806413dce80dba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48129
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 10:50:06 +00:00
Gabe Black
9278d7eda4 scons: Remove the unused env.Label assignment in makeEnv.
Change-Id: I33fe01bb0381061528c450bc5e8312b52882615e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48128
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 10:49:59 +00:00
Gabe Black
1a8a3864cd scons: Use Dir().Dir() and not os.path to extend CPPPATH.
Since we're already working with Dir nodes, they can figure out
appending to a path themselves without using os.path.join.

Change-Id: Ib46946d7ec181dbbf443f957f23196eb0fd7f6b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48127
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 10:49:52 +00:00
Gabe Black
1c7f63c84a scons: Use the os.path prefix when using components of that module.
That makes it obvious where the methods involved are coming from. Also
some of the imported names weren't being used.

Change-Id: I6ec75eef1e5ea9eae51e7df675e477dccb351bd1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48126
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 04:42:20 +00:00
Gabe Black
0eab559913 scons: Delete the comparison operators from SourceFile.
These are apparently not used and can be deleted.

Change-Id: I201d565d2e0207e0f43e94bbbb43ec03c2b695ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48125
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 04:42:07 +00:00
Gabe Black
a74fe97ac9 scons: Eliminate the SourceFile.basename property.
This value is used in only two places, and can be calculated in place to
avoid complexity.

Change-Id: I1e59b92521250b3f5a3e2cba599236ededf1761d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48124
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 04:41:56 +00:00
Gabe Black
b159756d1c scons: Replace the SourceFile.filename property with attribute.
The SourceFile.filename property dynamically calculated the str()
conversion of self.tnode. Since self.tnode shouldn't be changed, it
doesn't seem useful to calculate that value over and over, especially
since it adds some extra indirection and magic to something that's
really pretty simple.

Change-Id: Ia0e1e8f4b0c019a026a08b5c2730d93c66de8190
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48123
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 04:41:44 +00:00
Gabe Black
14f2bfe389 scons: Replace the extname property with os.path.splitext().
This is almost exactly the same, except it leaves the "." on the
extension, and returns an empty string instead of None if there is no
extension.

Change-Id: Idb540771007f9f7ca8aafdb09512eb1219010237
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48122
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-08-06 04:41:28 +00:00
Gabe Black
fbe5ed97c0 scons: Get rid of the unused "dirname" property of SourceFile.
Change-Id: I7c52f866542057b9f11ba96434f9c6f93ff0ea46
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48121
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 04:41:15 +00:00
Gabe Black
a5e2ef1429 scons: Make all Executables strip-able, and de-special case .fast.
The build for .fast was set up to produce a stripped executable, and the
unstripped executable was instead named .fast.unstripped. I think the
assumption that a stripped executable is faster than an unstripped
executable is flawed, since the parts of the binary that are removed,
debug symbols, are not loaded into memory anyway, so while the program
is executing it shouldn't be any different or take up any additional
memory. This also made .fast a special case compared to the other build
types, like .opt, .debug, etc.

Instead, this change makes .fast unstripped like all the other binaries,
and also makes it possible to request a stripped version of *any* binary
the build can produce with a .stripped suffix.

Change-Id: I2de82e0951d9f41c30594f32fba50acdd14ed69c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48120
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 04:41:15 +00:00
Gabe Black
c142629ccc arch,cpu: Rename RegClass to RegClassType.
This type is really an index which selects a RegClass, not a RegClass
itself.

A follow on change will rename RegClassInfo to RegClass.

Change-Id: I2c1b1d4105bd11b58680053b484d4c1aa1055a9f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45229
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 19:05:32 +00:00
Jan Vrany
db9e64a570 base: handle initial communication with GDB in attach()
When remote GDB attaches to gem5, handle the initial communication
(`qSupported` and alike) right away instead of scheduling a `DataEvent`
and firing the simulation loop in hope that GDB will be quick enough to
send initial packets before instructions are dispatched.

This requires attach() to be always called at instruction boundary
to make it safe to interact with the rest of gem5.

When `--wait-gdb` is used, connect() is called from workflow startup,
therefore on an instruction boundary and therefore needs not special
handling.

To handle case the GDB connects while simulation is already running,
we arrange (new) assynchronous IncommingConnectionEvent on listening
socket that, when there's a new connection being made, *only* schedules
*synchronous* ConnectEvent that handles the rest, *including* calling
an accept() on listening socket. This way it is safe to process commands
in attach().

In order to make the code more systematic and easier to understands,
detach() is also made to be called only synchronously (that is, at
intruction boundary). Asynchronous events and event handlers are
prefixed with "incoming".

This seems to fix the race described in 44612 [1]

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/44612

Change-Id: I33b2922ba017205acabd51b6a8be3e6fb2d6409a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48182
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 08:43:20 +00:00
Jan Vrany
6ed6f9c807 base: Extract GDB command processing into separate function
Change-Id: I1f090285f92752d6907044b9ee6ade1869a2cb9f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48181
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 08:43:20 +00:00
Giacomo Travaglini
79b57bbfb8 arch-arm: Add a shared L2 TLB to the default ArmMMU
JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I542c287a99c8b277afb4cd939c09521798dcf2f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48150
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-08-05 08:26:33 +00:00
Giacomo Travaglini
fb0929b5f9 arch-arm: Provide support for a multilevel-TLB in the ArmMMU
This is an initial implementation. It adapts the current MMU code
to account for extra levels of TLBs but it is still missing the
configurability we are looking for (to select the associativity
of the TLB and the replacement policy as an example)

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I938ec38183337cd0e839bf3e3cd03594126128cd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48149
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-08-05 08:26:33 +00:00
Giacomo Travaglini
395c6d4fa3 arch-arm: Explicitly implement I/DTLBI Ops in TLB
At the moment the ITLBI and DTLBI operations where implicitly
implemented as generic TLBIs

e.g:

* DTLBIASID, ITLBIASID = TLBIASID

This was possible as a single TLB was either an instruction TLB
or a data TLB and no generic/shared TLB option was available.
In other words, an ITLBI Op to an ITB was invalidating all entries
as we were sure the ITB was not containing data entries.

With shared TLBs, this doesn't hold true and we need to explicitly
implement I/DTLBIs

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I39a4add7674f6008dacaedfd1fd90560d264048e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48148
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 08:26:33 +00:00
Giacomo Travaglini
a23f39bc19 arch-arm: Distinguish Instruction from Data TLB entries
As we are going to support I+D (shared) TLBs we need to tag a TLB entry
as a data or instruction entry, so that I-TLBI and D-TLBI do not
over-invalidate entries

(The patch is also fixing the coding style of the TLB insertion
methods in the Table Walker)

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I3d5880175fe6eda1b2f0edcbd0ea6a146d3c7a39
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48147
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-08-05 08:26:33 +00:00
Giacomo Travaglini
242d0d467a arch: Implement operator& for TypeTLB
Change-Id: I05af52ba5e0ef84510ca3f4c27d8f9cd55e07d90
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48463
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 08:26:33 +00:00
Kai Ren
22d13aaec6 configs: Add --wait-gdb option to fs.py
Change-Id: Ib3174927ccc65ce1ddce450ce6020f74ea60d366
Signed-off-by: Kai Ren <binarystar2006@outlook.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48944
Reviewed-by: Kai Ren <binarystar.kai.ren@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 01:16:44 +00:00
Daecheol You
8e00f8e582 mem-ruby: Atomic transaction support for CHI protocol
Ruby assumes protocols use directory controllers as memory interface.
Thus, recvAtomic() uses the machine type of directory when it calls
mapAddressToMachine(). However, it doesn't work for CHI since
CHI does not use directory controllers as memory controller interface.
Therefore, the code was modified to check which controller type is used
for memory interface between MachineType_Directory and
MachineType_Memory, which is used for CHI.

Change-Id: If35a06a8a3772ce5e5b994df05c9d94c7770c90d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48403
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 00:29:34 +00:00
Gabe Black
91e24ba776 misc: Replace THE_ISA macro with IS_NULL_ISA.
Now all occurances of the THE_ISA macro which were being used to check
for anything other than the NULL_ISA have been eliminated. We still need
to be able to check whether the current ISA is the null ISA, but we
don't want to let any preprocessor checks back in which are based on
what the current ISA is.

This change removes the THE_ISA macro, and replaces it with IS_NULL_ISA
which evaluates to 1 if the ISA is null, and 0 if it isn't.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: Iec146b40d8cab846dae03e15191390f754f2b71b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48709
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 21:04:22 +00:00
Gabe Black
b71029f02b cpu-minor: Use the RegClassInfo::regName method instead of THE_ISA.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: I43b31897ed3a9e77c6d2908ac4a04f705a0f74f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48708
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 21:04:22 +00:00
Gabe Black
1e26e8f9a4 arm: Make the misc reg class return the name of misc regs.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: Ic2c8576b079c68f28b48006dd90515b1a5c68ed9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48707
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 21:04:22 +00:00
Giacomo Travaglini
1d600cd599 python: Expose the AddrRange exclude to the python world
Change-Id: I9cb1bf66d4e9390c8d3c4403afec9f896d19c162
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48904
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 09:18:40 +00:00
Giacomo Travaglini
19f2fd376b base: Add an exclude method to the AddrRange class
This will allow us to define a list of ranges provided an exclude
pattern, which is handy when a fragmented memory map is present

Change-Id: Ib3d76ef178355585d80e9e600b7c60e66efa01c1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48903
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 09:18:40 +00:00
Gabe Black
661611a8f6 cpu: Add a mechanism which lets a reg class name its members.
This can be used to get the "pretty" name for a given register index
within a register class, and can be specialized per ISA, or even per ISA
object.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: I7b290db73c7d04e0f61293ae82fc92ca5b4fe692
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48706
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 06:07:22 +00:00
Gabe Black
f15032fbb2 cpu: Use the newly promoted uReset in the minor CPU.
Rather than use an #if THE_ISA check to see if the CPU can use the
microPC accessirs, this change uses the newly promoted/exposed uReset
for the same purpose.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: I4ac931624a2c8e2bbcd5189a05d9ec174bd03d4a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48705
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 05:23:43 +00:00
Gabe Black
db1ec14120 scons: Disable the free-nonheap-object warning for gcc.
g++ 11.1 has a false positive in the systemc kernel for
free-nonheap-object which breaks the build. The check sees that an
EventWrapper is part of the systemc scheduler object, and doesn't
realize that it was *not* set to autodelete, and so would *not* delete
itself (as part of the scheduler) when it is descheduled.

Change-Id: Ia9f48f2113e8c165923e55d7db1442b11bb6a2e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48646
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 05:23:34 +00:00
Gabe Black
5e5205970b arch: Promote the micropc to the base PCState class.
The ISAs we support today mostly have a micropc, whether that's used
very heavily like on x86, or sparsely like on ARM, RISCV or SPARC. Only
MIPS and POWER don't currently use a micropc, and neither of those is
performance tuned to the point where adding some size to the PC object
should make a meaningful difference.

Because most ISAs already have a micropc anyway, and some minimal part
of managing the micropc has to be part of the guaranteed interface so
that the CPUs can work, it's a small step to make the micropc more
completely part of the base class.

This change also makes uReset part of the guaranteed interface so we can
get rid of an #if THE_ISA == in the minor CPU.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: Ide55a8feaee0bd5fff1d7ec05f95ad30a496b196
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48704
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 04:38:59 +00:00
Gabe Black
ac8d07a29e arch,cpu: Rename arch/generic/types.hh to pcstate.hh.
Also get rid of some unnecessary includes of it.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: I7556afc06401b35b9105a0009a10be15c1888be3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48703
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 04:15:21 +00:00
Gabe Black
1bf0b844ff scons: Simplify the CpuModel class into a function.
The CpuModel class looks like it was originally intended to hold a lot
more information that it does now, which is just the name of a CPU, and
whether it should be enabled by default. All the built in configs in
build_opts already explicitly list a set of CPUs, and CPUs should not,
generally speaking, be enabled by default, since they almost always need
to be specifically supported by an ISA. This is mutual, since usually
ISAs definitions are not quite correct or complete, and this is often
exposed by plugging them into different, and/or more complex CPU models
which stress those short comings.

This change drops the idea of a "default" CPU, and since the only thing
being tracked at this point is a list of CPUs, it turns CpuModel() into
a simple function which adds a name to a set of supported CPUs.

Change-Id: Id7475d5dc8548802b5253f79839da8c76ef4d165
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48963
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-03 21:06:39 +00:00
Giacomo Travaglini
3e6d08b751 tests: pyunit always exiting with 0
As unittest.TextTestRunner().run(suite) doesn't exit the script,
it won't set the exit code, even when some tests are failing.
This means testlib is always interpreting those unittests as passing
even when there are failures.

With this patch we are propagating the error to our CI system (testlib)

Change-Id: I63b7622661a19a9b40243d13b7391e510c2007d4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48969
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-03 14:16:27 +00:00
Gabe Black
d52db719cd scons: Delete the unused do_embed_text function.
Change-Id: I2ad37c9965e7a58e288711f0fa5bb1858f121c05
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48968
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-08-03 07:27:40 +00:00
Hoa Nguyen
8dffadf4e4 arch-riscv: Fix illegal instruction error message
Previously, the reason for the fault was not printed to the output.

Change-Id: I931b0de96fbb241f24ba69ad7e84d5d1c9db9e60
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48923
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-02 22:09:09 +00:00
Yu-hsin Wang
636d0c3745 base: improve gdb exception information
Even it is an unknow exception for GDB, we still can try to cast it
to std::exception and print some information from `what()`.

Change-Id: Ie0cdc978eb1b3e130bc2153eae99025dcd0109f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48825
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-02 02:07:17 +00:00
Yu-hsin Wang
29e3e03a97 fastmodel: replace memory space id lookup with getMemorySpaceId
Change-Id: Ib16ea3b92dadc149461fc40f8d85554b7afed656
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48868
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-02 02:07:17 +00:00
Yu-hsin Wang
43c6225da3 fastmodel: correct memory access space id
Change-Id: Ie513c44c362baddc0690cd97a2657f9ccdd06e96
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48823
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-02 02:07:17 +00:00
Yu-hsin Wang
32db3b4042 fastmodel: add memory space id map and getter
Change-Id: Ia9bd467b72ed59ba2b3d2aaf402761779c4e76e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48867
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-02 02:07:04 +00:00
Gabe Black
e24db5dedd dev: Fix style in i8254xGBE.cc.
Add missing spaces, remove excess spaces.

Change-Id: I9841a80172d3f1edfe68d9d4571535fe253f465e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48926
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-01 17:49:08 +00:00
Gabe Black
c81fd8e076 dev: Fix style in pktfifo.hh.
Put return types of multi-line functions on their own line.

Change-Id: I6c9cade720bd1c7aaa09c42b838c9bd83da7bc8f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48925
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-01 17:48:56 +00:00
Gabe Black
78c85d3bfa dev: Fix style in i8254xGBe_defs.hh.
Functions with more than one line in them put on a single line, lines
over 79 characters, missing spaces after ","s.

Change-Id: If3a1bf7d9b9068608ca70edf9577c0b2e1b44306
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48924
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-01 17:48:44 +00:00
Gabe Black
2cde260198 scons: Stop generating THE_ISA_STR in config/the_isa.hh.
This macro is no longer used or needed.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1056

Change-Id: Ib90f739c2d0df4c655239e55ecfe0da486ee3bf7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48885
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-31 18:07:07 +00:00
Gabe Black
a9af2e8810 sim: Don't serialize a root.isa string in checkpoints.
We are moving away from having a single ISA in a simulation. That means
it will no longer make sense to have a single, particular ISA at the
root of the object hierarchy which applies to the entire simulation.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1056

Change-Id: If4d354ac423e7ab4d3efbc6544d4feea93f56ab3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48884
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-31 18:06:52 +00:00
Gabe Black
afee6296b5 util: Add a fallback when checking for root.isa in checkpoints.
The upgraders in util/cpt_upgraders have been able to check the
root.isa element of checkpoints to determine what "the" ISA is for a
simulation, as a quick way to bail out of that particular updater
applies only to specific ISAs. We are moving away from the idea that
there is a single ISA, and so this mechanism will no longer work.

Fortunately, these cpt_upgraders are only relevant for old checkpoints.
If a checkpoint doesn't have a root.isa element inside it at all, we
know (as of this writing) that it is newer than all of these upgraders
and hence they do not apply. Any new upgraders will have to be written
to not rely on the root.isa field which will be removed. If that sort
of field is still needed, it can be added somewhere else in the
hierarchy, perhaps at the system level, or as part of the actual ISA
object.

The simplest way to implement this new behavior is to add a fallback
option when an upgrader looks for root.isa, specifically ''. If the
root.isa element does not exist, the script will get '' back, and this
will not match whatever ISA it's trying to check against. The one even
remotely more complicated script is isa-is-simobject.py which has
several behaviors for different ISAs. In that case, we just explicitly
check for '' and return early if that's what we found.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1056

Change-Id: Ie78deccb2bac51f38224e62a28dd733cefd63ed7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48883
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-07-31 09:56:40 +00:00
Tom Rollet
a366e66272 scons: fix hook for 'deprecated' attribute
On the new release, the compilation is polluted by the same warning:
    > ''deprecated' attribute directive ignored

It seems that the hook added in this patch does not work:
https://gem5-review.googlesource.com/c/public/gem5/+/45246/1..7

The snippet of code compile with TryCompile on g++{8,9}.
It probably comes from the fact that the compilation
only creates a warning and not an error.

By adding temporarily '-Werror' for this compilation test,
it filters the faulty gcc versions.

Change-Id: I2b8b7a1a7e06df437b76e98d212947f4f9452311
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48843
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-30 16:22:26 +00:00
Giacomo Travaglini
6add43e0f9 cpu: MiscReg read/writes polluting ExecContext integer stats
Change-Id: Ic505c1157f9008f19bfc500b8f20334c63a64106
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48686
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-30 14:43:48 +00:00
Nathanael Premillieu
2462e650ba mem-cache: reuse local variable in QueuedPrefetcher
Reuse local variable for PA in Queued::translationComplete.

Change-Id: Id3c0333ac1bf019ac21162aedf69f6019c818e30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48684
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2021-07-30 13:13:37 +00:00
Giacomo Travaglini
966ed29124 tests: Do not run test_hdf5 if HDF5 is not present
This regression is failing on machines not supporting the
HDF5 library

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I5c6762596dc86a9a2b0612d77f9f76e772d9fa42
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48685
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2021-07-30 08:25:53 +00:00
Nathanael Premillieu
393a964266 mem-cache: print VA and PA in the prefetch queues
As prefetcher can use VA and need translation, it is
interesting to see both VA and PA when printing the queues.
PA is printed as 0 if translation has not happened yet.
Also fix a bug when the pkt is not yet created.

Change-Id: I7cd225379c2930a8d6a7882efdb3dc7bc49fb8a3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48683
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2021-07-30 07:35:48 +00:00
Gabe Black
555cdefb34 scons: Stop providing an "m5" hard link to the gem5 binary.
gem5 has been called gem5 for a long time, and the m5 binary has not
properly existed for a long time as well. Users have had a very long
time to move to the new binary name, so it should be safe to remove this
bit of legacy cruft.

Change-Id: I8a8ac14f29d25d48afa9db0d906ed4056ac8e961
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48119
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-30 04:51:05 +00:00