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arm: Make the misc reg class return the name of misc regs.

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Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: Ic2c8576b079c68f28b48006dd90515b1a5c68ed9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48707
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-07-28 01:29:41 -07:00
parent 1d600cd599
commit 1e26e8f9a4
1 changed files with 12 additions and 1 deletions
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13
src/arch/arm/isa.cc
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@@ -45,6 +45,7 @@
#include "arch/arm/self_debug.hh"
#include "arch/arm/system.hh"
#include "arch/arm/tlbi_op.hh"
#include "base/cprintf.hh"
#include "cpu/base.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/reg_class.hh"
@@ -64,6 +65,16 @@ namespace gem5
namespace ArmISA
{
class MiscRegClassOps : public RegClassOps
{
public:
std::string
regName(const RegId &id) const override
{
return miscRegName[id.index()];
}
} miscRegClassOps;
ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
@@ -74,7 +85,7 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
_regClasses.emplace_back(NumVecRegs * TheISA::NumVecElemPerVecReg);
_regClasses.emplace_back(NumVecPredRegs);
_regClasses.emplace_back(NUM_CCREGS);
_regClasses.emplace_back(NUM_MISCREGS);
_regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps);
miscRegs[MISCREG_SCTLR_RST] = 0;