arch: Promote the micropc to the base PCState class.

The ISAs we support today mostly have a micropc, whether that's used
very heavily like on x86, or sparsely like on ARM, RISCV or SPARC. Only
MIPS and POWER don't currently use a micropc, and neither of those is
performance tuned to the point where adding some size to the PC object
should make a meaningful difference.

Because most ISAs already have a micropc anyway, and some minimal part
of managing the micropc has to be part of the guaranteed interface so
that the CPUs can work, it's a small step to make the micropc more
completely part of the base class.

This change also makes uReset part of the guaranteed interface so we can
get rid of an #if THE_ISA == in the minor CPU.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: Ide55a8feaee0bd5fff1d7ec05f95ad30a496b196
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48704
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-07-27 18:30:09 -07:00
parent ac8d07a29e
commit 5e5205970b

View File

@@ -57,11 +57,14 @@ namespace GenericISA
class PCStateBase : public Serializable
{
protected:
Addr _pc;
Addr _npc;
Addr _pc = 0;
Addr _npc = 0;
PCStateBase() : _pc(0), _npc(0) {}
PCStateBase(Addr val) : _pc(0), _npc(0) { set(val); }
MicroPC _upc = 0;
MicroPC _nupc = 1;
PCStateBase() {}
PCStateBase(Addr val) { set(val); }
public:
/**
@@ -94,7 +97,15 @@ class PCStateBase : public Serializable
MicroPC
microPC() const
{
return 0;
return _upc;
}
// Reset the macroop's upc without advancing the regular pc.
void
uReset()
{
_upc = 0;
_nupc = 1;
}
/**
@@ -122,6 +133,8 @@ class PCStateBase : public Serializable
{
SERIALIZE_SCALAR(_pc);
SERIALIZE_SCALAR(_npc);
SERIALIZE_SCALAR(_upc);
SERIALIZE_SCALAR(_nupc);
}
void
@@ -129,6 +142,8 @@ class PCStateBase : public Serializable
{
UNSERIALIZE_SCALAR(_pc);
UNSERIALIZE_SCALAR(_npc);
UNSERIALIZE_SCALAR(_upc);
UNSERIALIZE_SCALAR(_nupc);
}
};
@@ -200,22 +215,13 @@ class UPCState : public SimplePCState<InstWidth>
protected:
typedef SimplePCState<InstWidth> Base;
MicroPC _upc;
MicroPC _nupc;
public:
MicroPC upc() const { return _upc; }
void upc(MicroPC val) { _upc = val; }
MicroPC upc() const { return this->_upc; }
void upc(MicroPC val) { this->_upc = val; }
MicroPC nupc() const { return _nupc; }
void nupc(MicroPC val) { _nupc = val; }
MicroPC
microPC() const
{
return _upc;
}
MicroPC nupc() const { return this->_nupc; }
void nupc(MicroPC val) { this->_nupc = val; }
void
set(Addr val)
@@ -225,8 +231,8 @@ class UPCState : public SimplePCState<InstWidth>
nupc(1);
}
UPCState() : _upc(0), _nupc(1) {}
UPCState(Addr val) : _upc(0), _nupc(0) { set(val); }
UPCState() {}
UPCState(Addr val) { set(val); }
bool
branching() const
@@ -239,8 +245,8 @@ class UPCState : public SimplePCState<InstWidth>
void
uAdvance()
{
_upc = _nupc;
_nupc++;
upc(nupc());
nupc(nupc() + 1);
}
// End the macroop by resetting the upc and advancing the regular pc.
@@ -248,24 +254,15 @@ class UPCState : public SimplePCState<InstWidth>
uEnd()
{
this->advance();
_upc = 0;
_nupc = 1;
}
// Reset the macroop's upc without advancing the regular pc.
void
uReset()
{
_upc = 0;
_nupc = 1;
upc(0);
nupc(1);
}
bool
operator == (const UPCState<InstWidth> &opc) const
{
return Base::_pc == opc._pc &&
Base::_npc == opc._npc &&
_upc == opc._upc && _nupc == opc._nupc;
return this->pc() == opc.pc() && this->npc() == opc.npc() &&
this->upc() == opc.upc() && this->nupc() == opc.nupc();
}
bool
@@ -273,22 +270,6 @@ class UPCState : public SimplePCState<InstWidth>
{
return !(*this == opc);
}
void
serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(_upc);
SERIALIZE_SCALAR(_nupc);
}
void
unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(_upc);
UNSERIALIZE_SCALAR(_nupc);
}
};
template <int InstWidth>