arch,cpu: Rename arch/generic/types.hh to pcstate.hh.

Also get rid of some unnecessary includes of it.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: I7556afc06401b35b9105a0009a10be15c1888be3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48703
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/pcstate.hh

@@ -41,7 +41,7 @@
 #ifndef __ARCH_ARM_PCSTATE_HH__
 #define __ARCH_ARM_PCSTATE_HH__
 
-#include "arch/generic/types.hh"
+#include "arch/generic/pcstate.hh"
 #include "base/bitunion.hh"
 #include "base/types.hh"
 #include "debug/Decoder.hh"

src/arch/mips/pcstate.hh

@@ -29,7 +29,7 @@
 #ifndef __ARCH_MIPS_PCSTATE_HH__
 #define __ARCH_MIPS_PCSTATE_HH__
 
-#include "arch/generic/types.hh"
+#include "arch/generic/pcstate.hh"
 
 namespace gem5
 {

src/arch/null/pcstate.hh

@@ -35,10 +35,10 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_NULL_TYPES_HH__
-#define __ARCH_NULL_TYPES_HH__
+#ifndef __ARCH_NULL_PCSTATE_HH__
+#define __ARCH_NULL_PCSTATE_HH__
 
-#include "arch/generic/types.hh"
+#include "arch/generic/pcstate.hh"
 
 namespace gem5
 {
@@ -51,4 +51,4 @@ typedef GenericISA::UPCState<4> PCState;
 } // namespace NullISA
 } // namespace gem5
 
-#endif // __ARCH_NULL_TYPES_HH__
+#endif // __ARCH_NULL_PCSTATE_HH__

src/arch/null/vecregs.hh

@@ -40,7 +40,6 @@
 
 #include <cstdint>
 
-#include "arch/generic/types.hh"
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
 

src/arch/power/pcstate.hh

@@ -29,7 +29,7 @@
 #ifndef __ARCH_POWER_PCSTATE_HH__
 #define __ARCH_POWER_PCSTATE_HH__
 
-#include "arch/generic/types.hh"
+#include "arch/generic/pcstate.hh"
 #include "arch/power/types.hh"
 #include "enums/ByteOrder.hh"
 

src/arch/riscv/pcstate.hh

@@ -42,7 +42,7 @@
 #ifndef __ARCH_RISCV_PCSTATE_HH__
 #define __ARCH_RISCV_PCSTATE_HH__
 
-#include "arch/generic/types.hh"
+#include "arch/generic/pcstate.hh"
 
 namespace gem5
 {

src/arch/sparc/pcstate.hh

@@ -29,7 +29,7 @@
 #ifndef __ARCH_SPARC_PCSTATE_HH__
 #define __ARCH_SPARC_PCSTATE_HH__
 
-#include "arch/generic/types.hh"
+#include "arch/generic/pcstate.hh"
 
 namespace gem5
 {

src/arch/x86/pcstate.hh

@@ -38,7 +38,7 @@
 #ifndef __ARCH_X86_PCSTATE_HH__
 #define __ARCH_X86_PCSTATE_HH__
 
-#include "arch/generic/types.hh"
+#include "arch/generic/pcstate.hh"
 #include "sim/serialize.hh"
 
 namespace gem5

src/cpu/inst_res.hh

@@ -40,7 +40,6 @@
 
 #include <type_traits>
 
-#include "arch/generic/types.hh"
 #include "arch/generic/vec_reg.hh"
 
 namespace gem5

src/cpu/o3/cpu.hh

@@ -49,7 +49,6 @@
 #include <set>
 #include <vector>
 
-#include "arch/generic/types.hh"
 #include "arch/pcstate.hh"
 #include "base/statistics.hh"
 #include "config/the_isa.hh"

src/cpu/o3/regfile.cc

@@ -42,7 +42,6 @@
 #include "cpu/o3/regfile.hh"
 
 #include "cpu/o3/free_list.hh"
-#include "arch/generic/types.hh"
 #include "cpu/o3/free_list.hh"
 
 namespace gem5