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dev: Fix style in i8254xGBe_defs.hh.

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Change-Id: If3a1bf7d9b9068608ca70edf9577c0b2e1b44306
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48924
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-07-30 16:43:20 -07:00
parent 2cde260198
commit 78c85d3bfa
1 changed files with 387 additions and 272 deletions
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659
src/dev/net/i8254xGBe_defs.hh
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@@ -248,57 +248,179 @@ const uint8_t TXD_DATA = 0x1;
const uint8_t TXD_ADVCNXT = 0x2;
const uint8_t TXD_ADVDATA = 0x3;
inline bool isLegacy(TxDesc *d) { return !bits(d->d2,29,29); }
inline uint8_t getType(TxDesc *d) { return bits(d->d2, 23,20); }
inline bool isLegacy(TxDesc *d) { return !bits(d->d2, 29); }
inline uint8_t getType(TxDesc *d) { return bits(d->d2, 23, 20); }
inline bool isType(TxDesc *d, uint8_t type) { return getType(d) == type; }
inline bool isTypes(TxDesc *d, uint8_t t1, uint8_t t2) { return isType(d, t1) || isType(d, t2); }
inline bool isAdvDesc(TxDesc *d) { return !isLegacy(d) && isTypes(d, TXD_ADVDATA,TXD_ADVCNXT); }
inline bool isContext(TxDesc *d) { return !isLegacy(d) && isTypes(d,TXD_CNXT, TXD_ADVCNXT); }
inline bool isData(TxDesc *d) { return !isLegacy(d) && isTypes(d, TXD_DATA, TXD_ADVDATA); }
inline bool
isTypes(TxDesc *d, uint8_t t1, uint8_t t2)
{
return isType(d, t1) || isType(d, t2);
}
inline bool
isAdvDesc(TxDesc *d)
{
return !isLegacy(d) && isTypes(d, TXD_ADVDATA,TXD_ADVCNXT);
}
inline bool
isContext(TxDesc *d)
{
return !isLegacy(d) && isTypes(d,TXD_CNXT, TXD_ADVCNXT);
}
inline bool
isData(TxDesc *d)
{
return !isLegacy(d) && isTypes(d, TXD_DATA, TXD_ADVDATA);
}
inline Addr getBuf(TxDesc *d) { assert(isLegacy(d) || isData(d)); return d->d1; }
inline Addr getLen(TxDesc *d) { if (isLegacy(d)) return bits(d->d2,15,0); else return bits(d->d2, 19,0); }
inline Addr
getBuf(TxDesc *d)
{
assert(isLegacy(d) || isData(d));
return d->d1;
}
inline Addr
getLen(TxDesc *d)
{
if (isLegacy(d))
return bits(d->d2, 15, 0);
else
return bits(d->d2, 19, 0);
}
inline void setDd(TxDesc *d) { replaceBits(d->d2, 35, 32, 1ULL); }
inline bool ide(TxDesc *d) { return bits(d->d2, 31,31) && (getType(d) == TXD_DATA || isLegacy(d)); }
inline bool vle(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 30,30); }
inline bool rs(TxDesc *d) { return bits(d->d2, 27,27); }
inline bool ic(TxDesc *d) { assert(isLegacy(d) || isData(d)); return isLegacy(d) && bits(d->d2, 26,26); }
inline bool tse(TxDesc *d) {
inline bool
ide(TxDesc *d)
{
return bits(d->d2, 31, 31) && (getType(d) == TXD_DATA || isLegacy(d));
}
inline bool
vle(TxDesc *d)
{
assert(isLegacy(d) || isData(d));
return bits(d->d2, 30);
}
inline bool rs(TxDesc *d) { return bits(d->d2, 27); }
inline bool
ic(TxDesc *d)
{
assert(isLegacy(d) || isData(d));
return isLegacy(d) && bits(d->d2, 26);
}
inline bool
tse(TxDesc *d)
{
if (isTypes(d, TXD_CNXT, TXD_DATA))
return bits(d->d2, 26,26);
return bits(d->d2, 26);
if (isType(d, TXD_ADVDATA))
return bits(d->d2, 31, 31);
return bits(d->d2, 31);
return false;
}
inline bool ifcs(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 25,25); }
inline bool eop(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 24,24); }
inline bool ip(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 25,25); }
inline bool tcp(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 24,24); }
inline uint8_t getCso(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 23,16); }
inline uint8_t getCss(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 47,40); }
inline bool ixsm(TxDesc *d) { return isData(d) && bits(d->d2, 40,40); }
inline bool txsm(TxDesc *d) { return isData(d) && bits(d->d2, 41,41); }
inline int tucse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,63,48); }
inline int tucso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,47,40); }
inline int tucss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,39,32); }
inline int ipcse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,31,16); }
inline int ipcso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,15,8); }
inline int ipcss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,7,0); }
inline int mss(TxDesc *d) { assert(isContext(d)); return bits(d->d2,63,48); }
inline int hdrlen(TxDesc *d) {
inline bool
ifcs(TxDesc *d)
{
assert(isLegacy(d) || isData(d));
return bits(d->d2, 25);
}
inline bool
eop(TxDesc *d)
{
assert(isLegacy(d) || isData(d));
return bits(d->d2, 24);
}
inline bool
ip(TxDesc *d)
{
assert(isContext(d));
if (!isAdvDesc(d))
return bits(d->d2,47,40);
return bits(d->d2, 47,40) + bits(d->d1, 8,0) + bits(d->d1, 15, 9);
return bits(d->d2, 25);
}
inline bool
tcp(TxDesc *d)
{
assert(isContext(d));
return bits(d->d2, 24);
}
inline uint8_t
getCso(TxDesc *d)
{
assert(isLegacy(d));
return bits(d->d2, 23, 16);
}
inline uint8_t
getCss(TxDesc *d)
{
assert(isLegacy(d));
return bits(d->d2, 47, 40);
}
inline bool ixsm(TxDesc *d) { return isData(d) && bits(d->d2, 40, 40); }
inline bool txsm(TxDesc *d) { return isData(d) && bits(d->d2, 41, 41); }
inline int
tucse(TxDesc *d)
{
assert(isContext(d));
return bits(d->d1, 63, 48);
}
inline int
tucso(TxDesc *d)
{
assert(isContext(d));
return bits(d->d1, 47, 40);
}
inline int
tucss(TxDesc *d)
{
assert(isContext(d));
return bits(d->d1, 39, 32);
}
inline int
ipcse(TxDesc *d)
{
assert(isContext(d));
return bits(d->d1, 31, 16);
}
inline int
ipcso(TxDesc *d)
{
assert(isContext(d));
return bits(d->d1, 15, 8);
}
inline int
ipcss(TxDesc *d)
{
assert(isContext(d));
return bits(d->d1, 7, 0);
}
inline int
mss(TxDesc *d)
{
assert(isContext(d));
return bits(d->d2, 63, 48);
}
inline int
hdrlen(TxDesc *d)
{
assert(isContext(d));
if (!isAdvDesc(d))
return bits(d->d2, 47, 40);
return bits(d->d2, 47, 40) + bits(d->d1, 8, 0) + bits(d->d1, 15, 9);
}
inline int
getTsoLen(TxDesc *d)
{
assert(isType(d, TXD_ADVDATA));
return bits(d->d2, 63, 46);
}
inline int
utcmd(TxDesc *d)
{
assert(isContext(d));
return bits(d->d2, 24, 31);
}
inline int getTsoLen(TxDesc *d) { assert(isType(d, TXD_ADVDATA)); return bits(d->d2, 63,46); }
inline int utcmd(TxDesc *d) { assert(isContext(d)); return bits(d->d2,24,31); }
} // namespace txd_op
@@ -335,37 +457,37 @@ struct Regs : public Serializable
{
// 0x0000 CTRL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(fd,0,1); // full duplex
ADD_FIELD32(bem,1,1); // big endian mode
ADD_FIELD32(pcipr,2,1); // PCI priority
ADD_FIELD32(lrst,3,1); // link reset
ADD_FIELD32(tme,4,1); // test mode enable
ADD_FIELD32(asde,5,1); // Auto-speed detection
ADD_FIELD32(slu,6,1); // Set link up
ADD_FIELD32(ilos,7,1); // invert los-of-signal
ADD_FIELD32(speed,8,2); // speed selection bits
ADD_FIELD32(be32,10,1); // big endian mode 32
ADD_FIELD32(frcspd,11,1); // force speed
ADD_FIELD32(frcdpx,12,1); // force duplex
ADD_FIELD32(duden,13,1); // dock/undock enable
ADD_FIELD32(dudpol,14,1); // dock/undock polarity
ADD_FIELD32(fphyrst,15,1); // force phy reset
ADD_FIELD32(extlen,16,1); // external link status enable
ADD_FIELD32(rsvd,17,1); // reserved
ADD_FIELD32(sdp0d,18,1); // software controlled pin data
ADD_FIELD32(sdp1d,19,1); // software controlled pin data
ADD_FIELD32(sdp2d,20,1); // software controlled pin data
ADD_FIELD32(sdp3d,21,1); // software controlled pin data
ADD_FIELD32(sdp0i,22,1); // software controlled pin dir
ADD_FIELD32(sdp1i,23,1); // software controlled pin dir
ADD_FIELD32(sdp2i,24,1); // software controlled pin dir
ADD_FIELD32(sdp3i,25,1); // software controlled pin dir
ADD_FIELD32(rst,26,1); // reset
ADD_FIELD32(rfce,27,1); // receive flow control enable
ADD_FIELD32(tfce,28,1); // transmit flow control enable
ADD_FIELD32(rte,29,1); // routing tag enable
ADD_FIELD32(vme,30,1); // vlan enable
ADD_FIELD32(phyrst,31,1); // phy reset
ADD_FIELD32(fd, 0, 1); // full duplex
ADD_FIELD32(bem, 1, 1); // big endian mode
ADD_FIELD32(pcipr, 2, 1); // PCI priority
ADD_FIELD32(lrst, 3, 1); // link reset
ADD_FIELD32(tme, 4, 1); // test mode enable
ADD_FIELD32(asde, 5, 1); // Auto-speed detection
ADD_FIELD32(slu, 6, 1); // Set link up
ADD_FIELD32(ilos, 7, 1); // invert los-of-signal
ADD_FIELD32(speed, 8, 2); // speed selection bits
ADD_FIELD32(be32, 10, 1); // big endian mode 32
ADD_FIELD32(frcspd, 11, 1); // force speed
ADD_FIELD32(frcdpx, 12, 1); // force duplex
ADD_FIELD32(duden, 13, 1); // dock/undock enable
ADD_FIELD32(dudpol, 14, 1); // dock/undock polarity
ADD_FIELD32(fphyrst, 15, 1); // force phy reset
ADD_FIELD32(extlen, 16, 1); // external link status enable
ADD_FIELD32(rsvd, 17, 1); // reserved
ADD_FIELD32(sdp0d, 18, 1); // software controlled pin data
ADD_FIELD32(sdp1d, 19, 1); // software controlled pin data
ADD_FIELD32(sdp2d, 20, 1); // software controlled pin data
ADD_FIELD32(sdp3d, 21, 1); // software controlled pin data
ADD_FIELD32(sdp0i, 22, 1); // software controlled pin dir
ADD_FIELD32(sdp1i, 23, 1); // software controlled pin dir
ADD_FIELD32(sdp2i, 24, 1); // software controlled pin dir
ADD_FIELD32(sdp3i, 25, 1); // software controlled pin dir
ADD_FIELD32(rst, 26, 1); // reset
ADD_FIELD32(rfce, 27, 1); // receive flow control enable
ADD_FIELD32(tfce, 28, 1); // transmit flow control enable
ADD_FIELD32(rte, 29, 1); // routing tag enable
ADD_FIELD32(vme, 30, 1); // vlan enable
ADD_FIELD32(phyrst, 31, 1); // phy reset
};
CTRL ctrl;
@@ -373,18 +495,18 @@ struct Regs : public Serializable
{
// 0x0008 STATUS Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(fd,0,1); // full duplex
ADD_FIELD32(lu,1,1); // link up
ADD_FIELD32(func,2,2); // function id
ADD_FIELD32(txoff,4,1); // transmission paused
ADD_FIELD32(tbimode,5,1); // tbi mode
ADD_FIELD32(speed,6,2); // link speed
ADD_FIELD32(asdv,8,2); // auto speed detection value
ADD_FIELD32(mtxckok,10,1); // mtx clock running ok
ADD_FIELD32(pci66,11,1); // In 66Mhz pci slot
ADD_FIELD32(bus64,12,1); // in 64 bit slot
ADD_FIELD32(pcix,13,1); // Pci mode
ADD_FIELD32(pcixspd,14,2); // pci x speed
ADD_FIELD32(fd, 0, 1); // full duplex
ADD_FIELD32(lu, 1, 1); // link up
ADD_FIELD32(func, 2, 2); // function id
ADD_FIELD32(txoff, 4, 1); // transmission paused
ADD_FIELD32(tbimode, 5, 1); // tbi mode
ADD_FIELD32(speed, 6, 2); // link speed
ADD_FIELD32(asdv, 8, 2); // auto speed detection value
ADD_FIELD32(mtxckok, 10, 1); // mtx clock running ok
ADD_FIELD32(pci66, 11, 1); // In 66Mhz pci slot
ADD_FIELD32(bus64, 12, 1); // in 64 bit slot
ADD_FIELD32(pcix, 13, 1); // Pci mode
ADD_FIELD32(pcixspd, 14, 2); // pci x speed
};
STATUS sts;
@@ -392,18 +514,18 @@ struct Regs : public Serializable
{
// 0x0010 EECD Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(sk,0,1); // clack input to the eeprom
ADD_FIELD32(cs,1,1); // chip select to eeprom
ADD_FIELD32(din,2,1); // data input to eeprom
ADD_FIELD32(dout,3,1); // data output bit
ADD_FIELD32(fwe,4,2); // flash write enable
ADD_FIELD32(ee_req,6,1); // request eeprom access
ADD_FIELD32(ee_gnt,7,1); // grant eeprom access
ADD_FIELD32(ee_pres,8,1); // eeprom present
ADD_FIELD32(ee_size,9,1); // eeprom size
ADD_FIELD32(ee_sz1,10,1); // eeprom size
ADD_FIELD32(rsvd,11,2); // reserved
ADD_FIELD32(ee_type,13,1); // type of eeprom
ADD_FIELD32(sk, 0, 1); // clack input to the eeprom
ADD_FIELD32(cs, 1, 1); // chip select to eeprom
ADD_FIELD32(din, 2, 1); // data input to eeprom
ADD_FIELD32(dout, 3, 1); // data output bit
ADD_FIELD32(fwe, 4, 2); // flash write enable
ADD_FIELD32(ee_req, 6, 1); // request eeprom access
ADD_FIELD32(ee_gnt, 7, 1); // grant eeprom access
ADD_FIELD32(ee_pres, 8, 1); // eeprom present
ADD_FIELD32(ee_size, 9, 1); // eeprom size
ADD_FIELD32(ee_sz1, 10, 1); // eeprom size
ADD_FIELD32(rsvd, 11, 2); // reserved
ADD_FIELD32(ee_type, 13, 1); // type of eeprom
} ;
EECD eecd;
@@ -411,10 +533,10 @@ struct Regs : public Serializable
{
// 0x0014 EERD Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(start,0,1); // start read
ADD_FIELD32(done,1,1); // done read
ADD_FIELD32(addr,2,14); // address
ADD_FIELD32(data,16,16); // data
ADD_FIELD32(start, 0, 1); // start read
ADD_FIELD32(done, 1, 1); // done read
ADD_FIELD32(addr, 2, 14); // address
ADD_FIELD32(data, 16, 16); // data
};
EERD eerd;
@@ -422,21 +544,23 @@ struct Regs : public Serializable
{
// 0x0018 CTRL_EXT Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(gpi_en,0,4); // enable interrupts from gpio
ADD_FIELD32(phyint,5,1); // reads the phy internal int status
ADD_FIELD32(sdp2_data,6,1); // data from gpio sdp
ADD_FIELD32(spd3_data,7,1); // data frmo gpio sdp
ADD_FIELD32(spd2_iodir,10,1); // direction of sdp2
ADD_FIELD32(spd3_iodir,11,1); // direction of sdp2
ADD_FIELD32(asdchk,12,1); // initiate auto-speed-detection
ADD_FIELD32(eerst,13,1); // reset the eeprom
ADD_FIELD32(spd_byps,15,1); // bypass speed select
ADD_FIELD32(ro_dis,17,1); // disable relaxed memory ordering
ADD_FIELD32(vreg,21,1); // power down the voltage regulator
ADD_FIELD32(link_mode,22,2); // interface to talk to the link
ADD_FIELD32(iame, 27,1); // interrupt acknowledge auto-mask ??
ADD_FIELD32(drv_loaded, 28,1);// driver is loaded and incharge of device
ADD_FIELD32(timer_clr, 29,1); // clear interrupt timers after IMS clear ??
ADD_FIELD32(gpi_en, 0, 4); // enable interrupts from gpio
ADD_FIELD32(phyint, 5, 1); // reads the phy internal int status
ADD_FIELD32(sdp2_data, 6, 1); // data from gpio sdp
ADD_FIELD32(spd3_data, 7, 1); // data frmo gpio sdp
ADD_FIELD32(spd2_iodir, 10, 1); // direction of sdp2
ADD_FIELD32(spd3_iodir, 11, 1); // direction of sdp2
ADD_FIELD32(asdchk, 12, 1); // initiate auto-speed-detection
ADD_FIELD32(eerst, 13, 1); // reset the eeprom
ADD_FIELD32(spd_byps, 15, 1); // bypass speed select
ADD_FIELD32(ro_dis, 17, 1); // disable relaxed memory ordering
ADD_FIELD32(vreg, 21, 1); // power down the voltage regulator
ADD_FIELD32(link_mode, 22, 2); // interface to talk to the link
ADD_FIELD32(iame, 27, 1); // interrupt acknowledge auto-mask ??
ADD_FIELD32(drv_loaded, 28, 1); // driver is loaded and incharge of
// device
ADD_FIELD32(timer_clr, 29, 1); // clear interrupt timers after IMS
// clear ??
};
CTRL_EXT ctrl_ext;
@@ -444,13 +568,13 @@ struct Regs : public Serializable
{
// 0x0020 MDIC Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(data,0,16); // data
ADD_FIELD32(regadd,16,5); // register address
ADD_FIELD32(phyadd,21,5); // phy addresses
ADD_FIELD32(op,26,2); // opcode
ADD_FIELD32(r,28,1); // ready
ADD_FIELD32(i,29,1); // interrupt
ADD_FIELD32(e,30,1); // error
ADD_FIELD32(data, 0, 16); // data
ADD_FIELD32(regadd, 16, 5); // register address
ADD_FIELD32(phyadd, 21, 5); // phy addresses
ADD_FIELD32(op, 26, 2); // opcode
ADD_FIELD32(r, 28, 1); // ready
ADD_FIELD32(i, 29, 1); // interrupt
ADD_FIELD32(e, 30, 1); // error
};
MDIC mdic;
@@ -458,23 +582,23 @@ struct Regs : public Serializable
{
// 0x00C0 ICR Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(txdw,0,1) // tx descr witten back
ADD_FIELD32(txqe,1,1) // tx queue empty
ADD_FIELD32(lsc,2,1) // link status change
ADD_FIELD32(rxseq,3,1) // rcv sequence error
ADD_FIELD32(rxdmt0,4,1) // rcv descriptor min thresh
ADD_FIELD32(rsvd1,5,1) // reserved
ADD_FIELD32(rxo,6,1) // receive overrunn
ADD_FIELD32(rxt0,7,1) // receiver timer interrupt
ADD_FIELD32(mdac,9,1) // mdi/o access complete
ADD_FIELD32(rxcfg,10,1) // recv /c/ ordered sets
ADD_FIELD32(phyint,12,1) // phy interrupt
ADD_FIELD32(gpi1,13,1) // gpi int 1
ADD_FIELD32(gpi2,14,1) // gpi int 2
ADD_FIELD32(txdlow,15,1) // transmit desc low thresh
ADD_FIELD32(srpd,16,1) // small receive packet detected
ADD_FIELD32(ack,17,1); // receive ack frame
ADD_FIELD32(int_assert, 31,1); // interrupt caused a system interrupt
ADD_FIELD32(txdw, 0, 1) // tx descr witten back
ADD_FIELD32(txqe, 1, 1) // tx queue empty
ADD_FIELD32(lsc, 2, 1) // link status change
ADD_FIELD32(rxseq, 3, 1) // rcv sequence error
ADD_FIELD32(rxdmt0, 4, 1) // rcv descriptor min thresh
ADD_FIELD32(rsvd1, 5, 1) // reserved
ADD_FIELD32(rxo, 6, 1) // receive overrunn
ADD_FIELD32(rxt0, 7, 1) // receiver timer interrupt
ADD_FIELD32(mdac, 9, 1) // mdi/o access complete
ADD_FIELD32(rxcfg, 10, 1) // recv /c/ ordered sets
ADD_FIELD32(phyint, 12, 1) // phy interrupt
ADD_FIELD32(gpi1, 13, 1) // gpi int 1
ADD_FIELD32(gpi2, 14, 1) // gpi int 2
ADD_FIELD32(txdlow, 15, 1) // transmit desc low thresh
ADD_FIELD32(srpd, 16, 1) // small receive packet detected
ADD_FIELD32(ack, 17, 1); // receive ack frame
ADD_FIELD32(int_assert, 31, 1); // interrupt caused a system interrupt
};
ICR icr;
@@ -484,8 +608,8 @@ struct Regs : public Serializable
{
// 0x00C4 ITR Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(interval, 0,16); // minimum inter-interrutp inteval
// specified in 256ns interrupts
ADD_FIELD32(interval, 0, 16); // minimum inter-interrutp inteval
// specified in 256ns interrupts
};
ITR itr;
@@ -498,25 +622,25 @@ struct Regs : public Serializable
{
// 0x0100 RCTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(rst,0,1); // Reset
ADD_FIELD32(en,1,1); // Enable
ADD_FIELD32(sbp,2,1); // Store bad packets
ADD_FIELD32(upe,3,1); // Unicast Promiscuous enabled
ADD_FIELD32(mpe,4,1); // Multicast promiscuous enabled
ADD_FIELD32(lpe,5,1); // long packet reception enabled
ADD_FIELD32(lbm,6,2); //
ADD_FIELD32(rdmts,8,2); //
ADD_FIELD32(mo,12,2); //
ADD_FIELD32(mdr,14,1); //
ADD_FIELD32(bam,15,1); //
ADD_FIELD32(bsize,16,2); //
ADD_FIELD32(vfe,18,1); //
ADD_FIELD32(cfien,19,1); //
ADD_FIELD32(cfi,20,1); //
ADD_FIELD32(dpf,22,1); // discard pause frames
ADD_FIELD32(pmcf,23,1); // pass mac control frames
ADD_FIELD32(bsex,25,1); // buffer size extension
ADD_FIELD32(secrc,26,1); // strip ethernet crc from incoming packet
ADD_FIELD32(rst, 0, 1); // Reset
ADD_FIELD32(en, 1, 1); // Enable
ADD_FIELD32(sbp, 2, 1); // Store bad packets
ADD_FIELD32(upe, 3, 1); // Unicast Promiscuous enabled
ADD_FIELD32(mpe, 4, 1); // Multicast promiscuous enabled
ADD_FIELD32(lpe, 5, 1); // long packet reception enabled
ADD_FIELD32(lbm, 6, 2); //
ADD_FIELD32(rdmts, 8, 2); //
ADD_FIELD32(mo, 12, 2); //
ADD_FIELD32(mdr, 14, 1); //
ADD_FIELD32(bam, 15, 1); //
ADD_FIELD32(bsize, 16, 2); //
ADD_FIELD32(vfe, 18, 1); //
ADD_FIELD32(cfien, 19, 1); //
ADD_FIELD32(cfi, 20, 1); //
ADD_FIELD32(dpf, 22, 1); // discard pause frames
ADD_FIELD32(pmcf, 23, 1); // pass mac control frames
ADD_FIELD32(bsex, 25, 1); // buffer size extension
ADD_FIELD32(secrc, 26, 1); // strip ethernet crc from incoming packet
unsigned descSize()
{
switch(bsize()) {
@@ -535,7 +659,7 @@ struct Regs : public Serializable
{
// 0x0170 FCTTV
using Reg<uint32_t>::operator=;
ADD_FIELD32(ttv,0,16); // Transmit Timer Value
ADD_FIELD32(ttv, 0, 16); // Transmit Timer Value
};
FCTTV fcttv;
@@ -543,17 +667,17 @@ struct Regs : public Serializable
{
// 0x0400 TCTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(rst,0,1); // Reset
ADD_FIELD32(en,1,1); // Enable
ADD_FIELD32(bce,2,1); // busy check enable
ADD_FIELD32(psp,3,1); // pad short packets
ADD_FIELD32(ct,4,8); // collision threshold
ADD_FIELD32(cold,12,10); // collision distance
ADD_FIELD32(swxoff,22,1); // software xoff transmission
ADD_FIELD32(pbe,23,1); // packet burst enable
ADD_FIELD32(rtlc,24,1); // retransmit late collisions
ADD_FIELD32(nrtu,25,1); // on underrun no TX
ADD_FIELD32(mulr,26,1); // multiple request
ADD_FIELD32(rst, 0, 1); // Reset
ADD_FIELD32(en, 1, 1); // Enable
ADD_FIELD32(bce, 2, 1); // busy check enable
ADD_FIELD32(psp, 3, 1); // pad short packets
ADD_FIELD32(ct, 4, 8); // collision threshold
ADD_FIELD32(cold, 12, 10); // collision distance
ADD_FIELD32(swxoff, 22, 1); // software xoff transmission
ADD_FIELD32(pbe, 23, 1); // packet burst enable
ADD_FIELD32(rtlc, 24, 1); // retransmit late collisions
ADD_FIELD32(nrtu, 25, 1); // on underrun no TX
ADD_FIELD32(mulr, 26, 1); // multiple request
};
TCTL tctl;
@@ -561,8 +685,8 @@ struct Regs : public Serializable
{
// 0x1000 PBA Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(rxa,0,16);
ADD_FIELD32(txa,16,16);
ADD_FIELD32(rxa, 0, 16);
ADD_FIELD32(txa, 16, 16);
};
PBA pba;
@@ -570,9 +694,9 @@ struct Regs : public Serializable
{
// 0x2160 FCRTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(rtl,3,28); // make this bigger than the spec so we can have
// a larger buffer
ADD_FIELD32(xone, 31,1);
ADD_FIELD32(rtl, 3, 28); // make this bigger than the spec so we can
// have a larger buffer
ADD_FIELD32(xone, 31, 1);
};
FCRTL fcrtl;
@@ -580,9 +704,9 @@ struct Regs : public Serializable
{
// 0x2168 FCRTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(rth,3,13); // make this bigger than the spec so we can have
//a larger buffer
ADD_FIELD32(xfce, 31,1);
ADD_FIELD32(rth, 3, 13); // make this bigger than the spec so we can
// have a larger buffer
ADD_FIELD32(xfce, 31, 1);
};
FCRTH fcrth;
@@ -590,8 +714,8 @@ struct Regs : public Serializable
{
// 0x2800 RDBA Register
using Reg<uint64_t>::operator=;
ADD_FIELD64(rdbal,0,32); // base address of rx descriptor ring
ADD_FIELD64(rdbah,32,32); // base address of rx descriptor ring
ADD_FIELD64(rdbal, 0, 32); // base address of rx descriptor ring
ADD_FIELD64(rdbah, 32, 32); // base address of rx descriptor ring
};
RDBA rdba;
@@ -599,7 +723,7 @@ struct Regs : public Serializable
{
// 0x2808 RDLEN Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer
ADD_FIELD32(len, 7, 13); // number of bytes in the descriptor buffer
};
RDLEN rdlen;
@@ -609,8 +733,8 @@ struct Regs : public Serializable
using Reg<uint32_t>::operator=;
ADD_FIELD32(pktlen, 0, 8);
ADD_FIELD32(hdrlen, 8, 8); // guess based on header, not documented
ADD_FIELD32(desctype, 25,3); // type of descriptor 000 legacy, 001 adv,
//101 hdr split
ADD_FIELD32(desctype, 25, 3); // type of descriptor 000 legacy,
// 001 adv, 101 hdr split
unsigned bufLen() { return pktlen() << 10; }
unsigned hdrLen() { return hdrlen() << 6; }
};
@@ -620,7 +744,7 @@ struct Regs : public Serializable
{
// 0x2810 RDH Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(rdh,0,16); // head of the descriptor ring
ADD_FIELD32(rdh, 0, 16); // head of the descriptor ring
};
RDH rdh;
@@ -628,7 +752,7 @@ struct Regs : public Serializable
{
// 0x2818 RDT Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(rdt,0,16); // tail of the descriptor ring
ADD_FIELD32(rdt, 0, 16); // tail of the descriptor ring
};
RDT rdt;
@@ -636,8 +760,8 @@ struct Regs : public Serializable
{
// 0x2820 RDTR Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(delay,0,16); // receive delay timer
ADD_FIELD32(fpd, 31,1); // flush partial descriptor block ??
ADD_FIELD32(delay, 0, 16); // receive delay timer
ADD_FIELD32(fpd, 31, 1); // flush partial descriptor block ??
};
RDTR rdtr;
@@ -645,12 +769,12 @@ struct Regs : public Serializable
{
// 0x2828 RXDCTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(pthresh,0,6); // prefetch threshold, less that this
// consider prefetch
ADD_FIELD32(hthresh,8,6); // number of descriptors in host mem to
// consider prefetch
ADD_FIELD32(wthresh,16,6); // writeback threshold
ADD_FIELD32(gran,24,1); // granularity 0 = desc, 1 = cacheline
ADD_FIELD32(pthresh, 0, 6); // prefetch threshold, less that this
// consider prefetch
ADD_FIELD32(hthresh, 8, 6); // number of descriptors in host mem to
// consider prefetch
ADD_FIELD32(wthresh, 16, 6); // writeback threshold
ADD_FIELD32(gran, 24, 1); // granularity 0 = desc, 1 = cacheline
};
RXDCTL rxdctl;
@@ -658,7 +782,7 @@ struct Regs : public Serializable
{
// 0x282C RADV Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(idv,0,16); // absolute interrupt delay
ADD_FIELD32(idv, 0, 16); // absolute interrupt delay
};
RADV radv;
@@ -666,7 +790,7 @@ struct Regs : public Serializable
{
// 0x2C00 RSRPD Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(idv,0,12); // size to interrutp on small packets
ADD_FIELD32(idv, 0, 12); // size to interrutp on small packets
};
RSRPD rsrpd;
@@ -674,8 +798,8 @@ struct Regs : public Serializable
{
// 0x3800 TDBAL Register
using Reg<uint64_t>::operator=;
ADD_FIELD64(tdbal,0,32); // base address of transmit descriptor ring
ADD_FIELD64(tdbah,32,32); // base address of transmit descriptor ring
ADD_FIELD64(tdbal, 0, 32); // base address of transmit descriptor ring
ADD_FIELD64(tdbah, 32, 32); // base address of transmit descriptor ring
};
TDBA tdba;
@@ -683,7 +807,7 @@ struct Regs : public Serializable
{
// 0x3808 TDLEN Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer
ADD_FIELD32(len, 7, 13); // number of bytes in the descriptor buffer
};
TDLEN tdlen;
@@ -691,7 +815,7 @@ struct Regs : public Serializable
{
// 0x3810 TDH Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(tdh,0,16); // head of the descriptor ring
ADD_FIELD32(tdh, 0, 16); // head of the descriptor ring
};
TDH tdh;
@@ -700,7 +824,7 @@ struct Regs : public Serializable
// 0x3814 TXDCA_CTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(cpu_mask, 0, 5);
ADD_FIELD32(enabled, 5,1);
ADD_FIELD32(enabled, 5, 1);
ADD_FIELD32(relax_ordering, 6, 1);
};
TXDCA_CTL txdca_ctl;
@@ -709,7 +833,7 @@ struct Regs : public Serializable
{
// 0x3818 TDT Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(tdt,0,16); // tail of the descriptor ring
ADD_FIELD32(tdt, 0, 16); // tail of the descriptor ring
};
TDT tdt;
@@ -717,7 +841,7 @@ struct Regs : public Serializable
{
// 0x3820 TIDV Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(idv,0,16); // interrupt delay
ADD_FIELD32(idv, 0, 16); // interrupt delay
};
TIDV tidv;
@@ -725,16 +849,17 @@ struct Regs : public Serializable
{
// 0x3828 TXDCTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(pthresh, 0,6); // if number of descriptors control has is
// below this number, a prefetch is considered
ADD_FIELD32(hthresh,8,8); // number of valid descriptors is host memory
// before a prefetch is considered
ADD_FIELD32(wthresh,16,6); // number of descriptors to keep until
ADD_FIELD32(pthresh, 0, 6); // if number of descriptors control has is
// below this number, a prefetch is
//considered
ADD_FIELD32(hthresh, 8, 8); // number of valid descriptors is host
// memory before a prefetch is considered
ADD_FIELD32(wthresh, 16, 6);// number of descriptors to keep until
// writeback is considered
ADD_FIELD32(gran, 24,1); // granulatiry of above values (0 = cacheline,
// 1 == desscriptor)
ADD_FIELD32(lwthresh,25,7); // xmit descriptor low thresh, interrupt
// below this level
ADD_FIELD32(gran, 24, 1); // granulatiry of above values
// (0 = cacheline, 1 == desscriptor)
ADD_FIELD32(lwthresh, 25, 7); // xmit descriptor low thresh, interrupt
// below this level
};
TXDCTL txdctl;
@@ -742,29 +867,19 @@ struct Regs : public Serializable
{
// 0x382C TADV Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(idv,0,16); // absolute interrupt delay
ADD_FIELD32(idv, 0, 16); // absolute interrupt delay
};
TADV tadv;
/*
struct TDWBA : public Reg<uint64_t>
{
// 0x3838 TDWBA Register
using Reg<uint64_t>::operator=;
ADD_FIELD64(en,0,1); // enable transmit description ring address writeback
ADD_FIELD64(tdwbal,2,32); // base address of transmit descriptor ring address writeback
ADD_FIELD64(tdwbah,32,32); // base address of transmit descriptor ring
};
TDWBA tdwba;*/
uint64_t tdwba;
struct RXCSUM : public Reg<uint32_t>
{
// 0x5000 RXCSUM Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(pcss,0,8);
ADD_FIELD32(ipofld,8,1);
ADD_FIELD32(tuofld,9,1);
ADD_FIELD32(pcsd, 13,1);
ADD_FIELD32(pcss, 0, 8);
ADD_FIELD32(ipofld, 8, 1);
ADD_FIELD32(tuofld, 9, 1);
ADD_FIELD32(pcsd, 13, 1);
};
RXCSUM rxcsum;
@@ -774,16 +889,16 @@ struct Regs : public Serializable
{
// 0x5008 RFCTL Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(iscsi_dis,0,1);
ADD_FIELD32(iscsi_dwc,1,5);
ADD_FIELD32(nfsw_dis,6,1);
ADD_FIELD32(nfsr_dis,7,1);
ADD_FIELD32(nfs_ver,8,2);
ADD_FIELD32(ipv6_dis,10,1);
ADD_FIELD32(ipv6xsum_dis,11,1);
ADD_FIELD32(ackdis,13,1);
ADD_FIELD32(ipfrsp_dis,14,1);
ADD_FIELD32(exsten,15,1);
ADD_FIELD32(iscsi_dis, 0, 1);
ADD_FIELD32(iscsi_dwc, 1, 5);
ADD_FIELD32(nfsw_dis, 6, 1);
ADD_FIELD32(nfsr_dis, 7, 1);
ADD_FIELD32(nfs_ver, 8, 2);
ADD_FIELD32(ipv6_dis, 10, 1);
ADD_FIELD32(ipv6xsum_dis, 11, 1);
ADD_FIELD32(ackdis, 13, 1);
ADD_FIELD32(ipfrsp_dis, 14, 1);
ADD_FIELD32(exsten, 15, 1);
};
RFCTL rfctl;
@@ -791,33 +906,33 @@ struct Regs : public Serializable
{
// 0x5820 MANC Register
using Reg<uint32_t>::operator=;
ADD_FIELD32(smbus,0,1); // SMBus enabled #####
ADD_FIELD32(asf,1,1); // ASF enabled #####
ADD_FIELD32(ronforce,2,1); // reset of force
ADD_FIELD32(rsvd,3,5); // reserved
ADD_FIELD32(rmcp1,8,1); // rcmp1 filtering
ADD_FIELD32(rmcp2,9,1); // rcmp2 filtering
ADD_FIELD32(ipv4,10,1); // enable ipv4
ADD_FIELD32(ipv6,11,1); // enable ipv6
ADD_FIELD32(snap,12,1); // accept snap
ADD_FIELD32(arp,13,1); // filter arp #####
ADD_FIELD32(neighbor,14,1); // neighbor discovery
ADD_FIELD32(arp_resp,15,1); // arp response
ADD_FIELD32(tcorst,16,1); // tco reset happened
ADD_FIELD32(rcvtco,17,1); // receive tco enabled ######
ADD_FIELD32(blkphyrst,18,1);// block phy resets ########
ADD_FIELD32(rcvall,19,1); // receive all
ADD_FIELD32(macaddrfltr,20,1); // mac address filtering ######
ADD_FIELD32(mng2host,21,1); // mng2 host packets #######
ADD_FIELD32(ipaddrfltr,22,1); // ip address filtering
ADD_FIELD32(xsumfilter,23,1); // checksum filtering
ADD_FIELD32(brfilter,24,1); // broadcast filtering
ADD_FIELD32(smbreq,25,1); // smb request
ADD_FIELD32(smbgnt,26,1); // smb grant
ADD_FIELD32(smbclkin,27,1); // smbclkin
ADD_FIELD32(smbdatain,28,1); // smbdatain
ADD_FIELD32(smbdataout,29,1); // smb data out
ADD_FIELD32(smbclkout,30,1); // smb clock out
ADD_FIELD32(smbus, 0, 1); // SMBus enabled #####
ADD_FIELD32(asf, 1, 1); // ASF enabled #####
ADD_FIELD32(ronforce, 2, 1); // reset of force
ADD_FIELD32(rsvd, 3, 5); // reserved
ADD_FIELD32(rmcp1, 8, 1); // rcmp1 filtering
ADD_FIELD32(rmcp2, 9, 1); // rcmp2 filtering
ADD_FIELD32(ipv4, 10, 1); // enable ipv4
ADD_FIELD32(ipv6, 11, 1); // enable ipv6
ADD_FIELD32(snap, 12, 1); // accept snap
ADD_FIELD32(arp, 13, 1); // filter arp #####
ADD_FIELD32(neighbor, 14, 1); // neighbor discovery
ADD_FIELD32(arp_resp, 15, 1); // arp response
ADD_FIELD32(tcorst, 16, 1); // tco reset happened
ADD_FIELD32(rcvtco, 17, 1); // receive tco enabled ######
ADD_FIELD32(blkphyrst, 18, 1);// block phy resets ########
ADD_FIELD32(rcvall, 19, 1); // receive all
ADD_FIELD32(macaddrfltr, 20, 1); // mac address filtering ######
ADD_FIELD32(mng2host, 21, 1); // mng2 host packets #######
ADD_FIELD32(ipaddrfltr, 22, 1); // ip address filtering
ADD_FIELD32(xsumfilter, 23, 1); // checksum filtering
ADD_FIELD32(brfilter, 24, 1); // broadcast filtering
ADD_FIELD32(smbreq, 25, 1); // smb request
ADD_FIELD32(smbgnt, 26, 1); // smb grant
ADD_FIELD32(smbclkin, 27, 1); // smbclkin
ADD_FIELD32(smbdatain, 28, 1); // smbdatain
ADD_FIELD32(smbdataout, 29, 1); // smb data out
ADD_FIELD32(smbclkout, 30, 1); // smb clock out
};
MANC manc;
@@ -825,9 +940,9 @@ struct Regs : public Serializable
{
// 0x5B50 SWSM register
using Reg<uint32_t>::operator=;
ADD_FIELD32(smbi,0,1); // Semaphone bit
ADD_FIELD32(swesmbi, 1,1); // Software eeporm semaphore
ADD_FIELD32(wmng, 2,1); // Wake MNG clock
ADD_FIELD32(smbi, 0, 1); // Semaphone bit
ADD_FIELD32(swesmbi, 1, 1); // Software eeporm semaphore
ADD_FIELD32(wmng, 2, 1); // Wake MNG clock
ADD_FIELD32(reserved, 3, 29);
};
SWSM swsm;
@@ -836,12 +951,12 @@ struct Regs : public Serializable
{
// 0x5B54 FWSM register
using Reg<uint32_t>::operator=;
ADD_FIELD32(eep_fw_semaphore,0,1);
ADD_FIELD32(fw_mode, 1,3);
ADD_FIELD32(ide, 4,1);
ADD_FIELD32(sol, 5,1);
ADD_FIELD32(eep_roload, 6,1);
ADD_FIELD32(reserved, 7,8);
ADD_FIELD32(eep_fw_semaphore, 0, 1);
ADD_FIELD32(fw_mode, 1, 3);
ADD_FIELD32(ide, 4, 1);
ADD_FIELD32(sol, 5, 1);
ADD_FIELD32(eep_roload, 6, 1);
ADD_FIELD32(reserved, 7, 8);
ADD_FIELD32(fw_val_bit, 15, 1);
ADD_FIELD32(reset_cnt, 16, 3);
ADD_FIELD32(ext_err_ind, 19, 6);