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cpu: MiscReg read/writes polluting ExecContext integer stats

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Change-Id: Ic505c1157f9008f19bfc500b8f20334c63a64106
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48686
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2021-07-29 13:43:59 +01:00
parent 2462e650ba
commit 6add43e0f9
1 changed files with 13 additions and 5 deletions
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18
src/cpu/simple/exec_context.hh
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2018, 2020 ARM Limited
* Copyright (c) 2014-2018, 2020-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -128,6 +128,10 @@ class SimpleExecContext : public ExecContext
"Number of times the CC registers were read"),
ADD_STAT(numCCRegWrites, statistics::units::Count::get(),
"Number of times the CC registers were written"),
ADD_STAT(numMiscRegReads, statistics::units::Count::get(),
"Number of times the Misc registers were read"),
ADD_STAT(numMiscRegWrites, statistics::units::Count::get(),
"Number of times the Misc registers were written"),
ADD_STAT(numMemRefs, statistics::units::Count::get(),
"Number of memory refs"),
ADD_STAT(numLoadInsts, statistics::units::Count::get(),
@@ -237,6 +241,10 @@ class SimpleExecContext : public ExecContext
statistics::Scalar numCCRegReads;
statistics::Scalar numCCRegWrites;
// Number of misc register file accesses
statistics::Scalar numMiscRegReads;
statistics::Scalar numMiscRegWrites;
// Number of simulated memory references
statistics::Scalar numMemRefs;
statistics::Scalar numLoadInsts;
@@ -423,7 +431,7 @@ class SimpleExecContext : public ExecContext
RegVal
readMiscRegOperand(const StaticInst *si, int idx) override
{
execContextStats.numIntRegReads++;
execContextStats.numMiscRegReads++;
const RegId& reg = si->srcRegIdx(idx);
assert(reg.is(MiscRegClass));
return thread->readMiscReg(reg.index());
@@ -432,7 +440,7 @@ class SimpleExecContext : public ExecContext
void
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
execContextStats.numIntRegWrites++;
execContextStats.numMiscRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(MiscRegClass));
thread->setMiscReg(reg.index(), val);
@@ -445,7 +453,7 @@ class SimpleExecContext : public ExecContext
RegVal
readMiscReg(int misc_reg) override
{
execContextStats.numIntRegReads++;
execContextStats.numMiscRegReads++;
return thread->readMiscReg(misc_reg);
}
@@ -456,7 +464,7 @@ class SimpleExecContext : public ExecContext
void
setMiscReg(int misc_reg, RegVal val) override
{
execContextStats.numIntRegWrites++;
execContextStats.numMiscRegWrites++;
thread->setMiscReg(misc_reg, val);
}