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util: Add a fallback when checking for root.isa in checkpoints.

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The upgraders in util/cpt_upgraders have been able to check the
root.isa element of checkpoints to determine what "the" ISA is for a
simulation, as a quick way to bail out of that particular updater
applies only to specific ISAs. We are moving away from the idea that
there is a single ISA, and so this mechanism will no longer work.

Fortunately, these cpt_upgraders are only relevant for old checkpoints.
If a checkpoint doesn't have a root.isa element inside it at all, we
know (as of this writing) that it is newer than all of these upgraders
and hence they do not apply. Any new upgraders will have to be written
to not rely on the root.isa field which will be removed. If that sort
of field is still needed, it can be added somewhere else in the
hierarchy, perhaps at the system level, or as part of the actual ISA
object.

The simplest way to implement this new behavior is to add a fallback
option when an upgrader looks for root.isa, specifically ''. If the
root.isa element does not exist, the script will get '' back, and this
will not match whatever ISA it's trying to check against. The one even
remotely more complicated script is isa-is-simobject.py which has
several behaviors for different ISAs. In that case, we just explicitly
check for '' and return early if that's what we found.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1056

Change-Id: Ie78deccb2bac51f38224e62a28dd733cefd63ed7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48883
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
This commit is contained in:
Gabe Black
2021-07-30 02:11:07 -07:00
parent a366e66272
commit afee6296b5
12 changed files with 14 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
util/cpt_upgraders/arm-ccregs.py
View File

@@ -1,7 +1,7 @@
# Use condition code registers for the ARM architecture.
# Previously the integer register file was used for these registers.
def upgrader(cpt):
if cpt.get('root','isa') == 'arm':
if cpt.get('root', 'isa', fallback='') == 'arm':
for sec in cpt.sections():
import re

2
util/cpt_upgraders/arm-contextidr-el2.py
View File

@@ -1,6 +1,6 @@
# Add the ARM CONTEXTIDR_EL2 miscreg.
def upgrader(cpt):
if cpt.get('root','isa') == 'arm':
if cpt.get('root', 'isa', fallback='') == 'arm':
for sec in cpt.sections():
import re
# Search for all ISA sections

2
util/cpt_upgraders/arm-gem5-gic-ext.py
View File

@@ -38,7 +38,7 @@ def upgrader(cpt):
structures. Resize them to match the new GIC."""
import re
if cpt.get('root','isa') != 'arm':
if cpt.get('root', 'isa', fallback='') != 'arm':
return
old_cpu_max = 8

2
util/cpt_upgraders/arm-gicv2-banked-regs.py
View File

@@ -35,7 +35,7 @@
# duplicate banked registers into new per-cpu arrays.
def upgrader(cpt):
if cpt.get('root','isa') == 'arm':
if cpt.get('root', 'isa', fallback='') == 'arm':
for sec in cpt.sections():
import re

2
util/cpt_upgraders/arm-hdlcd-upgrade.py
View File

@@ -39,7 +39,7 @@ def upgrader(cpt):
after they are loaded. Expect some timing differences."""
import re
if cpt.get('root','isa') != 'arm':
if cpt.get('root', 'isa', fallback='') != 'arm':
return
option_names = {

2
util/cpt_upgraders/arm-miscreg-teehbr.py
View File

@@ -1,6 +1,6 @@
# Add the ARM MISCREG TEEHBR
def upgrader(cpt):
if cpt.get('root','isa') == 'arm':
if cpt.get('root', 'isa', fallback='') == 'arm':
for sec in cpt.sections():
import re
# Search for all ISA sections

2
util/cpt_upgraders/arm-sve.py
View File

@@ -7,7 +7,7 @@ def upgrader(cpt):
2) Set isa.sveVL to 1
3) Add SVE misc registers in the checkpoint
"""
if cpt.get('root','isa') == 'arm':
if cpt.get('root', 'isa', fallback='') == 'arm':
for sec in cpt.sections():
import re
# Search for all ISA sections

2
util/cpt_upgraders/arm-sysreg-mapping-ns.py
View File

@@ -35,7 +35,7 @@
# reflect updated register mappings for ARM ISA
def upgrader(cpt):
if cpt.get('root','isa') == 'arm':
if cpt.get('root', 'isa', fallback='') == 'arm':
for sec in cpt.sections():
import re
# Search for all ISA sections

2
util/cpt_upgraders/armv8.py
View File

@@ -1,6 +1,6 @@
# Add all ARMv8 state
def upgrader(cpt):
if cpt.get('root','isa') != 'arm':
if cpt.get('root', 'isa', fallback='') != 'arm':
return
import re
print("Warning: The size of the FP register file has changed. "

4
util/cpt_upgraders/isa-is-simobject.py
View File

@@ -1,7 +1,9 @@
# The ISA is now a separate SimObject, which means that we serialize
# it in a separate section instead of as a part of the ThreadContext.
def upgrader(cpt):
isa = cpt.get('root','isa')
isa = cpt.get('root', 'isa', fallback='')
if isa == '':
return
isa_fields = {
"arm" : ( "miscRegs" ),
"sparc" : ( "asi", "tick", "fprs", "gsr", "softint", "tick_cmpr",

2
util/cpt_upgraders/remove-arm-cpsr-mode-miscreg.py
View File

@@ -1,6 +1,6 @@
# Remove the MISCREG_CPSR_MODE register from the ARM register file
def upgrader(cpt):
if cpt.get('root','isa') == 'arm':
if cpt.get('root', 'isa', fallback='') == 'arm':
for sec in cpt.sections():
import re
# Search for all ISA sections

2
util/cpt_upgraders/x86-add-tlb.py
View File

@@ -1,6 +1,6 @@
# Add TLB to x86 checkpoints
def upgrader(cpt):
if cpt.get('root','isa') == 'x86':
if cpt.get('root', 'isa', fallback='') == 'x86':
for sec in cpt.sections():
import re
# Search for all ISA sections