diff --git a/util/cpt_upgraders/arm-ccregs.py b/util/cpt_upgraders/arm-ccregs.py
index 2e3cf1ac2f..3bce03608d 100644
--- a/util/cpt_upgraders/arm-ccregs.py
+++ b/util/cpt_upgraders/arm-ccregs.py
@@ -1,7 +1,7 @@
 # Use condition code registers for the ARM architecture.
 # Previously the integer register file was used for these registers.
 def upgrader(cpt):
-    if cpt.get('root','isa') == 'arm':
+    if cpt.get('root', 'isa', fallback='') == 'arm':
         for sec in cpt.sections():
             import re
 
diff --git a/util/cpt_upgraders/arm-contextidr-el2.py b/util/cpt_upgraders/arm-contextidr-el2.py
index 9910ded78b..87d7ab670b 100644
--- a/util/cpt_upgraders/arm-contextidr-el2.py
+++ b/util/cpt_upgraders/arm-contextidr-el2.py
@@ -1,6 +1,6 @@
 # Add the ARM CONTEXTIDR_EL2 miscreg.
 def upgrader(cpt):
-    if cpt.get('root','isa') == 'arm':
+    if cpt.get('root', 'isa', fallback='') == 'arm':
         for sec in cpt.sections():
             import re
             # Search for all ISA sections
diff --git a/util/cpt_upgraders/arm-gem5-gic-ext.py b/util/cpt_upgraders/arm-gem5-gic-ext.py
index 50114b373c..d4d588042e 100644
--- a/util/cpt_upgraders/arm-gem5-gic-ext.py
+++ b/util/cpt_upgraders/arm-gem5-gic-ext.py
@@ -38,7 +38,7 @@ def upgrader(cpt):
     structures. Resize them to match the new GIC."""
 
     import re
-    if cpt.get('root','isa') != 'arm':
+    if cpt.get('root', 'isa', fallback='') != 'arm':
         return
 
     old_cpu_max = 8
diff --git a/util/cpt_upgraders/arm-gicv2-banked-regs.py b/util/cpt_upgraders/arm-gicv2-banked-regs.py
index 703598ceab..e6437e62df 100644
--- a/util/cpt_upgraders/arm-gicv2-banked-regs.py
+++ b/util/cpt_upgraders/arm-gicv2-banked-regs.py
@@ -35,7 +35,7 @@
 
 # duplicate banked registers into new per-cpu arrays.
 def upgrader(cpt):
-    if cpt.get('root','isa') == 'arm':
+    if cpt.get('root', 'isa', fallback='') == 'arm':
         for sec in cpt.sections():
             import re
 
diff --git a/util/cpt_upgraders/arm-hdlcd-upgrade.py b/util/cpt_upgraders/arm-hdlcd-upgrade.py
index 05a3bb5f2d..a7885a295c 100644
--- a/util/cpt_upgraders/arm-hdlcd-upgrade.py
+++ b/util/cpt_upgraders/arm-hdlcd-upgrade.py
@@ -39,7 +39,7 @@ def upgrader(cpt):
     after they are loaded. Expect some timing differences."""
 
     import re
-    if cpt.get('root','isa') != 'arm':
+    if cpt.get('root', 'isa', fallback='') != 'arm':
         return
 
     option_names = {
diff --git a/util/cpt_upgraders/arm-miscreg-teehbr.py b/util/cpt_upgraders/arm-miscreg-teehbr.py
index f0174d5985..1717d40208 100644
--- a/util/cpt_upgraders/arm-miscreg-teehbr.py
+++ b/util/cpt_upgraders/arm-miscreg-teehbr.py
@@ -1,6 +1,6 @@
 # Add the ARM MISCREG TEEHBR
 def upgrader(cpt):
-    if cpt.get('root','isa') == 'arm':
+    if cpt.get('root', 'isa', fallback='') == 'arm':
         for sec in cpt.sections():
             import re
             # Search for all ISA sections
diff --git a/util/cpt_upgraders/arm-sve.py b/util/cpt_upgraders/arm-sve.py
index aa66045c88..4ef28d0a6e 100644
--- a/util/cpt_upgraders/arm-sve.py
+++ b/util/cpt_upgraders/arm-sve.py
@@ -7,7 +7,7 @@ def upgrader(cpt):
     2) Set isa.sveVL to 1
     3) Add SVE misc registers in the checkpoint
     """
-    if cpt.get('root','isa') == 'arm':
+    if cpt.get('root', 'isa', fallback='') == 'arm':
         for sec in cpt.sections():
             import re
             # Search for all ISA sections
diff --git a/util/cpt_upgraders/arm-sysreg-mapping-ns.py b/util/cpt_upgraders/arm-sysreg-mapping-ns.py
index a9aac389dd..e0418300e2 100644
--- a/util/cpt_upgraders/arm-sysreg-mapping-ns.py
+++ b/util/cpt_upgraders/arm-sysreg-mapping-ns.py
@@ -35,7 +35,7 @@
 
 # reflect updated register mappings for ARM ISA
 def upgrader(cpt):
-    if cpt.get('root','isa') == 'arm':
+    if cpt.get('root', 'isa', fallback='') == 'arm':
         for sec in cpt.sections():
             import re
             # Search for all ISA sections
diff --git a/util/cpt_upgraders/armv8.py b/util/cpt_upgraders/armv8.py
index 9da6047093..4390aa1a3a 100644
--- a/util/cpt_upgraders/armv8.py
+++ b/util/cpt_upgraders/armv8.py
@@ -1,6 +1,6 @@
 # Add all ARMv8 state
 def upgrader(cpt):
-    if cpt.get('root','isa') != 'arm':
+    if cpt.get('root', 'isa', fallback='') != 'arm':
         return
     import re
     print("Warning: The size of the FP register file has changed. "
diff --git a/util/cpt_upgraders/isa-is-simobject.py b/util/cpt_upgraders/isa-is-simobject.py
index 72c62568ac..f6aa63d35b 100644
--- a/util/cpt_upgraders/isa-is-simobject.py
+++ b/util/cpt_upgraders/isa-is-simobject.py
@@ -1,7 +1,9 @@
 # The ISA is now a separate SimObject, which means that we serialize
 # it in a separate section instead of as a part of the ThreadContext.
 def upgrader(cpt):
-    isa = cpt.get('root','isa')
+    isa = cpt.get('root', 'isa', fallback='')
+    if isa == '':
+        return
     isa_fields = {
         "arm" : ( "miscRegs" ),
         "sparc" : ( "asi", "tick", "fprs", "gsr", "softint", "tick_cmpr",
diff --git a/util/cpt_upgraders/remove-arm-cpsr-mode-miscreg.py b/util/cpt_upgraders/remove-arm-cpsr-mode-miscreg.py
index be3bf07b53..73256e1e94 100644
--- a/util/cpt_upgraders/remove-arm-cpsr-mode-miscreg.py
+++ b/util/cpt_upgraders/remove-arm-cpsr-mode-miscreg.py
@@ -1,6 +1,6 @@
 # Remove the MISCREG_CPSR_MODE register from the ARM register file
 def upgrader(cpt):
-    if cpt.get('root','isa') == 'arm':
+    if cpt.get('root', 'isa', fallback='') == 'arm':
         for sec in cpt.sections():
             import re
             # Search for all ISA sections
diff --git a/util/cpt_upgraders/x86-add-tlb.py b/util/cpt_upgraders/x86-add-tlb.py
index db465d512c..0109f5d35a 100644
--- a/util/cpt_upgraders/x86-add-tlb.py
+++ b/util/cpt_upgraders/x86-add-tlb.py
@@ -1,6 +1,6 @@
 # Add TLB to x86 checkpoints
 def upgrader(cpt):
-    if cpt.get('root','isa') == 'x86':
+    if cpt.get('root', 'isa', fallback='') == 'x86':
         for sec in cpt.sections():
             import re
             # Search for all ISA sections