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arch-arm: Add a shared L2 TLB to the default ArmMMU

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JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I542c287a99c8b277afb4cd939c09521798dcf2f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48150
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2021-07-08 14:46:02 +01:00
parent fb0929b5f9
commit 79b57bbfb8
1 changed files with 6 additions and 2 deletions
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8
src/arch/arm/ArmMMU.py
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@@ -63,8 +63,12 @@ class ArmMMU(BaseMMU):
cxx_class = 'gem5::ArmISA::MMU'
cxx_header = 'arch/arm/mmu.hh'
itb = ArmTLB(entry_type="instruction")
dtb = ArmTLB(entry_type="data")
# L2 TLBs
l2_shared = ArmTLB(entry_type="unified", size=1280)
# L1 TLBs
itb = ArmTLB(entry_type="instruction", next_level=Parent.l2_shared)
dtb = ArmTLB(entry_type="data", next_level=Parent.l2_shared)
sys = Param.System(Parent.any, "system object parameter")