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Author SHA1 Message Date
Giacomo Travaglini
59aed6f3bd dev-arm: Allow IOMMU binding to HDLcd 
Change-Id: I894080e7bd76e7efedef141c937e1561c0c0527c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20841
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-16 09:10:43 +00:00
Giacomo Travaglini
587c94c773 dev-arm: Store the IOMMU reference from within the SMMU::connect 
Change-Id: I35718a71dc040ee4acad9eee2a07076ebb571304
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20840
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-13 08:14:24 +00:00
Giacomo Travaglini
3d494d763d dev: Enable DTB IOMMU binding with a DMA object 
This happens by storing a iommu reference in the dma device, and by
calling the addIommuProperty method once doing dtb autogeneration for
the device

Change-Id: Ibd585addac686a9eeaba6959f459d81901087549
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20839
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-13 08:14:24 +00:00
Gabe Black
b87670f172 sparc: Fix a warning/error in tlb.cc. 
gcc has started to not like memseting an ojbect to zero in some cases.
Cast the TlbEntry pointer to a void * before memsetting it to placate
gcc.

Change-Id: Iccb3c326fdb82f1f111329ff1a80bb6719cace47
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20830
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
 2019-09-13 00:55:25 +00:00
Gabe Black
c9fabe1179 dev: Generalize the x86 int source/sink pins. 
Sink pins are now templated based on the underlying device types, and
the pins themselves are based on the new, generalized Port mechanism.

Change-Id: I09c678c56f6eb6b4a167c12f221ae0241fe99c2d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20700
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-12 20:36:39 +00:00
Daniel R. Carvalho
8f0efe340b mem-cache: Fix BDI size calculation 
The bitmask field indicates to which base a delta refers, and in
the original paper it is fixed and proportional to the highest
number of bases allowed in the compressed data.

Change-Id: I271bf2e19e0765de52b933eaf6d4fcc2ce25d185
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19748
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-12 19:40:58 +00:00
Daniel R. Carvalho
28c8fa0454 base: Add a perfect bloom filter 
Add a bloom filter that keeps track of all observed entries, and
thus has no false negatives nor false positives.

Change-Id: Iba784e617a99c77554c688470d9b9e12c260f23b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18879
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
 2019-09-12 19:40:47 +00:00
Tommaso Marinelli
904784fb1e stats: Add M5_VAR_USED to variable 
Fixes compile error for gem5.fast due to unused variable.

Change-Id: Ib1664b100e95a741174610f8cdbdebaff9635f66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20759
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-10 19:02:08 +00:00
Andreas Sandberg
eb920362ae stats: Fix incorrect name conflict panic with grouped stats 
Info::setName() performs a sanity check to ensure that the same stat
name isn't used twice. This doesn't work for new-style stats with a
parent group since the name is only unique within the group. Disable
the check for new-style stats since these usually use names generated
from member variable names.

Change-Id: I590abe6040407c6a4fe582c0782a418165ff5588
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20760
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-10 15:55:50 +00:00
Chun-Chen TK Hsu
ebc1caf9e8 stats: Ignore non-Group objects in stat hierarchy 
Some objects, such as SystemC modules, are not a subclass of
Stat::Group. Calling the addStatGroup function on them causes errors.
This changes ignores those objects that are not Stat::Group in the stat
hierarchy.

Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Change-Id: I9b62419417b7af7331461fbfaf15e45a4ee2b35f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20680
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-10 10:01:24 +00:00
Daniel R. Carvalho
946250181a base: Make Bloom Filter counting by default 
Since a boolean bool filter is a saturating bloom filter with a
single bit per entry, generalize them by using SatCounter instead
of int for the filter entries.

Change-Id: I7f54e28d54de5671e0770b02ed9161735e6bd339
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18877
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
 2019-09-10 07:00:09 +00:00
Daniel R. Carvalho
f20624fd6c base: Make Bulk inherit from MultiBitSel Bloom Filter 
Cleanup bulk's code and make it inherit from MultiBitSel.

Change-Id: I83154feb30bb3dac3d02743bcafbdcb57489c2fd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18876
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
 2019-09-10 07:00:09 +00:00
Daniel R. Carvalho
8d65e51f7f mem-ruby: Move Bloom Filters to base 
All Bloom Filters are completely independent of Ruby, and
therefore can be used everywhere.

As a side effect, Ruby was not using the filters, so
their dependency was removed.

Change-Id: Ic5f430610c33c0791fb81c79101ebe737189497e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18875
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
 2019-09-10 07:00:09 +00:00
Gabe Black
9b9045bb67 mem: Mark MemObject as deprecated. 
It's constructor will now warn that it's deprecated and suggest using
ClockedObject directly. This change also gets rid of the params()
method and the Params typedef since they are functionally equivalent to
the ClockedObject versions.

It also removes the include of mem/port.hh which is not used in
mem_object.hh. This may break code which purposefully or (more likely)
accidentally depended on that transitive include from mem_object.hh.

Change-Id: I6dab3ba626e3f3ab6a6bd86edcf4f5cb4d6d2c45
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20720
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-10 03:39:57 +00:00
Giacomo Travaglini
a04da61ce1 dev-arm: Reset HPPI when clearing an LPI 
Change-Id: I2a69e6cef69aa48d7c265d59915b859e5eac2bcc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20638
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Giacomo Travaglini
bd2d851548 dev-arm: Add resetHppi method in the GICv3 cpu interface 
The method is used for resetting the highest priority pending interrupt
interrupt from the cpu interface if it matches the intid passed as an
argument.

Change-Id: I9fbc4cb3e05a1cc32f853b6afab5c2bc99369435
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20637
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Giacomo Travaglini
8ea1bd8ad0 dev-arm: Cleanup GICv3 initialization 
This patch is removing the unnecessary initState() / reset() methods
from GICv3 classes, since we can initialize everything at
construction/init time

Change-Id: Ia70edcc4ca4f11878fac0024342e4f2cd81883a0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20636
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Giacomo Travaglini
e5e1d85bbb dev-arm: Initialize GICD_TYPER once at construction time 
Change-Id: Ib4dfdf7005709c22b4ba95099b1192f6edd6ff06
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20635
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Giacomo Travaglini
0004a6a060 dev-arm: Writes to IGRPEN1_EL3 triggering update 
Change-Id: I56804eb1bfc8913bd0d3cab05865a382bf270bc1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20634
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Giacomo Travaglini
59370dde2e dev-arm: Fix GICv3 ITS cmdq wrapping 
Change-Id: I979e8d1378d5b5d2647158798479cf4238f2c349
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20633
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Giacomo Travaglini
54e6625546 dev-arm: Fix mapping between IGRPEN1_EL3 and IGRPEN1_EL1 
Previous mapping was wrong because it was checking which security bits
it was accessing by using the inSecureState() function, whereas it
should have used the isSecureBelowEL3().  This patch is not making the
sostitution since it is optimizing the mapping furthermore by avoiding
updating both IGRPEN1_EL1 and  IGRPEN1_EL3 on writes.  The IGRPEN1_EL1
register is used as a storage, and any reads/writes to IGRPEN1_EL3 is
routed to that register.

Change-Id: Id318ec44e19d4f844e4e3410d74d0c4f89810811
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20632
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Giacomo Travaglini
5aa85f38cb dev-arm: Implement message-based SPIs 
Change-Id: I35e79dfd572c3e0d9cadc8e0aab01befd6004ece
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20631
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Gabe Black
37551510ea dev: Scrub out some lingering uses of MemObject. 
MemObject doesn't do anything any more, and is basically just an alias
for ClockedObject.

Change-Id: Ic0e1658609e4e1d7f4b829fbc421f222e4869dee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20719
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-09 01:54:36 +00:00
Giacomo Travaglini
286b6267af dev-arm: Add GICD_SGIR register 
The Distributor Software Generated Interrupt Register is implemented
only if affinity routing is disabled. Since this configuration is
currently not supported in gem5, it has to be treated as RES0.

Change-Id: I9ffcb31b26fc17547f74a4f1d43ce72c59786fa8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20630
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-07 12:12:55 +00:00
Gabe Black
e87a293d1f python: Make the dot writer handle unconnected Port vector elements. 
Change-Id: I5234013716cdcce5fc39e239dc3d92cd1f2b7799
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20699
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-07 01:58:40 +00:00
Giacomo Travaglini
1c72e90e4e dev: Enable Terminal output's dump to stdout 
While the default option is to dump the Terminal content in a file (e.g.
m5out/system.terminal), with this patch it will be possible to choose to
dump it to standard output.

Change-Id: If51c2fd671fa3eb0867a855b5f7d3b0df9cad025
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20639
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-06 20:01:25 +00:00
Giacomo Travaglini
e7c75d2c11 dev-arm: State update when setting MISCREG_ICC_IGRPENx register 
This is because by enabling ainterrupt group at the cpu interface, we
need to check if a previously pending interrupt needs to be forwarded to
the PE.
We are doing the same when globally enabling irqs in the distributor
(GICD_CTLR).

Change-Id: I80aeb87b2a58a108de899006d5a2f12eadbe6c2e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20629
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 20:00:34 +00:00
Giacomo Travaglini
2a818db77a arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 banking 
Change-Id: Ic08ac1e7f3ebef408a83aa068ce15e9dfe2aa3cd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20628
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 20:00:34 +00:00
Giacomo Travaglini
34f1b771ed arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 banking 
Change-Id: Ide93464f62288fbe8f409f718487a15512c01295
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20627
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 20:00:34 +00:00
Giacomo Travaglini
22273000d0 arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking 
Change-Id: Ib1691f1cba08251a36ceb959849b61c33cc3e93b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20626
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 20:00:34 +00:00
Giacomo Travaglini
1e1d5e247e arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking 
Change-Id: Ib30c7a49490f05f88ddfd7572dd360cb92647f81
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20625
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 20:00:34 +00:00
Giacomo Travaglini
96fdb20871 dev-arm: Add read/writeBanked helpers to GICv3 
These will be used by AA64 security banked registers in GICv3.

Change-Id: Ia980c4f5c14187ab9c18da1d1d596562644111ae
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20624
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 20:00:34 +00:00
Giacomo Travaglini
982a7d4f13 arch-arm: Add explicit AArch64 MiscReg banking 
Change-Id: I89836d14491a51b1573f45c8012e3ad12b107d24
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20623
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 20:00:34 +00:00
Giacomo Travaglini
2d2f51f989 arch-arm: Use same template across all MSR inst 
Change-Id: Ifb9f1db288e401761b71ccf426e370c475e5663f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20622
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 20:00:34 +00:00
Giacomo Travaglini
d1251cd2c6 arch-arm: SySDC64 Instructions (CMO) using MiscRegIndex 
Change-Id: Ia66d6abf965b1d33579e8fa048608d99c93ff2ce
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20621
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-06 19:59:58 +00:00
Chun-Chen TK Hsu
665b67e365 dev: Fix segmentation fault in VirtIOBlock 
GEM5 got a segmentation fault when the size is large in
VirtIOBlock::write. This change uses a vector to avoid this segmentation
fault.

Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Change-Id: I26272686a6e7e39cdf2389657ecd38ce90261144
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20679
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 16:14:30 +00:00
Ciro Santilli
36a575071c arch-arm: fix GDB stub after SVE 
The SVE patches made registers longer by increasing NumVecElemPerVecReg,
but the GDB XML was not updated to account for that, and as a result GDB
connections were failing with:

Remote 'g' packet reply is too long

This commit introduces NumVecElemPerSimdVecReg which counts only the SIMD
register sizes to get it back working. SVE GDB support is not added here.

Change-Id: I4191b9f1999ae02b0308863db4cc9b5b16a27d6d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20468
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 15:00:35 +00:00
Giacomo Travaglini
ead1e7a2a3 dev-arm: Rewrite ICC_BPR0/ICC_BPR1 handling 
The patch is fixing BPR reads in AA32, by removing the line

Gicv3::GroupId group =
    misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;

Where a read to ICC_BPR0 will return a G1S group.
The patch is also fixing Security banking accesses.

Change-Id: I28f1d1244c44d4b8b202d3141f8380943c7c1c86
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20620
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 11:53:49 +00:00
Giacomo Travaglini
51022bfe0e dev-arm: Add GICv3 unimplemented Hyp Active Priorities Group regs 
ICH_APxR1, ICH_APxR2, ICH_APxR3 are implemented only if supporting more
than 6 bits of priority. Since this is not the case, they are currently
unimplemented.
According to spec, unimplemented registers are RAZ/WI.

Change-Id: Ifd7f7a3d42b4575c2f7aff3b95d5a47ac1e61842
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20619
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 11:53:49 +00:00
Giacomo Travaglini
7a1f018ce7 dev-arm: Allow 32-bit access to GITS_TYPER 
Change-Id: I9d19174b38ba70f82050102f955ccc162965d1fb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20618
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 11:53:49 +00:00
Giacomo Travaglini
7f89594029 dev-arm: Cpu interface groupEnabled check for global enable 
Gicv3CPUInterface::groupEnabled should check for global enable flags at
distributor level:
- Gicv3Distributor.EnableGrp0
- Gicv3Distributor.EnableGrp1S
- Gicv3Distributor.EnableGrp1NS

Change-Id: I1c855b0e4c2bc8f1cd0a8f086b9450f516177b08
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20617
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 11:53:49 +00:00
Giacomo Travaglini
983f667dc3 dev-arm: Check if INTID group is enabled when reading HPPIRx 
If it is not enabled, it should return INTID_SPOURIOUS

Change-Id: I4dfa8b9fcea874b4d281cd154dd38752b05e1d59
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20616
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 11:53:49 +00:00
Giacomo Travaglini
cad88af5bd dev-arm: Writing GICD_CTLR should trigger an update 
This is the case where an interrupt is pending, but the distributor is
masking it. As soon as the group gets enabled, the interrupt should be
forwarded to the PE.

Change-Id: Ie428780bde7e4726688adf78dfcc4d43d1b45261
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20615
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 11:53:49 +00:00
Giacomo Travaglini
3093d65ad3 dev-arm: Rewrite GICv3 update 
The GICv3 update methods are method which are invoked anytime the model
needs to evaluate a change in its state, which most of the time means
managing the state of an interrupt (forwarding it to a PE, deasserting
it, etc).
The way it is currently done is a little bit obscure and doesn't
handle correctly IRQ prioritization.
Example:
An IRQ which is handled by the redistributor (PPI or LPI) was not
competing with any pending interrupts coming from the distributor (SPIs)
once raised by a peripheral.

Also the way the pending state of an interrupt was removed at the
cpu interface level wasn't happening in place where this was actually
happening (E.g. when activating it), but happened with a weird
fullUpdate semantic, where if there was a pending interrupt in a
cpu interface, all cpu interfaces had their pending interrupt (if any)
been disabled.

With this patch, state update always starts at the distributor, and
it goes down until the cpu interface where a Gicv3CPUInterface::update
method selects the winning interrupt coming from distributor/redistributor
to be forwarded to the PE.

Change-Id: I1c517cbc4bf107cc2d7ae7beb2692e3cf5187a40
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20614
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 11:53:49 +00:00
Giacomo Travaglini
c1458b5d58 dev-arm: Fix GICv3 IGRPMOD writes 
Writes to IGRPMOD were not right shifting the value, which resulted in
interrupts having a IGRPMOD value > 1, whereas the only allowed values
are 0 and 1.

Change-Id: Id491bd1b184d6e5abeeea25ea272eeb91792ccf7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20613
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 11:53:49 +00:00
Giacomo Travaglini
f8ac63a289 arch-arm: SGI registers undecoded in AArch32 
Change-Id: I64d3e639e1beaa507263637d59499aafeb5a19f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20612
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 11:53:49 +00:00
Giacomo Travaglini
2cac191491 arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regs 
The readMiscReg/setMiscReg methods were not forwarding register
reads/writes to the cpu interface when in AArch32.

Change-Id: Ide983e793b8033a88d31fe6ea87eaeffe9b093f5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20611
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-06 11:53:28 +00:00
Giacomo Travaglini
1768c47bc4 dev-arm: Fix SGI generation 
The patch is fixing the following aspects of SGIs

* The conditons over which an SGI can be forwarded to a PE
* SGIs in AArch32 (see below)

It is in fact refactoring SGI generation under a common method in the
cpu interface. It is abandoning the implicit fallthrough mechanism not
only for cosmetic reasons, but also because checking "misc_reg ==" was
only working if the register was an AArch64 one (e.g.
MISCREG_ICC_SGI0R_EL1) and not the AArch32 counterpart (MISCREG_SGI0R).

Change-Id: I6fedfb80388666f4f1d20f6abef378a9f093aa83
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20610
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 08:32:04 +00:00
Adrian Herrera
aec83a6451 dev-arm: Gicv3 ITS device tree autogen 
This patch adds device tree automatic generation for Gicv3 ITS.

Change-Id: Ic01500ffa691b331f527c5c2c785ff715660b0c2
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20609
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 08:32:04 +00:00
Adrian Herrera
69097ceac8 dev-arm: modify GICv3 ITS default addr 
The current default base address for GICv3 ITS stated in RealView is
0x2c120000. The redistributors base address is 0x2c010000; each
instantiated core has an associated redistributor with memory region
size 0x40000 (with GICv4 extension, enabled by default). With 8 cores,
the redistributor range spans to 0x2c210000, creating a conflict with
the ITS address space.

This patch changes the ITS base address to 0x2e010000 which guarantees
no overlapping with the redistributor.

Change-Id: I7dc1af9e69ac037f85ae96f0985554f1fb8372a0
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20608
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 08:32:04 +00:00