Once the switch node in a dist-gem5 simulation gets started it listens
the first available port starting from the initially supplied one.
To bind full system nodes to the switch, the switch logfile
is parsed for the exact port number.
This is fragile and it broke when the following line:
info: tcp_iface listening on port
changed to
build/ARM/dev/net/tcp_iface.cc:97: info: tcp_iface listening on port
This patch is fixing the problem with a more robust regex matching
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I2721b3c04653ac1e09878e80d8b1ea34ec1a0f73
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62512
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The description explains when we have to set this True (when a
downstream cache acts as a victim cache). Also, it describes general
(default) setup, but this seems inaccurate and not consistent with
default vaule.
Change-Id: I389adb0af0d6421e8a9672c4cf5d23510eb38242
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62832
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
By default, caches in classic memory system are assume to be a mostly
inclusive cache with respect to their upstream caches.
Therefore, `writeback_clean` should be `False` by default, which is
consistent with src/mem/cache/Cache.py
Change-Id: I1395690f7f5fafee7fb151906302877ada953861
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62831
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Theses improvements are:
1. Renames the test suite to the correct "ResourceDownloaderTestSuite".
This was correctly named MD5FileTestSuite due to a copy-and-paste
error.
2. Adds the `setUpClass` and `tearDownClass` from the Python's unittest
framework. These are used to create the simple "resources.json" file
used for testing, set the "GEM5_RESOURCE_JSON", and delete these when
the test is complete.
3. The tests have been updated to utilize the improvements added in 2.
Change-Id: Ia54e45892452bf23b54c8b5a6bb4a94910d83c5f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62651
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit adds the concept of a "Workload" to the stdlib. Workloads
specify the details needed to run a particular gem5 workload on an
stdlib board. These are specified as part of gem5-resources and loaded
via the `Workload` class though can be specified locally via the
`CustomWorkload` class.
Tests are included in this commit to verify the functionality of these
Workloads.
Change-Id: I8840d281eb01ee4138f01ee499cae96bf7e0579d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62532
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This change adds a component for HBM2 stack in the gem5 stdlib.
For HBM2 stack, the atom size is used to interleave across pseudo
channels in a single physical channel or HBMCtrl and the bits
beyond that will be used to interleave across channels/controllers.
Change-Id: I95a279504981a5c000f38c9a6ad0e03484eb258e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61489
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This change adds a flag to MemCtrl to allow disabling
response port's queue size sanity check. This is needed
for cases/tests where you might want to drive the memory
system with a much higher bandwidth, for example as in
HBM2.
Change-Id: If8d621339ce8f3ab92cbe2b94039486705c64fc1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62372
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
An exception was raised if the SwitchableProcessor was setup to
switch to a KVM core from a non-KVM core (i.e., if KVM cores were
present they needed to be the starting core). This was due to a bug in
the Simulator module where the `root.sim_quantum` as not setup for cases
where the SwitchableProcessor was not starting with a KVM core, thus
causing an error when switched to KVM cores.
This has been fixed by modifying the Simulator module to always set
root.sim_quantum. This is acceptable as this is only used in KVM setups.
Change-Id: If57352ba67b7bca81882eae2ef1e9013ef45272f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62471
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Without setting the correct memory mode the SimpleSwitchableProcessor,
the Minor CPU could not be used as a valid core. This patch corrects
this issue by setting the memory mode to TIMING for Minor CPU cores.
Due to the increasingly complex if-else to determine the memory mode, a
function has been added to CPUTypes to determine what MemMode is
required for each CPUType.
Change-Id: I9384b4a9c0673af34cca04917d763ca45d0ea434
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61535
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
The `set_se_binary_workload` function was only setting up the binary to
work on one (the first) processor core. This caused an exception to be
thrown when trying to run an SE mode binary on a multicore system.
Tests have been added to ensure this works as intended.
Note: While this implementation fixes the bugs, it is limited. Future
work is needed to allow for multiprogram workloads.
Change-Id: I33dbaf5015705c299215dc83e8449b16df301cd4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62014
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Currently, when using the switchable processor the first N cores are the
starting cores and the next N cores (e.g., board.processor.core<N+1>)
are the switched in cores. This is confusing when looking at the stats.
This change makes it so that the names of the different processor lists
used in the dictionary when constructing the switchable processor are
used in for the member names as well. This will allow users to have
names like board.processor.ff_cores and board.processor.detailed_cores.
A bit of refactoring of the base processor was required for this.
Change-Id: I244ee5f6080599acb60a777da979da048cf7463e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62652
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
This patch does two things:
1. Ensures that both the 'pre-commit' and 'commit-msg' hooks are
installed. The `pre-commit install` by itself will only install the
'pre-commit' hooks. This expanded instlal command will also install
the 'commit-msg' hook.
2. How to run pre-commit to automatically format your code.
Change-Id: I0561f2918568bb9191e4ec457c297fcd264248c0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62573
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The gem5 commit msg checker must be run during the 'commit-msg'
stage ergo this is explicitly set. The other hooks are only applicable
to the "commit" stage, the `default_stage` for the hooks.
To install all the hooks, you need to run the following:
```
pre-commit install -t pre-commit -t commit-msg
```
This ensures both the 'commit-msg' and 'pre-commit' hooks are installed.
If you run just `pre-commit install`, only the pre-commit hooks are
installed.
Change-Id: I4a0dcc7159ed5048baa120adf80bbf65f63c11dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62552
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
In commit 83b14e56, getVirtProxy is replaced by inline ternary operators
to decide between FS or SE version. However, dynamic dispatch will not
work in this scenario and the virtual function of SETranslatingPortProxy
will not be called. It may lead to failure in m5op read_file in SE mode.
Change-Id: I9b5f757096cfdbd6fb8bc14b1b0e02245703a0ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62611
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Glibc requires x86-64-v2 ISA level on newer Linux distributions (e.g.
Debian Bookworm), and running applications in GEM5 will fail with "CPU
ISA level is lower than required" error. It is due to glibc not
detecting CPU features when the vendor string is unknown yet requiring
them to run. For glibc to detect correct CPU features, this commit adds
a command line option to allow user to override x86 cpu vendor string to
well-known ones, e.g. GenuineIntel. It allows glibc to detect more cpu
features and fixes the issue.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1117
Change-Id: I22907e7b983e9aa6122543042af207e35b09badb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62555
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
