Commit Graph

15341 Commits

Author SHA1 Message Date
Richard Cooper
49ae60abe4 misc: Fix util/gem5img.py for new versions of sfdisk
Newer versions of sfdisk have changed the format of the dump output,
as well as the options for partitioning a disk.

Updated the gem5img.py script to work with the new version of sfdisk.
The script should still work with older versions of sfdisk, but this
has not been tested (see https://askubuntu.com/a/819614).

Tested on Ubuntu 18.04.2 LTS with sfdisk from util-linux 2.31.1.

Change-Id: I1197ecacabdd7caaab00327977fb9ab6eae06654
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29472
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-27 10:03:36 +00:00
Gabe Black
7cea164392 systemc: Disable some warnings generating false positives.
These false positives break the build. The error is below, and is bogus
as best I can tell. The constructor for the sc_unsigned and sc_signed
types, defined with some macro goop in sc_nbcommon.inc, have a call to
vec_copy_and_zero to copy over some data and zero the data that isn't
copied. That only happens if the source is smaller than the destination.
Then in vec_copy_and_zero, it calls vec_zero to set the last elements to
zero. Because of the check back at the constructor, only values that
exist should ever be set.

Also, in gem5, SC_MAX_NBITS is not set, so the definition of the array
it's bounds checking is declared right near where it's used and is sized
based on the variable being passed into vec_copy_and_zero.

In file included from build/ARM/systemc/ext/dt/bit/../int/../fx/sc_fxdefs.hh:52,
                 from build/ARM/systemc/ext/dt/bit/../int/sc_length_param.hh:63,
                 from build/ARM/systemc/ext/dt/bit/sc_bv_base.hh:56,
                 from build/ARM/systemc/dt/int/sc_unsigned.cc:83:
In function 'void sc_dt::vec_zero(int, int, sc_dt::sc_digit*)',
    inlined from 'void sc_dt::vec_copy_and_zero(int, sc_dt::sc_digit*, int, const sc_digit*)' at build/ARM/systemc/ext/dt/bit/../int/../fx/../int/sc_nbutils.hh:407:13,
    inlined from 'sc_dt::sc_unsigned::sc_unsigned(sc_dt::small_type, int, int, sc_dt::sc_digit*, bool)' at build/ARM/systemc/dt/int/sc_nbcommon.inc:2285:26:
build/ARM/systemc/ext/dt/bit/../int/../fx/../int/sc_nbutils.hh:379:14: error: 'void* __builtin_memset(void*, int, long unsigned int)' offset [12, 15] is out of the bounds [0, 12] [-Werror=array-bounds]
  379 |         u[i] = 0;
      |

Change-Id: Ica721178b24de56dbeabf4af7d3422dea6336a23
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29432
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-26 02:24:20 +00:00
Gabe Black
1e2f4a8aa6 sim: Fix a possible memory error in copyOutStatfsBuf.
When memcpy-ing, we need to be sure not to read beyond the end of the
source, or write beyond the end of the target.

Change-Id: I3cf259bedce4c6e88aef47ef5379aab198338cb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29404
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-26 00:12:10 +00:00
Gabe Black
ce8a6a0cec sim: Fix the Ticked class constructor's event wrapper.
This uses a "name()" method which is not defined by the Ticked class,
and isn't a global method. This was probably originally supposed to be
the name() method of the Serializable class that Ticked inherits from,
but a while ago that was removed. It's not clear how this has been
compiling.

Instead, use the name() method of the ClockedObject which is the first
constructor argument.

Change-Id: Icfb71732c58ea9984ef7343bbaa46097a25abf28
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29406
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-25 21:21:33 +00:00
Gabe Black
997b74166b cpu: Fix a = that was supposed to be a == in an assert.
The KVM CPU has a _status field which is checked by an assert, but
rather than checking it with an ==, it accidentally used a =.

Change-Id: Ic1970d232786af6666c4ec2719c70f3f1509277c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29405
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-25 21:05:41 +00:00
Gabe Black
72ed8c6e76 sim,dev: Get rid of the global retryTime constant.
This constant isn't in normalized units, ie doesn't scale when the time
value of a Tick changes, is global, has an extremely generic name even
though it's only used by a few ethernet devices, and has an arbitrary
value.

Get rid of it, and replace it with 1ns, what it would typically be
equivalent to when using the default 1ps time scale.

Change-Id: I31d9dad438f854b4152cd53c9a7042a25d13e0a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29398
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-25 12:44:38 +00:00
Gabe Black
1425640eda cpu: Remove the ancient do_quiesce config option.
This option has existed for a very long time, defaults to True, and is
not used in any of the checked in configs. It enables the "quiesce"
mechanism, originally just pseudo instructions, and it's not clear
why you'd ever want to turn it off.

Change-Id: I92c7e5af22157e8435c7326634857d30bb5d7254
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25143
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-23 07:04:59 +00:00
Polydoros Petrakis
7695a21404 mem-garnet: Remove extraneous loop in Router resetStats.
This outer loop makes no sense.

Change-Id: Ibe4b8b50c5843fba2119906f59ea1cb6c1d8c762
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29254
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-21 20:56:49 +00:00
Polydoros Petrakis
8fdad96b7c mem-garnet,mem-ruby: Properly reset garnet2.0 statistics.
Statistics for crossbar activity, and link related statistics were not getting reset when using m5_reset_stats.

Change-Id: Ib84c55200e4a86c6f9190de28498112bd43dde9d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29253
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-21 20:56:25 +00:00
Kyle Roarty
fc5e23c5c7 util: Add dockerfile for GCN3 w/machine learning
This dockerfile creates an image that installs the software stack needed
to run both machine learning and non-machine learning applications using
the GCN3 gpu model, while also applying patches to the software stack to
optimize machine learning applications, as well as APUs, which is the
current type of GPU in the GCN3 GPU model.

Change-Id: If36c2df1c00c895e27e9d741027fd10c17bf224e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29192
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-21 05:30:38 +00:00
Ciro Santilli
a3b329a773 tests: add ruby_mem_test.py to the tests
This catches ruby functional memory errors we have observed, and ensures
that ruby_mem_test.py itself won't be broken.

The test duration is about 10 seconds, and it can be run as:

./main.py run --uid SuiteUID:tests/gem5/test_ruby_mem_test.py:test-ruby\
_mem_test-NULL-x86_64-opt

Change-Id: I39bc559aaea3ebb41217a96cd4e8dae46271ea1f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26805
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-20 10:09:14 +00:00
Michiel W. van Tol
2bceeaafb4 python: Make DOT config generation optional
By default, DOT configs are always generated when pydot is present.
This change allows a user to pass an empty --dot-config='' to disable
generating the DOT configuration. This can be useful to save space, or
to reduce Gem5 startup time when running many small regression tests.

This brings the behavior in-line with providing an empty
--dump_config='' and/or --json_config='' which similarly disables
generation of those output files.

Change-Id: I5bf39fda0409b948a8d14f3afa95db8fc78de6ee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29232
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-20 09:20:20 +00:00
Ciro Santilli
0767ade61b sim-se: ignore all scheduler related syscalls for arm
With the simplistic syscall emulation fork algorithm that we currently have
of running one thread per call, those calls simply cannot be reasonably
implemented.

However, content can often still work without them.

Change-Id: Iac88dfd055564c47b7a7b6898b7582cf4087f708
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28591
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2020-05-20 07:58:05 +00:00
Ciro Santilli
66e598fa08 sim-se: implement the getcpu syscall
Change-Id: I63a1384646829b8cf68453c42aed6a7d12172787
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28590
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-20 07:58:05 +00:00
Gabe Black
fe974125d6 sim: Add some methods to create derived symbol tables.
These tables are based on passing the symbols in the current table
through some sort of operator function which can chose to add those
symbols, modified versions of those symbols, or nothing at all into a
new symbol table.

The new table is returned as a shared_ptr so its memory will be
managed automatically.

Change-Id: I8809336e2fc2fda63b16a0400536116ca852ca13
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24786
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-20 02:37:54 +00:00
Gabe Black
337c586eab arch,base,cpu,sim: Statically allocate debugSymbolTable.
This singleton object is used thruoughout the simulator. There is
really no reason not to have it statically allocated, except that
whether it was allocated seems to sometimes be used as a signal that
something already put symbols in it, specifically in SE mode.

To keep that functionality for the moment, this change adds an "empty"
method to the SymbolTable class to make it easy to check if the symbol
table is empty, or if someone already populated it.

Change-Id: Ia93510082d3f9809fc504bc5803254d8c308d572
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24785
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-19 22:32:50 +00:00
Gabe Black
c5b2b8e19f arch,base,cpu,kern,sim: Encapsulate symbols in a class.
The SymbolTable class had been tracking symbols as two independent
pieces, a name and an address, and acted as a way to translate between
them. Symbols can be more complex than that, and so this change
encapsulates the information associated with a symbol in a new class.

As a step towards simplifying the API for reading symbols from a
binary, this change also adds a "binding" field to that class so that
global, local and weak symbols can all go in the same table and be
differentiated later as needed. That should unify the current API
which has a method for each symbol type.

While the innards of SymbolTable were being reworked, this change
also makes that class more STL like by adding iterators, and begin
and end methods. These iterate over a new vector which holds all the
symbols. The address and name keyed maps now hold indexes into that
vector instead of the other half of the symbol.

Change-Id: I8084f86fd737f697ec041bac86a635a315fd1194
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24784
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-19 22:32:21 +00:00
Andrea Mondelli
fd580041fe cpu: fixed unused variable on fast binary
When gem5.fast is compiled, an error on a variable
used only for debug purposes is raised:

build/X86/cpu/o3/mem_dep_unit_impl.hh:262:19: error: unused variable 'producing_store' [-Werror=unused-variable]
         for (auto producing_store : producing_stores)

This patch remove the variable when *.fast is used.

Change-Id: Ib77c26073db39644e3525bc16edcb7d3bc871d76
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29252
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-05-19 11:29:29 +00:00
Tiago Mück
2b63ba5700 cpu-minor: fix store-release issuing
Store with release flag are treated like store conditionals and are not
bufferable. Also they are only sent when the store buffer is empty to
satisfy the release semantics.

Change-Id: I253ec5ecd39901b14d0dc8efbc82cf7e4b07f08f
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27135
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
2020-05-19 02:17:06 +00:00
Tiago Mück
24dbb7ab93 cpu-o3: fix store-release issuing
Requests from stores with release semantics are only issued when they
are at the head of the store queue.

Change-Id: I19fbceb5ee057d3aa70175cbeec6b9b466334e8c
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27134
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
2020-05-19 02:17:06 +00:00
Tiago Mück
aca00c0645 arch-arm: Using acquire/release memory flags
Appends the acquire/release memory flags for the instructions with those
semantics.

Change-Id: I9d1e12c6ced511f2ff7a1006c27ae9014965e044
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27133
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2020-05-19 02:17:06 +00:00
Gabe Black
e850d3f4c7 util: Pull argument parsing functions out of m5.c.
Make them available in other files as well.

Change-Id: I3ddaed1a06023f929acc95c90f8f9adda7ff429c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27243
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
2020-05-18 04:03:38 +00:00
Matthew Poremba
27426fab83 mem: Remove infinite queue between Ruby and memory
AbstractController sends requests using a QueuedMasterPort which has an
implicit buffer which is unbounded. Remove this by changing the port to
a MasterPort and implement a retry mechanism for AbstractController.
Although the request remains in the MessageBuffer if a retry is needed,
the additional retry logic optimizes serviceMemoryQueue slightly and
prevents the DRAMCtrl retry stats from being incorrect due to multiple
calls to sendTimingReq.

Change-Id: I8c592af92a1a499a418f34cfee16dd69d84803ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28387
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-12 21:12:21 +00:00
Gabe Black
1e4a6b32b4 arm,x86,sim: Use the new return value suppression in GuestABI.
This gets rid of some dummy Return structure definitions. Also augment
the PseudoInst::pseudoInst dispatch function so it can store or not
store results, depending on what's needed at each call sight.

Change-Id: If4a53bc0a27e5214a26ef1a100c99948ca95418d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28289
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-12 16:32:09 +00:00
Gabe Black
6554a9f181 sim: Convert GuestABI example signatures to comments.
In the base Result and Argument templates, there were private static
functions which weren't meant to be used, but which would act as
documentation for what those functions should look like. They were
marked as private to prevent them from being accidentally used and
causing confusing, hard to debug errors.

Unfortunately, that also meant that those functions exist, and
apparently cause inconsistent problems with SFINAE. I assume if the
functions don't exist at all, then SFINAE will work properly. When
they're private, that seems to cause a substitution failure which
actually is an error which makes the build fail.

Change-Id: I326e9e1d05eafe1b00732ae10264354b07426e74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28308
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-12 16:32:09 +00:00
Matthew Poremba
3d57eaf9f5 gpu-compute,mem-ruby: Refactor GPU coalescer
Remove the read/write tables and coalescing table and introduce a two
levels of tables for uncoalesced and coalesced packets. Tokens are
granted to GPU instructions to place in uncoalesced table. If tokens
are available, the operation always succeeds such that the 'Aliased'
status is never returned. Coalesced accesses are placed in the
coalesced table while requests are outstanding. Requests to the same
address are added as targets to the table similar to how MSHRs
operate.

Change-Id: I44983610307b638a97472db3576d0a30df2de600
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27429
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-11 21:25:19 +00:00
Giacomo Travaglini
2f9cc04a5f arch-arm: SVE instruction in EL1s cannot be trapped to EL2
haveVirtualization() is not a valid check on its own:
We need to check if EL2 trapping is currently supported and this
can only happen if we are in NS state or if SecEL2 is implemented

Change-Id: Ie2312caba1ac0f186a2a3305c55a23c7705ba3fd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28769
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-09 21:35:44 +00:00
Giacomo Travaglini
0b7e0199fb arch-arm: CPTR.FPEN controlling SVE enablement
CheckSveEnabled shouldn't check for .ZEN only.
SVE instructions require Advanced SIMD to be supported as
well (CPTR.FPEN) with the caveat of ZEN check having priority
over the FPEN.

Change-Id: Ia1b5f7df3e25e7ffcad472542cb973635f62637b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28768
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-09 21:35:44 +00:00
Giacomo Travaglini
5aff442c76 arch-arm: Remove checkSveTrap method
This is not part of the arm arm pseudocode and prevents a proper
fix of the checkSveEnabled

Change-Id: I075749095316e59e395d5b84a23db4309bdd7a92
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28767
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-09 21:35:44 +00:00
Tiago Mück
e2a5063e5f cpu-o3: MemDepUnit tracks load-acquire/store-release
MemDepUnit tracks loads/stores that are also barriers, which is the case
of load-acquire / store-release instructions. The tracking logic is also
extended to consider multiple outstanding barriers.

Change-Id: I95b0c710d7c7e4a138492177e3eaaf5143e9a0ba
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27132
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-08 20:25:12 +00:00
Jordi Vaquero
3eab6ea51e arch-arm: Fix SVE indx inst by sizeof error and dest overwrite
This patch includes two fixes for SVE FMUL; FMLA FMLS AND FCMLA instructions

+ Fixes indexed functions like FMUL, FMLA, FMLS, FCMLA due to its
destination register overwrite with temporary values, wince the imm
can make changes in vector positions that will be read in the future.

+ sizeof return bytes not bits so division of 128 shouild be of 16 instead

Change-Id: I304d1b254a299069c85bbc3319e5a6d4119436d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28228
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-07 08:01:23 +00:00
Tiago Mück
d9cb548d83 mem-ruby: fix possible MOESI_CMP deadlock
Freeing the L2 block only after local invalidates are acked in the OLSF
state may lead to a deadlock.

Change-Id: Ia4b60e5bc9e2d3315b874a8c6616478db6eb38c1
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21929
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-06 14:42:33 +00:00
Tiago Muck
a0130e741b mem-ruby: Fixed MOESI_CMP_directory resource tracking
Fixes a few resource allocation issues in the directory controller:

- Added TBE resource checks on allocation.
- Now also allocating a TBE when issuing read requests to the controller
  to allow for a better response to backpressure. Without the TBE as a
  limiting factor, the directory can have an unbounded amount of
  outstanding memory requests.
- Also allocating a TBE for forwarded requests.

Change-Id: I17016668bd64a50a4354baad5d181e6d3802ac46
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21928
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
2020-05-06 14:42:33 +00:00
Tiago Muck
8ec2abb98a mem-ruby: fix MOESI_CMP_directory functional reads
This patch properly sets the access permissions in all controllers.
'Busy' was used for all transient states, which is incorrect in lots of
cases when we still hold a valid copy of the line and are able to handle
a functional read.

In the L2 controller these states were split to differentiate the access
permissions:
IFGXX -> IFGXX, IFGXXD
IGMO -> IGMO, IGMOU
IGMIOF -> IGMIOF, IGMIOFD

Same for the dir. controller:
IS -> IS, IS_M
MM -> MM, MM_M

The dir. controllers also has the states WBI/WBS for lines that have
been queued for a writeback. In these states we hold the data in the TBE
for replying to functional reads until the memory acks the write and we
move to I or S.

Other minor changes includes updated debug messages and asserts.

Change-Id: Ie4f6eac3b4d2641ec91ac6b168a0a017f61c0d6f
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21927
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-06 14:42:33 +00:00
Tiago Muck
5abac60ccf mem-ruby: Fix MOESI_CMP_directory DMA handling
This patch fixes some issues in the directory controller regarding DMA
handling:

1) Junk data messages were being sent immediately in response to DMA reads
for a line in the S state (one or more sharers, clean). Now, data is
fetched from memory directly and forwarded to the device. Some existing
transitions for handling GETS requests are reused, since it's essentially
the same behavior (except we don't update the list of sharers for DMAs)

2) DMA writes for lines in the I or S states would always overwrite the
whole line. We now check if it's only a partial line write, in which case
we fetch the line from memory, update it, and writeback.

3) Fixed incorrect DMA msg size

Some existing functions were renamed for clarity.

Change-Id: I759344ea4136cd11c3a52f9eaab2e8ce678edd04
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21926
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
2020-05-06 14:42:33 +00:00
Tiago Muck
b85235b5da mem-ruby: Missing transition in MOESI_CMP_directory
Change-Id: I3aa9cd0230c141128ef5bddc728775b1ea6bbe14
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21925
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-06 14:42:33 +00:00
Tiago Mück
a72eb993e8 mem-ruby: removed unused checkCoherence
Change-Id: I108b95513f2828470fe70bad5f136b0721598582
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21924
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-06 14:42:33 +00:00
Tiago Mück
daa3dc556e mem-ruby: removed checkCoherence from MOESI_CMP_directory
The implementation is empty and this is not used by other protocols

Change-Id: Iaed7d6d4b7ef1eb4cd47bdc0710dc9dbb7a86a0c
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21923
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-06 14:42:33 +00:00
Tiago Mück
8213cbcc97 mem-ruby: Removed invalid transition from MOESI_CMP dir
When memory data is received we always have a valid directory
entry or are in a transient state.

Change-Id: I0e9120e320c157fd306909458cbc446275a4f738
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27848
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
2020-05-06 14:42:33 +00:00
Tiago Mück
852198cd7b mem-ruby: Deallocating unused entries in MOESI_CMP dir
Invalid entries are never removed from the directory the Directory
controller. This patch fixes this by deallocating the entries
when they become invalid.

Change-Id: I616686a78c5eddb7748192bf94bb691a4f158cbc
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27847
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
2020-05-06 14:42:33 +00:00
Tiago Mück
9db98e7adb mem-ruby: Deallocating unused entries in MOESI_CMP L2
Invalid entries are never removed from the directories in the L2
controller. This patch fixes this by deallocating the entries
when they become invalid. The NP (not present) state was removed
since it's now equivalent to Invalid.

Change-Id: Id807b341a2aadb06008491545aca614d5a09b8df
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21922
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-06 14:42:33 +00:00
Tiago Muck
f4b4ff8d44 mem-ruby: Check on PerfectCacheMemory deallocate
Allowing deallocate to be called for non-existing blocks may hide
potential bugs.

Change-Id: Ida77e2db1da59d7cdb21d58968e1f17e75eaa6e0
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21921
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-06 14:42:33 +00:00
Tiago Muck
efa6c773b3 mem-ruby: Add deallocate to DirectoryMemory
Change-Id: Ib261ec8b302b55e539d8e13064957170412b752c
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21920
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-06 14:42:33 +00:00
Ciro Santilli
14ca8b58f0 arch-arm: show names on --debug-flags MiscRegs write:
Before this commit it would show only numbers:

Writing to misc reg 19 (19) : 0x74178

and now it also shows the name:

Writing MiscReg lockaddr (19 19) : 0x74178

MiscReg reads were already showing names and are unchanged, e.g.:

Reading MiscReg sctlr_el1 with clear res1 bits: 0x18100800

Change-Id: If46da88359ce4a549a6a50080a2b13077d41e373
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28467
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-05 09:29:15 +00:00
Jordi Vaquero
0860a91b11 arch-arm: FCVTZS instruction returns sign extension
This patch fix Fcvtzs instruction adding sign extension instead of
zero extension

Change-Id: I28cdca432fa6baa8a524de4c431f492f23f0e9a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28229
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-04 21:12:25 +00:00
Daniel R. Carvalho
c764e1b3dc mem-cache: Fixes to PIF prefetcher
The temporal compactor was never initialized.

There were more possible indexes to the prec/succ vectors than
entries, so a block distance of zero would seg fault.

When checking for an address the wrong vector was being used.

From the original paper, "The prediction mechanism searches for
the PC of the accessed instruction in the index table"

Change-Id: I3c3aceac3c0adbbe8aef5c634c88cb35ba7487be
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28487
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-04 10:29:03 +00:00
Giacomo Travaglini
dcd5ca6402 arch-arm: Decode SEVL instruction for A32 and T32 IS
The instruction had been defined but it was not used for AArch32

Change-Id: I2bb106e98647eaa1f4c71fffb541e76ac1688674
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28450
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-04 08:03:45 +00:00
Timothy Hayes
003c08418f mem-ruby: MESI_Three_level prefetcher page crossing
This patch allows MESI_Three_level using the Ruby prefetcher to
safely cross page boundaries by determining if an address is bad
and cannot be mapped to a memory controller.

Change-Id: I675a13dfa6deb5b6a9f986ced5a3130436db911d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28048
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-02 06:50:57 +00:00
Timothy Hayes
203efba46a mem-ruby: MESI_Three_level prefetcher support
Add support for the Ruby stride prefetcher to MESI_Three_Level.

Change-Id: Id68935e2a7d3ccd0e22a59f43a15f167410632a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27715
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-02 06:50:44 +00:00
Timothy Hayes
e61f10740b mem-ruby: MESI_Three_Level LL/SC improvements
This patch fixes the MESI_Three_Level protocols so that it correctly
informers the Ruby sequencer when a line eviction occurs. Furthermore,
the patch allows the protocol to recognize the 'Store_Conditional'
RubyRequestType and shortcuts this operation if the monitored line
has been cleared from the address monitor. This prevents certain
livelock behaviour in which a line could ping-pong between competing
cores.

The patch establishes a new C/C++ preprocessor definition which allows
the Sequencer to send the 'Store_Conditional' RubyRequestType to
MESI_Three_Level instead of 'ST'. This is a temporary measure until
the other protocols explicitely recognize 'Store_Conditional'.

Change-Id: I27ae041ab0e015a4f54f20df666f9c4873c7583d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28328
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-02 06:49:17 +00:00