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cpu-o3: fix store-release issuing

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Requests from stores with release semantics are only issued when they
are at the head of the store queue.

Change-Id: I19fbceb5ee057d3aa70175cbeec6b9b466334e8c
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27134
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
This commit is contained in:
Tiago Mück
2019-07-26 15:06:26 -05:00
parent aca00c0645
commit 24dbb7ab93
1 changed files with 16 additions and 1 deletions
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17
src/cpu/o3/lsq_unit_impl.hh
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@@ -1,6 +1,6 @@
/*
* Copyright (c) 2010-2014, 2017-2019 ARM Limited
* Copyright (c) 2010-2014, 2017-2020 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -753,6 +753,21 @@ LSQUnit<Impl>::writebackStores()
DynInstPtr inst = storeWBIt->instruction();
LSQRequest* req = storeWBIt->request();
// Process store conditionals or store release after all previous
// stores are completed
if ((req->mainRequest()->isLLSC() ||
req->mainRequest()->isRelease()) &&
(storeWBIt.idx() != storeQueue.head())) {
DPRINTF(LSQUnit, "Store idx:%i PC:%s to Addr:%#x "
"[sn:%lli] is %s%s and not head of the queue\n",
storeWBIt.idx(), inst->pcState(),
req->request()->getPaddr(), inst->seqNum,
req->mainRequest()->isLLSC() ? "SC" : "",
req->mainRequest()->isRelease() ? "/Release" : "");
break;
}
storeWBIt->committed() = true;
assert(!inst->memData);