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arch-arm: Using acquire/release memory flags

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Appends the acquire/release memory flags for the instructions with those
semantics.

Change-Id: I9d1e12c6ced511f2ff7a1006c27ae9014965e044
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27133
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
This commit is contained in:
Tiago Mück
2019-07-12 17:35:33 -05:00
parent e850d3f4c7
commit aca00c0645
4 changed files with 12 additions and 4 deletions
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4
src/arch/arm/isa/insts/ldr.isa
View File

@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2010-2011,2019 ARM Limited
// Copyright (c) 2010-2011,2019-2020 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -182,6 +182,7 @@ let {{
self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
self.memFlags.append("Request::ACQUIRE")
# Disambiguate the class name for different flavors of loads
if self.flavor != "normal":
@@ -256,6 +257,7 @@ let {{
self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
self.memFlags.append("Request::ACQUIRE")
def emit(self):
# Address computation code

4
src/arch/arm/isa/insts/ldr64.isa
View File

@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2011-2014, 2017, 2019 ARM Limited
// Copyright (c) 2011-2014, 2017, 2019-2020 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -94,6 +94,8 @@ let {{
self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
self.memFlags.append("Request::ACQUIRE")
if self.flavor in ("acex", "exclusive", "exp", "acexp"):
self.memFlags.append("Request::LLSC")

4
src/arch/arm/isa/insts/str.isa
View File

@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2010-2011,2017,2019 ARM Limited
// Copyright (c) 2010-2011,2017,2019-2020 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -190,6 +190,7 @@ let {{
self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
self.memFlags.append("Request::RELEASE")
# Disambiguate the class name for different flavors of stores
if self.flavor != "normal":
@@ -271,6 +272,7 @@ let {{
self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
self.memFlags.append("Request::RELEASE")
# Disambiguate the class name for different flavors of stores
if self.flavor != "normal":

4
src/arch/arm/isa/insts/str64.isa
View File

@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2011-2013,2017,2019 ARM Limited
// Copyright (c) 2011-2013,2017,2019-2020 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -82,6 +82,8 @@ let {{
self.instFlags.extend(["IsMemBarrier",
"IsWriteBarrier",
"IsReadBarrier"])
self.memFlags.append("Request::RELEASE")
if self.flavor in ("relex", "exclusive", "exp", "relexp"):
self.instFlags.append("IsStoreConditional")
self.memFlags.append("Request::LLSC")