diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index dc1d650218..d828fcff06 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2010-2011,2019 ARM Limited
+// Copyright (c) 2010-2011,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -182,6 +182,7 @@ let {{
                 self.instFlags.extend(["IsMemBarrier",
                                        "IsWriteBarrier",
                                        "IsReadBarrier"])
+                self.memFlags.append("Request::ACQUIRE")
 
             # Disambiguate the class name for different flavors of loads
             if self.flavor != "normal":
@@ -256,6 +257,7 @@ let {{
                 self.instFlags.extend(["IsMemBarrier",
                                        "IsWriteBarrier",
                                        "IsReadBarrier"])
+                self.memFlags.append("Request::ACQUIRE")
 
         def emit(self):
             # Address computation code
diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa
index 4f1250938e..fc4f34f0cc 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2011-2014, 2017, 2019 ARM Limited
+// Copyright (c) 2011-2014, 2017, 2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -94,6 +94,8 @@ let {{
                 self.instFlags.extend(["IsMemBarrier",
                                        "IsWriteBarrier",
                                        "IsReadBarrier"])
+                self.memFlags.append("Request::ACQUIRE")
+
             if self.flavor in ("acex", "exclusive", "exp", "acexp"):
                 self.memFlags.append("Request::LLSC")
 
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index f5424789c1..e99f6adc42 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2010-2011,2017,2019 ARM Limited
+// Copyright (c) 2010-2011,2017,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -190,6 +190,7 @@ let {{
                 self.instFlags.extend(["IsMemBarrier",
                                        "IsWriteBarrier",
                                        "IsReadBarrier"])
+                self.memFlags.append("Request::RELEASE")
 
             # Disambiguate the class name for different flavors of stores
             if self.flavor != "normal":
@@ -271,6 +272,7 @@ let {{
                 self.instFlags.extend(["IsMemBarrier",
                                        "IsWriteBarrier",
                                        "IsReadBarrier"])
+                self.memFlags.append("Request::RELEASE")
 
             # Disambiguate the class name for different flavors of stores
             if self.flavor != "normal":
diff --git a/src/arch/arm/isa/insts/str64.isa b/src/arch/arm/isa/insts/str64.isa
index 22d1456611..7ad1cad2cc 100644
--- a/src/arch/arm/isa/insts/str64.isa
+++ b/src/arch/arm/isa/insts/str64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2011-2013,2017,2019 ARM Limited
+// Copyright (c) 2011-2013,2017,2019-2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -82,6 +82,8 @@ let {{
                 self.instFlags.extend(["IsMemBarrier",
                                        "IsWriteBarrier",
                                        "IsReadBarrier"])
+                self.memFlags.append("Request::RELEASE")
+
             if self.flavor in ("relex", "exclusive", "exp", "relexp"):
                 self.instFlags.append("IsStoreConditional")
                 self.memFlags.append("Request::LLSC")