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mem-ruby: MESI_Three_level prefetcher page crossing

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This patch allows MESI_Three_level using the Ruby prefetcher to
safely cross page boundaries by determining if an address is bad
and cannot be mapped to a memory controller.

Change-Id: I675a13dfa6deb5b6a9f986ced5a3130436db911d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28048
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Timothy Hayes
2020-04-21 18:58:03 +01:00
committed by Pouya Fotouhi
parent 203efba46a
commit 003c08418f
2 changed files with 16 additions and 2 deletions
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2
configs/ruby/MESI_Three_Level.py
View File

@@ -127,7 +127,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
nonunit_filter = 256,
train_misses = 5,
num_startup_pfs = 4,
cross_page = False
cross_page = True
)
l0_cntrl = L0Cache_Controller(

16
src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
View File

@@ -140,6 +140,7 @@ machine(MachineType:L0Cache, "MESI Directory L0 Cache")
PF_Load, desc="Load request from prefetcher";
PF_Ifetch, desc="Instruction fetch request from prefetcher";
PF_Store, desc="Exclusive load request from prefetcher";
PF_Bad_Addr, desc="Throw away prefetch request due to bad address generation";
}
// TYPES
@@ -323,7 +324,16 @@ machine(MachineType:L0Cache, "MESI Directory L0 Cache")
in_port(optionalQueue_in, RubyRequest, prefetchQueue, desc="...", rank = 2) {
if (optionalQueue_in.isReady(clockEdge())) {
peek(optionalQueue_in, RubyRequest) {
if (in_msg.Type == RubyRequestType:IFETCH) {
// first check for valid address
MachineID mid := mapAddressToMachine(in_msg.LineAddress, MachineType:Directory);
NodeID nid := machineIDToNodeID(mid);
int nidint := IDToInt(nid);
int numDirs := machineCount(MachineType:Directory);
if (nidint >= numDirs) {
Entry cache_entry := static_cast(Entry, "pointer", Dcache.getNullEntry());
TBE tbe := TBEs.getNullEntry();
trigger(Event:PF_Bad_Addr, in_msg.LineAddress, cache_entry, tbe);
} else if (in_msg.Type == RubyRequestType:IFETCH) {
// Instruction Prefetch
Entry icache_entry := getICacheEntry(in_msg.LineAddress);
if (is_valid(icache_entry)) {
@@ -1164,4 +1174,8 @@ machine(MachineType:L0Cache, "MESI Directory L0 Cache")
o_popIncomingResponseQueue;
kd_wakeUpDependents;
}
transition(I, PF_Bad_Addr) {
pq_popPrefetchQueue;
}
}